Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1089315730 13093 0 0
auto_block_debounce_ctl_rd_A 1089315730 2136 0 0
auto_block_out_ctl_rd_A 1089315730 3159 0 0
com_det_ctl_0_rd_A 1089315730 3248 0 0
com_det_ctl_1_rd_A 1089315730 3350 0 0
com_det_ctl_2_rd_A 1089315730 3270 0 0
com_det_ctl_3_rd_A 1089315730 3448 0 0
com_out_ctl_0_rd_A 1089315730 4074 0 0
com_out_ctl_1_rd_A 1089315730 4059 0 0
com_out_ctl_2_rd_A 1089315730 3923 0 0
com_out_ctl_3_rd_A 1089315730 4100 0 0
com_pre_det_ctl_0_rd_A 1089315730 1484 0 0
com_pre_det_ctl_1_rd_A 1089315730 1550 0 0
com_pre_det_ctl_2_rd_A 1089315730 1684 0 0
com_pre_det_ctl_3_rd_A 1089315730 1621 0 0
com_pre_sel_ctl_0_rd_A 1089315730 4444 0 0
com_pre_sel_ctl_1_rd_A 1089315730 4307 0 0
com_pre_sel_ctl_2_rd_A 1089315730 4344 0 0
com_pre_sel_ctl_3_rd_A 1089315730 4226 0 0
com_sel_ctl_0_rd_A 1089315730 4292 0 0
com_sel_ctl_1_rd_A 1089315730 4307 0 0
com_sel_ctl_2_rd_A 1089315730 4297 0 0
com_sel_ctl_3_rd_A 1089315730 4282 0 0
ec_rst_ctl_rd_A 1089315730 2422 0 0
intr_enable_rd_A 1089315730 2102 0 0
key_intr_ctl_rd_A 1089315730 5249 0 0
key_intr_debounce_ctl_rd_A 1089315730 1587 0 0
key_invert_ctl_rd_A 1089315730 5224 0 0
pin_allowed_ctl_rd_A 1089315730 6880 0 0
pin_out_ctl_rd_A 1089315730 4807 0 0
pin_out_value_rd_A 1089315730 4478 0 0
regwen_rd_A 1089315730 1807 0 0
ulp_ac_debounce_ctl_rd_A 1089315730 1761 0 0
ulp_ctl_rd_A 1089315730 1708 0 0
ulp_lid_debounce_ctl_rd_A 1089315730 1643 0 0
ulp_pwrb_debounce_ctl_rd_A 1089315730 1853 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 13093 0 0
T1 231959 0 0 0
T2 64358 0 0 0
T3 62001 0 0 0
T5 431686 15 0 0
T6 246261 0 0 0
T10 0 25 0 0
T14 101742 0 0 0
T15 240715 0 0 0
T16 265838 0 0 0
T17 76787 0 0 0
T21 63224 0 0 0
T33 0 11 0 0
T44 0 16 0 0
T54 0 3 0 0
T56 0 9 0 0
T83 0 3 0 0
T86 0 3 0 0
T106 0 7 0 0
T323 0 8 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 2136 0 0
T7 468186 0 0 0
T28 22400 0 0 0
T33 0 34 0 0
T54 0 24 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 36 0 0
T86 400504 12 0 0
T87 50728 0 0 0
T106 0 22 0 0
T125 0 9 0 0
T175 51156 0 0 0
T323 0 24 0 0
T324 0 6 0 0
T325 0 6 0 0
T326 0 8 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 3159 0 0
T7 468186 0 0 0
T28 22400 0 0 0
T33 0 26 0 0
T54 0 16 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 29 0 0
T86 400504 26 0 0
T87 50728 0 0 0
T106 0 33 0 0
T125 0 12 0 0
T175 51156 0 0 0
T323 0 21 0 0
T324 0 8 0 0
T325 0 10 0 0
T326 0 3 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 3248 0 0
T7 468186 0 0 0
T13 0 93 0 0
T28 22400 0 0 0
T33 0 26 0 0
T46 0 30 0 0
T48 0 34 0 0
T54 0 24 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 31 0 0
T86 400504 15 0 0
T87 50728 0 0 0
T106 0 14 0 0
T116 0 60 0 0
T175 51156 0 0 0
T323 0 19 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 3350 0 0
T7 468186 0 0 0
T13 0 53 0 0
T28 22400 0 0 0
T33 0 38 0 0
T46 0 39 0 0
T48 0 37 0 0
T54 0 10 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 40 0 0
T86 400504 19 0 0
T87 50728 0 0 0
T106 0 21 0 0
T116 0 91 0 0
T175 51156 0 0 0
T323 0 27 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 3270 0 0
T7 468186 0 0 0
T13 0 73 0 0
T28 22400 0 0 0
T33 0 27 0 0
T46 0 28 0 0
T48 0 30 0 0
T54 0 24 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 37 0 0
T86 400504 8 0 0
T87 50728 0 0 0
T106 0 16 0 0
T116 0 74 0 0
T175 51156 0 0 0
T323 0 23 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 3448 0 0
T7 468186 0 0 0
T13 0 71 0 0
T28 22400 0 0 0
T33 0 24 0 0
T46 0 42 0 0
T48 0 46 0 0
T54 0 18 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 27 0 0
T86 400504 16 0 0
T87 50728 0 0 0
T106 0 18 0 0
T116 0 72 0 0
T175 51156 0 0 0
T323 0 19 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4074 0 0
T7 468186 0 0 0
T13 0 47 0 0
T28 22400 0 0 0
T33 0 15 0 0
T46 0 25 0 0
T48 0 45 0 0
T54 0 24 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 29 0 0
T86 400504 17 0 0
T87 50728 0 0 0
T106 0 13 0 0
T116 0 71 0 0
T175 51156 0 0 0
T323 0 12 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4059 0 0
T7 468186 0 0 0
T13 0 81 0 0
T28 22400 0 0 0
T33 0 12 0 0
T46 0 19 0 0
T48 0 30 0 0
T54 0 22 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 41 0 0
T86 400504 16 0 0
T87 50728 0 0 0
T106 0 21 0 0
T116 0 76 0 0
T175 51156 0 0 0
T323 0 18 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 3923 0 0
T7 468186 0 0 0
T13 0 73 0 0
T28 22400 0 0 0
T33 0 8 0 0
T46 0 53 0 0
T48 0 25 0 0
T54 0 16 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 24 0 0
T86 400504 21 0 0
T87 50728 0 0 0
T106 0 17 0 0
T116 0 75 0 0
T175 51156 0 0 0
T323 0 27 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4100 0 0
T7 468186 0 0 0
T13 0 79 0 0
T28 22400 0 0 0
T33 0 38 0 0
T46 0 39 0 0
T48 0 31 0 0
T54 0 17 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 25 0 0
T86 400504 8 0 0
T87 50728 0 0 0
T106 0 15 0 0
T116 0 78 0 0
T175 51156 0 0 0
T323 0 21 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 1484 0 0
T7 468186 0 0 0
T28 22400 0 0 0
T33 0 14 0 0
T54 0 22 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 27 0 0
T86 400504 14 0 0
T87 50728 0 0 0
T106 0 26 0 0
T175 51156 0 0 0
T323 0 16 0 0
T326 0 27 0 0
T327 0 14 0 0
T328 0 13 0 0
T329 0 13 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 1550 0 0
T7 468186 0 0 0
T28 22400 0 0 0
T33 0 11 0 0
T54 0 19 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 30 0 0
T86 400504 17 0 0
T87 50728 0 0 0
T106 0 13 0 0
T175 51156 0 0 0
T323 0 16 0 0
T326 0 9 0 0
T327 0 15 0 0
T328 0 11 0 0
T329 0 23 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 1684 0 0
T7 468186 0 0 0
T28 22400 0 0 0
T33 0 20 0 0
T54 0 32 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 32 0 0
T86 400504 29 0 0
T87 50728 0 0 0
T106 0 31 0 0
T175 51156 0 0 0
T323 0 22 0 0
T326 0 11 0 0
T327 0 13 0 0
T328 0 19 0 0
T329 0 15 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 1621 0 0
T7 468186 0 0 0
T28 22400 0 0 0
T33 0 19 0 0
T54 0 20 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 31 0 0
T86 400504 10 0 0
T87 50728 0 0 0
T106 0 23 0 0
T175 51156 0 0 0
T323 0 32 0 0
T326 0 6 0 0
T327 0 22 0 0
T328 0 22 0 0
T329 0 19 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4444 0 0
T7 468186 0 0 0
T13 0 63 0 0
T28 22400 0 0 0
T33 0 37 0 0
T46 0 46 0 0
T48 0 35 0 0
T54 0 21 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 45 0 0
T86 400504 15 0 0
T87 50728 0 0 0
T106 0 14 0 0
T116 0 85 0 0
T175 51156 0 0 0
T323 0 22 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4307 0 0
T7 468186 0 0 0
T13 0 62 0 0
T28 22400 0 0 0
T33 0 10 0 0
T46 0 24 0 0
T48 0 35 0 0
T54 0 31 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 33 0 0
T86 400504 17 0 0
T87 50728 0 0 0
T106 0 36 0 0
T116 0 73 0 0
T175 51156 0 0 0
T323 0 15 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4344 0 0
T7 468186 0 0 0
T13 0 68 0 0
T28 22400 0 0 0
T33 0 17 0 0
T46 0 51 0 0
T48 0 43 0 0
T54 0 31 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 17 0 0
T86 400504 8 0 0
T87 50728 0 0 0
T106 0 32 0 0
T116 0 66 0 0
T175 51156 0 0 0
T323 0 13 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4226 0 0
T7 468186 0 0 0
T13 0 71 0 0
T28 22400 0 0 0
T33 0 23 0 0
T46 0 41 0 0
T48 0 44 0 0
T54 0 15 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 30 0 0
T86 400504 27 0 0
T87 50728 0 0 0
T106 0 22 0 0
T116 0 49 0 0
T175 51156 0 0 0
T323 0 13 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4292 0 0
T7 468186 0 0 0
T13 0 77 0 0
T28 22400 0 0 0
T33 0 43 0 0
T46 0 49 0 0
T48 0 43 0 0
T54 0 26 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 20 0 0
T86 400504 8 0 0
T87 50728 0 0 0
T106 0 22 0 0
T116 0 71 0 0
T175 51156 0 0 0
T323 0 15 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4307 0 0
T7 468186 0 0 0
T13 0 82 0 0
T28 22400 0 0 0
T33 0 41 0 0
T46 0 23 0 0
T48 0 34 0 0
T54 0 18 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 32 0 0
T86 400504 25 0 0
T87 50728 0 0 0
T106 0 18 0 0
T116 0 60 0 0
T175 51156 0 0 0
T323 0 13 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4297 0 0
T7 468186 0 0 0
T13 0 90 0 0
T28 22400 0 0 0
T33 0 23 0 0
T46 0 23 0 0
T48 0 37 0 0
T54 0 21 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 45 0 0
T86 400504 20 0 0
T87 50728 0 0 0
T106 0 11 0 0
T116 0 80 0 0
T175 51156 0 0 0
T323 0 16 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4282 0 0
T7 468186 0 0 0
T13 0 78 0 0
T28 22400 0 0 0
T33 0 21 0 0
T46 0 32 0 0
T48 0 37 0 0
T54 0 16 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 35 0 0
T86 400504 21 0 0
T87 50728 0 0 0
T106 0 21 0 0
T116 0 70 0 0
T175 51156 0 0 0
T323 0 21 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 2422 0 0
T7 468186 0 0 0
T13 0 32 0 0
T28 22400 0 0 0
T33 0 25 0 0
T46 0 4 0 0
T48 0 2 0 0
T54 0 17 0 0
T57 0 2 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 25 0 0
T86 400504 9 0 0
T87 50728 0 0 0
T106 0 17 0 0
T175 51156 0 0 0
T323 0 16 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 2102 0 0
T7 468186 0 0 0
T28 22400 0 0 0
T33 0 17 0 0
T38 0 5 0 0
T54 0 27 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 32 0 0
T86 400504 21 0 0
T87 50728 0 0 0
T106 0 28 0 0
T107 0 37 0 0
T175 51156 0 0 0
T323 0 17 0 0
T326 0 21 0 0
T327 0 3 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 5249 0 0
T3 62001 6 0 0
T17 76787 0 0 0
T18 106996 0 0 0
T19 103754 0 0 0
T20 123431 0 0 0
T33 0 22 0 0
T38 0 3 0 0
T54 0 30 0 0
T83 462246 0 0 0
T84 0 31 0 0
T85 19689 0 0 0
T86 400504 17 0 0
T87 50728 0 0 0
T106 0 41 0 0
T168 0 4 0 0
T169 0 4 0 0
T175 51156 0 0 0
T323 0 23 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 1587 0 0
T7 468186 0 0 0
T28 22400 0 0 0
T33 0 15 0 0
T54 0 20 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 27 0 0
T86 400504 27 0 0
T87 50728 0 0 0
T106 0 30 0 0
T175 51156 0 0 0
T323 0 17 0 0
T326 0 7 0 0
T327 0 24 0 0
T328 0 25 0 0
T329 0 12 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 5224 0 0
T7 468186 0 0 0
T28 22400 0 0 0
T33 0 18 0 0
T54 0 18 0 0
T61 212368 0 0 0
T72 0 63 0 0
T78 0 43 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 26 0 0
T86 400504 17 0 0
T87 50728 0 0 0
T106 0 19 0 0
T175 51156 0 0 0
T323 0 17 0 0
T330 0 77 0 0
T331 0 55 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 6880 0 0
T7 468186 0 0 0
T20 123431 40 0 0
T28 22400 0 0 0
T33 0 71 0 0
T54 0 18 0 0
T61 212368 0 0 0
T70 0 53 0 0
T79 33090 0 0 0
T83 462246 0 0 0
T84 0 39 0 0
T85 19689 0 0 0
T86 400504 20 0 0
T87 50728 0 0 0
T106 0 54 0 0
T175 51156 0 0 0
T323 0 10 0 0
T326 0 12 0 0
T332 0 90 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4807 0 0
T7 468186 0 0 0
T20 123431 52 0 0
T28 22400 0 0 0
T33 0 62 0 0
T54 0 9 0 0
T61 212368 0 0 0
T70 0 73 0 0
T79 33090 0 0 0
T83 462246 0 0 0
T84 0 30 0 0
T85 19689 0 0 0
T86 400504 15 0 0
T87 50728 0 0 0
T106 0 27 0 0
T175 51156 0 0 0
T323 0 35 0 0
T326 0 6 0 0
T332 0 57 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 4478 0 0
T7 468186 0 0 0
T20 123431 61 0 0
T28 22400 0 0 0
T33 0 71 0 0
T54 0 29 0 0
T61 212368 0 0 0
T70 0 66 0 0
T79 33090 0 0 0
T83 462246 0 0 0
T84 0 25 0 0
T85 19689 0 0 0
T86 400504 20 0 0
T87 50728 0 0 0
T106 0 28 0 0
T175 51156 0 0 0
T323 0 12 0 0
T326 0 17 0 0
T332 0 60 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 1807 0 0
T7 468186 0 0 0
T28 22400 0 0 0
T33 0 12 0 0
T54 0 26 0 0
T61 212368 0 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 22 0 0
T86 400504 22 0 0
T87 50728 0 0 0
T106 0 21 0 0
T175 51156 0 0 0
T323 0 21 0 0
T326 0 15 0 0
T327 0 41 0 0
T328 0 13 0 0
T329 0 8 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 1761 0 0
T7 468186 0 0 0
T26 0 6 0 0
T28 22400 0 0 0
T33 0 18 0 0
T54 0 17 0 0
T61 212368 0 0 0
T62 0 4 0 0
T65 0 4 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 37 0 0
T86 400504 24 0 0
T87 50728 0 0 0
T90 0 3 0 0
T106 0 14 0 0
T175 51156 0 0 0
T323 0 18 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 1708 0 0
T7 468186 0 0 0
T26 0 4 0 0
T28 22400 0 0 0
T33 0 19 0 0
T54 0 19 0 0
T61 212368 0 0 0
T62 0 4 0 0
T65 0 8 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 26 0 0
T86 400504 14 0 0
T87 50728 0 0 0
T90 0 11 0 0
T106 0 33 0 0
T175 51156 0 0 0
T323 0 9 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 1643 0 0
T7 468186 0 0 0
T26 0 2 0 0
T28 22400 0 0 0
T33 0 15 0 0
T54 0 22 0 0
T61 212368 0 0 0
T62 0 5 0 0
T65 0 8 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 31 0 0
T86 400504 21 0 0
T87 50728 0 0 0
T106 0 14 0 0
T175 51156 0 0 0
T323 0 5 0 0
T333 0 5 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1089315730 1853 0 0
T7 468186 0 0 0
T26 0 9 0 0
T28 22400 0 0 0
T33 0 31 0 0
T54 0 24 0 0
T61 212368 0 0 0
T65 0 1 0 0
T79 33090 0 0 0
T80 121056 0 0 0
T81 51279 0 0 0
T83 462246 0 0 0
T84 0 15 0 0
T86 400504 25 0 0
T87 50728 0 0 0
T106 0 4 0 0
T175 51156 0 0 0
T323 0 22 0 0
T326 0 2 0 0
T334 0 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%