Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T1,T16
1	0	Covered	T4,T1,T16
1	1	Covered	T10,T62,T63

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T1,T16
1	0	Covered	T10,T62,T63
1	1	Covered	T4,T1,T16

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	208935	0	0
SrcPulseCheck_M	2147483647	210974	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	208935
T1	5798959	204
T2	1364978	0
T3	1321841	0
T4	139788	0
T7	0	272
T8	0	170
T9	1804214	85
T10	1387120	0
T11	0	51
T12	0	96
T14	2145062	0
T15	5065035	0
T16	5603838	0
T17	1549080	0
T18	2227260	17
T19	2083540	0
T20	2478680	0
T27	0	16
T29	0	14
T30	0	34
T32	156394	12
T33	1014930	20
T45	0	144
T46	0	13
T47	442134	272
T48	0	2
T49	0	14
T50	0	14
T51	0	12
T52	0	16
T53	0	18
T54	750398	0
T55	282030	0
T56	734564	0
T57	37220	0
T58	483426	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	210974
T1	5613391	204
T2	1301293	0
T3	1260831	0
T4	559	0
T7	0	272
T8	0	170
T9	1804214	85
T10	1387120	0
T11	0	51
T12	0	96
T14	2043744	0
T15	4824821	0
T16	5339062	0
T17	1549080	0
T18	2227260	17
T19	2083540	0
T20	2478680	0
T27	0	16
T29	0	14
T30	0	34
T32	156394	12
T33	1014930	20
T45	0	144
T46	0	13
T47	442134	272
T48	0	2
T49	0	14
T50	0	14
T51	0	12
T52	0	16
T53	0	18
T54	750398	0
T55	282030	0
T56	734564	0
T57	37220	0
T58	483426	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T1,T16
1	0	Covered	T4,T1,T16
1	1	Covered	T35,T36,T366

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T1,T16
1	0	Covered	T35,T36,T366
1	1	Covered	T4,T1,T16

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1859	0	0
SrcPulseCheck_M	1089315730	1920	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1859
T1	46391	12
T2	673	0
T3	991	0
T4	559	1
T5	863	0
T6	502	0
T7	0	17
T8	0	10
T14	424	0
T15	501	0
T16	1062	1
T17	0	1
T18	0	1
T21	526	0
T45	0	9
T47	0	17
T61	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1920
T1	231959	12
T2	64358	0
T3	62001	0
T4	139788	1
T5	431686	0
T6	246261	0
T7	0	17
T8	0	10
T14	101742	0
T15	240715	0
T16	265838	1
T17	0	1
T18	0	1
T21	63224	0
T45	0	9
T47	0	17
T61	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T1,T16
1	0	Covered	T4,T1,T16
1	1	Covered	T35,T36,T366

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T1,T16
1	0	Covered	T35,T36,T366
1	1	Covered	T4,T1,T16

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1912	0	0
SrcPulseCheck_M	6185301	1912	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1912
T1	231959	12
T2	64358	0
T3	62001	0
T4	139788	1
T5	431686	0
T6	246261	0
T7	0	17
T8	0	10
T14	101742	0
T15	240715	0
T16	265838	1
T17	0	1
T18	0	1
T21	63224	0
T45	0	9
T47	0	17
T61	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1912
T1	46391	12
T2	673	0
T3	991	0
T4	559	1
T5	863	0
T6	502	0
T7	0	17
T8	0	10
T14	424	0
T15	501	0
T16	1062	1
T17	0	1
T18	0	1
T21	526	0
T45	0	9
T47	0	17
T61	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T10,T26,T27
1	1	Covered	T62,T63,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T62,T63,T64
1	1	Covered	T10,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	957	0	0
SrcPulseCheck_M	1089315730	1017	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	957
T10	329770	1
T11	12736	0
T12	18567	0
T13	21523	0
T26	0	1
T27	0	1
T46	8570	0
T57	517	0
T58	502	0
T62	0	2
T63	0	3
T64	0	2
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	713	0
T70	502	0
T71	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1017
T10	363790	1
T11	312050	0
T12	157823	0
T13	753308	0
T26	0	1
T27	0	1
T46	728447	0
T57	18093	0
T58	241211	0
T62	0	2
T63	0	3
T64	0	2
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	342521	0
T70	238660	0
T71	48891	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T10,T26,T27
1	1	Covered	T62,T63,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T62,T63,T64
1	1	Covered	T10,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1006	0	0
SrcPulseCheck_M	6185301	1006	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1006
T10	363790	1
T11	312050	0
T12	157823	0
T13	753308	0
T26	0	1
T27	0	1
T46	728447	0
T57	18093	0
T58	241211	0
T62	0	2
T63	0	3
T64	0	2
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	342521	0
T70	238660	0
T71	48891	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1006
T10	329770	1
T11	12736	0
T12	18567	0
T13	21523	0
T26	0	1
T27	0	1
T46	8570	0
T57	517	0
T58	502	0
T62	0	2
T63	0	3
T64	0	2
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	713	0
T70	502	0
T71	407	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T10,T26,T27
1	1	Covered	T62,T63,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T62,T63,T64
1	1	Covered	T10,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	964	0	0
SrcPulseCheck_M	1089315730	1022	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	964
T10	329770	1
T11	12736	0
T12	18567	0
T13	21523	0
T26	0	1
T27	0	1
T46	8570	0
T57	517	0
T58	502	0
T62	0	2
T63	0	3
T64	0	2
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	713	0
T70	502	0
T71	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1022
T10	363790	1
T11	312050	0
T12	157823	0
T13	753308	0
T26	0	1
T27	0	1
T46	728447	0
T57	18093	0
T58	241211	0
T62	0	2
T63	0	3
T64	0	2
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	342521	0
T70	238660	0
T71	48891	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T10,T26,T27
1	1	Covered	T62,T63,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T62,T63,T64
1	1	Covered	T10,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1010	0	0
SrcPulseCheck_M	6185301	1010	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1010
T10	363790	1
T11	312050	0
T12	157823	0
T13	753308	0
T26	0	1
T27	0	1
T46	728447	0
T57	18093	0
T58	241211	0
T62	0	2
T63	0	3
T64	0	2
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	342521	0
T70	238660	0
T71	48891	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1010
T10	329770	1
T11	12736	0
T12	18567	0
T13	21523	0
T26	0	1
T27	0	1
T46	8570	0
T57	517	0
T58	502	0
T62	0	2
T63	0	3
T64	0	2
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	713	0
T70	502	0
T71	407	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T10,T26,T27
1	1	Covered	T62,T63,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T62,T63,T64
1	1	Covered	T10,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	969	0	0
SrcPulseCheck_M	1089315730	1028	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	969
T10	329770	1
T11	12736	0
T12	18567	0
T13	21523	0
T26	0	1
T27	0	1
T46	8570	0
T57	517	0
T58	502	0
T62	0	2
T63	0	3
T64	0	2
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	713	0
T70	502	0
T71	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1028
T10	363790	1
T11	312050	0
T12	157823	0
T13	753308	0
T26	0	1
T27	0	1
T46	728447	0
T57	18093	0
T58	241211	0
T62	0	2
T63	0	3
T64	0	2
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	342521	0
T70	238660	0
T71	48891	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T10,T26,T27
1	1	Covered	T62,T63,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T62,T63,T64
1	1	Covered	T10,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1018	0	0
SrcPulseCheck_M	6185301	1018	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1018
T10	363790	1
T11	312050	0
T12	157823	0
T13	753308	0
T26	0	1
T27	0	1
T46	728447	0
T57	18093	0
T58	241211	0
T62	0	2
T63	0	3
T64	0	2
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	342521	0
T70	238660	0
T71	48891	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1018
T10	329770	1
T11	12736	0
T12	18567	0
T13	21523	0
T26	0	1
T27	0	1
T46	8570	0
T57	517	0
T58	502	0
T62	0	2
T63	0	3
T64	0	2
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	713	0
T70	502	0
T71	407	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T10,T26,T27
1	1	Covered	T10,T26,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T10,T26,T27
1	1	Covered	T10,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	985	0	0
SrcPulseCheck_M	1089315730	1043	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	985
T10	329770	2
T11	12736	0
T12	18567	0
T13	21523	0
T26	0	2
T27	0	2
T46	8570	0
T57	517	0
T58	502	0
T62	0	4
T63	0	4
T64	0	2
T67	0	4
T68	0	2
T69	713	0
T70	502	0
T71	407	0
T90	0	2
T91	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1043
T10	363790	2
T11	312050	0
T12	157823	0
T13	753308	0
T26	0	2
T27	0	2
T46	728447	0
T57	18093	0
T58	241211	0
T62	0	4
T63	0	4
T64	0	2
T67	0	4
T68	0	2
T69	342521	0
T70	238660	0
T71	48891	0
T90	0	2
T91	0	4

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T10,T26,T27
1	1	Covered	T10,T26,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T10,T26,T27
1	0	Covered	T10,T26,T27
1	1	Covered	T10,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1033	0	0
SrcPulseCheck_M	6185301	1033	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1033
T10	363790	2
T11	312050	0
T12	157823	0
T13	753308	0
T26	0	2
T27	0	2
T46	728447	0
T57	18093	0
T58	241211	0
T62	0	4
T63	0	4
T64	0	2
T67	0	4
T68	0	2
T69	342521	0
T70	238660	0
T71	48891	0
T90	0	2
T91	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1033
T10	329770	2
T11	12736	0
T12	18567	0
T13	21523	0
T26	0	2
T27	0	2
T46	8570	0
T57	517	0
T58	502	0
T62	0	4
T63	0	4
T64	0	2
T67	0	4
T68	0	2
T69	713	0
T70	502	0
T71	407	0
T90	0	2
T91	0	4

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8
1	1	Covered	T9,T62,T63

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T8
1	0	Covered	T9,T62,T63
1	1	Covered	T1,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1082	0	0
SrcPulseCheck_M	1089315730	1144	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1082
T1	46391	11
T2	673	0
T3	991	0
T7	0	6
T8	0	1
T9	0	3
T10	0	1
T11	0	2
T12	0	2
T13	0	4
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T37	0	2
T60	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1144
T1	231959	11
T2	64358	0
T3	62001	0
T7	0	6
T8	0	1
T9	0	3
T10	0	1
T11	0	2
T12	0	2
T13	0	4
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	0
T19	103754	0
T20	123431	0
T37	0	2
T60	0	3

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T28,T29,T30
1	0	Covered	T28,T29,T30
1	1	Covered	T28,T29,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T28,T29,T30
1	0	Covered	T28,T29,T30
1	1	Covered	T28,T29,T30

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	2126	0	0
SrcPulseCheck_M	1089315730	2186	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	2126
T7	39016	0
T8	27461	0
T28	497	20
T29	0	20
T30	0	20
T32	704	0
T45	22192	0
T61	607	0
T72	0	20
T73	0	20
T74	0	20
T75	0	20
T76	0	20
T77	0	20
T78	0	20
T79	508	0
T80	504	0
T81	427	0
T82	422	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	2186
T7	468186	0
T8	315811	0
T28	22400	20
T29	0	20
T30	0	20
T32	77493	0
T45	266308	0
T61	212368	0
T72	0	20
T73	0	20
T74	0	20
T75	0	20
T76	0	20
T77	0	20
T78	0	20
T79	33090	0
T80	121056	0
T81	51279	0
T82	194318	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T28,T29,T30
1	0	Covered	T28,T29,T30
1	1	Covered	T28,T29,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T28,T29,T30
1	0	Covered	T28,T29,T30
1	1	Covered	T28,T29,T30

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	2177	0	0
SrcPulseCheck_M	6185301	2177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	2177
T7	468186	0
T8	315811	0
T28	22400	20
T29	0	20
T30	0	20
T32	77493	0
T45	266308	0
T61	212368	0
T72	0	20
T73	0	20
T74	0	20
T75	0	20
T76	0	20
T77	0	20
T78	0	20
T79	33090	0
T80	121056	0
T81	51279	0
T82	194318	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	2177
T7	39016	0
T8	27461	0
T28	497	20
T29	0	20
T30	0	20
T32	704	0
T45	22192	0
T61	607	0
T72	0	20
T73	0	20
T74	0	20
T75	0	20
T76	0	20
T77	0	20
T78	0	20
T79	508	0
T80	504	0
T81	427	0
T82	422	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T6,T21,T15
1	0	Covered	T6,T21,T15
1	1	Covered	T6,T21,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T6,T21,T15
1	0	Covered	T6,T21,T15
1	1	Covered	T6,T21,T15

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	3807	0	0
SrcPulseCheck_M	1089315730	3868	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	3807
T1	46391	0
T2	673	0
T3	991	0
T6	502	20
T14	424	0
T15	501	20
T16	1062	0
T17	667	0
T18	4367	0
T20	0	20
T21	526	20
T28	0	1
T33	0	20
T58	0	20
T79	0	20
T80	0	20
T83	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	3868
T1	231959	0
T2	64358	0
T3	62001	0
T6	246261	20
T14	101742	0
T15	240715	20
T16	265838	0
T17	76787	0
T18	106996	0
T20	0	20
T21	63224	20
T28	0	1
T33	0	20
T58	0	20
T79	0	20
T80	0	20
T83	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T6,T21,T15
1	0	Covered	T6,T21,T15
1	1	Covered	T6,T21,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T6,T21,T15
1	0	Covered	T6,T21,T15
1	1	Covered	T6,T21,T15

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	3855	0	0
SrcPulseCheck_M	6185301	3856	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	3855
T1	231959	0
T2	64358	0
T3	62001	0
T6	246261	20
T14	101742	0
T15	240715	20
T16	265838	0
T17	76787	0
T18	106996	0
T20	0	20
T21	63224	20
T28	0	1
T33	0	20
T58	0	20
T79	0	20
T80	0	20
T83	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	3856
T1	46391	0
T2	673	0
T3	991	0
T6	502	20
T14	424	0
T15	501	20
T16	1062	0
T17	667	0
T18	4367	0
T20	0	20
T21	526	20
T28	0	1
T33	0	20
T58	0	20
T79	0	20
T80	0	20
T83	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T21
1	0	Covered	T4,T6,T21
1	1	Covered	T6,T21,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T21
1	0	Covered	T6,T21,T15
1	1	Covered	T4,T6,T21

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	4827	0	0
SrcPulseCheck_M	1089315730	4885	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	4827
T1	46391	12
T2	673	0
T3	991	0
T4	559	1
T5	863	0
T6	502	20
T14	424	0
T15	501	20
T16	1062	1
T17	0	1
T18	0	1
T20	0	20
T21	526	20
T83	0	21

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	4885
T1	231959	12
T2	64358	0
T3	62001	0
T4	139788	1
T5	431686	0
T6	246261	20
T14	101742	0
T15	240715	20
T16	265838	1
T17	0	1
T18	0	1
T20	0	20
T21	63224	20
T83	0	21

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T21
1	0	Covered	T4,T6,T21
1	1	Covered	T6,T21,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T21
1	0	Covered	T6,T21,T15
1	1	Covered	T4,T6,T21

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	4875	0	0
SrcPulseCheck_M	6185301	4875	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	4875
T1	231959	12
T2	64358	0
T3	62001	0
T4	139788	1
T5	431686	0
T6	246261	20
T14	101742	0
T15	240715	20
T16	265838	1
T17	0	1
T18	0	1
T20	0	20
T21	63224	20
T83	0	21

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	4875
T1	46391	12
T2	673	0
T3	991	0
T4	559	1
T5	863	0
T6	502	20
T14	424	0
T15	501	20
T16	1062	1
T17	0	1
T18	0	1
T20	0	20
T21	526	20
T83	0	21

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T6,T21,T15
1	0	Covered	T6,T21,T15
1	1	Covered	T6,T21,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T6,T21,T15
1	0	Covered	T6,T21,T15
1	1	Covered	T6,T21,T15

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	3727	0	0
SrcPulseCheck_M	1089315730	3787	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	3727
T1	46391	0
T2	673	0
T3	991	0
T6	502	20
T14	424	0
T15	501	20
T16	1062	0
T17	667	0
T18	4367	0
T20	0	20
T21	526	20
T33	0	20
T58	0	20
T70	0	20
T79	0	20
T80	0	20
T83	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	3787
T1	231959	0
T2	64358	0
T3	62001	0
T6	246261	20
T14	101742	0
T15	240715	20
T16	265838	0
T17	76787	0
T18	106996	0
T20	0	20
T21	63224	20
T33	0	20
T58	0	20
T70	0	20
T79	0	20
T80	0	20
T83	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T6,T21,T15
1	0	Covered	T6,T21,T15
1	1	Covered	T6,T21,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T6,T21,T15
1	0	Covered	T6,T21,T15
1	1	Covered	T6,T21,T15

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	3777	0	0
SrcPulseCheck_M	6185301	3777	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	3777
T1	231959	0
T2	64358	0
T3	62001	0
T6	246261	20
T14	101742	0
T15	240715	20
T16	265838	0
T17	76787	0
T18	106996	0
T20	0	20
T21	63224	20
T33	0	20
T58	0	20
T70	0	20
T79	0	20
T80	0	20
T83	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	3777
T1	46391	0
T2	673	0
T3	991	0
T6	502	20
T14	424	0
T15	501	20
T16	1062	0
T17	667	0
T18	4367	0
T20	0	20
T21	526	20
T33	0	20
T58	0	20
T70	0	20
T79	0	20
T80	0	20
T83	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T3,T12
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T12
1	0	Covered	T59,T117,T35
1	1	Covered	T2,T3,T12

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	988	0	0
SrcPulseCheck_M	1089315730	1045	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	988
T2	673	1
T3	991	1
T12	0	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T38	0	1
T39	0	1
T40	0	1
T41	0	1
T44	0	1
T84	0	1
T85	437	0
T86	910	0
T87	405	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1045
T2	64358	1
T3	62001	1
T12	0	1
T16	265838	0
T17	76787	0
T18	106996	0
T19	103754	0
T20	123431	0
T29	0	1
T38	0	1
T39	0	1
T40	0	1
T41	0	1
T44	0	1
T84	0	1
T85	19689	0
T86	400504	0
T87	50728	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T3,T12
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T12
1	0	Covered	T59,T117,T35
1	1	Covered	T2,T3,T12

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1034	0	0
SrcPulseCheck_M	6185301	1034	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1034
T2	64358	1
T3	62001	1
T12	0	1
T16	265838	0
T17	76787	0
T18	106996	0
T19	103754	0
T20	123431	0
T29	0	1
T38	0	1
T39	0	1
T40	0	1
T41	0	1
T44	0	1
T84	0	1
T85	19689	0
T86	400504	0
T87	50728	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1034
T2	673	1
T3	991	1
T12	0	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T38	0	1
T39	0	1
T40	0	1
T41	0	1
T44	0	1
T84	0	1
T85	437	0
T86	910	0
T87	405	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1845	0	0
SrcPulseCheck_M	1089315730	1904	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1845
T1	46391	12
T2	673	1
T3	991	1
T7	0	17
T8	0	10
T9	0	5
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T33	0	1
T45	0	9
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1904
T1	231959	12
T2	64358	1
T3	62001	1
T7	0	17
T8	0	10
T9	0	5
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T33	0	1
T45	0	9
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1894	0	0
SrcPulseCheck_M	6185301	1895	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1894
T1	231959	12
T2	64358	1
T3	62001	1
T7	0	17
T8	0	10
T9	0	5
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T33	0	1
T45	0	9
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1895
T1	46391	12
T2	673	1
T3	991	1
T7	0	17
T8	0	10
T9	0	5
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T33	0	1
T45	0	9
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T32,T33,T29
1	0	Covered	T32,T33,T29
1	1	Covered	T32,T33,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T32,T33,T29
1	0	Covered	T32,T33,T29
1	1	Covered	T32,T33,T29

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1217	0	0
SrcPulseCheck_M	1089315730	1277	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1217
T9	18041	0
T10	329770	0
T27	0	5
T29	0	4
T30	0	11
T32	704	3
T33	4193	5
T47	38445	0
T49	0	4
T50	0	4
T51	0	3
T52	0	5
T53	0	6
T54	823	0
T55	408	0
T56	763	0
T57	517	0
T58	502	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1277
T9	884066	0
T10	363790	0
T27	0	5
T29	0	4
T30	0	11
T32	77493	3
T33	503272	5
T47	182622	0
T49	0	4
T50	0	4
T51	0	3
T52	0	5
T53	0	6
T54	374376	0
T55	140607	0
T56	366519	0
T57	18093	0
T58	241211	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T32,T33,T29
1	0	Covered	T32,T33,T29
1	1	Covered	T32,T33,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T32,T33,T29
1	0	Covered	T32,T33,T29
1	1	Covered	T32,T33,T29

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1267	0	0
SrcPulseCheck_M	6185301	1267	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1267
T9	884066	0
T10	363790	0
T27	0	5
T29	0	4
T30	0	11
T32	77493	3
T33	503272	5
T47	182622	0
T49	0	4
T50	0	4
T51	0	3
T52	0	5
T53	0	6
T54	374376	0
T55	140607	0
T56	366519	0
T57	18093	0
T58	241211	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1267
T9	18041	0
T10	329770	0
T27	0	5
T29	0	4
T30	0	11
T32	704	3
T33	4193	5
T47	38445	0
T49	0	4
T50	0	4
T51	0	3
T52	0	5
T53	0	6
T54	823	0
T55	408	0
T56	763	0
T57	517	0
T58	502	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T32,T33,T29
1	0	Covered	T32,T33,T29
1	1	Covered	T32,T33,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T32,T33,T29
1	0	Covered	T32,T33,T29
1	1	Covered	T32,T33,T29

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1027	0	0
SrcPulseCheck_M	1089315730	1082	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1027
T9	18041	0
T10	329770	0
T27	0	3
T29	0	3
T30	0	6
T32	704	3
T33	4193	3
T47	38445	0
T49	0	3
T50	0	3
T51	0	3
T52	0	3
T53	0	3
T54	823	0
T55	408	0
T56	763	0
T57	517	0
T58	502	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1082
T9	884066	0
T10	363790	0
T27	0	3
T29	0	3
T30	0	6
T32	77493	3
T33	503272	3
T47	182622	0
T49	0	3
T50	0	3
T51	0	3
T52	0	3
T53	0	3
T54	374376	0
T55	140607	0
T56	366519	0
T57	18093	0
T58	241211	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T32,T33,T29
1	0	Covered	T32,T33,T29
1	1	Covered	T32,T33,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T32,T33,T29
1	0	Covered	T32,T33,T29
1	1	Covered	T32,T33,T29

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1075	0	0
SrcPulseCheck_M	6185301	1075	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1075
T9	884066	0
T10	363790	0
T27	0	3
T29	0	3
T30	0	6
T32	77493	3
T33	503272	3
T47	182622	0
T49	0	3
T50	0	3
T51	0	3
T52	0	3
T53	0	3
T54	374376	0
T55	140607	0
T56	366519	0
T57	18093	0
T58	241211	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1075
T9	18041	0
T10	329770	0
T27	0	3
T29	0	3
T30	0	6
T32	704	3
T33	4193	3
T47	38445	0
T49	0	3
T50	0	3
T51	0	3
T52	0	3
T53	0	3
T54	823	0
T55	408	0
T56	763	0
T57	517	0
T58	502	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	7164	0	0
SrcPulseCheck_M	1089315730	7227	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	7164
T1	46391	78
T2	673	0
T3	991	0
T8	0	83
T9	0	61
T11	0	77
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T46	0	83
T48	0	88
T60	0	74
T88	0	69
T89	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	7227
T1	231959	78
T2	64358	0
T3	62001	0
T8	0	83
T9	0	61
T11	0	77
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T46	0	83
T48	0	88
T60	0	74
T88	0	69
T89	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	7217	0	0
SrcPulseCheck_M	6185301	7217	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	7217
T1	231959	78
T2	64358	0
T3	62001	0
T8	0	83
T9	0	61
T11	0	77
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T46	0	83
T48	0	88
T60	0	74
T88	0	69
T89	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	7217
T1	46391	78
T2	673	0
T3	991	0
T8	0	83
T9	0	61
T11	0	77
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T46	0	83
T48	0	88
T60	0	74
T88	0	69
T89	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	7080	0	0
SrcPulseCheck_M	1089315730	7143	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	7080
T1	46391	78
T2	673	0
T3	991	0
T8	0	69
T9	0	72
T11	0	77
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T46	0	66
T48	0	76
T60	0	62
T88	0	63
T89	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	7143
T1	231959	78
T2	64358	0
T3	62001	0
T8	0	69
T9	0	72
T11	0	77
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T46	0	66
T48	0	76
T60	0	62
T88	0	63
T89	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	7131	0	0
SrcPulseCheck_M	6185301	7131	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	7131
T1	231959	78
T2	64358	0
T3	62001	0
T8	0	69
T9	0	72
T11	0	77
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T46	0	66
T48	0	76
T60	0	62
T88	0	63
T89	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	7131
T1	46391	78
T2	673	0
T3	991	0
T8	0	69
T9	0	72
T11	0	77
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T46	0	66
T48	0	76
T60	0	62
T88	0	63
T89	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	7029	0	0
SrcPulseCheck_M	1089315730	7094	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	7029
T1	46391	76
T2	673	0
T3	991	0
T8	0	92
T9	0	77
T11	0	53
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T46	0	63
T48	0	75
T60	0	69
T88	0	66
T89	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	7094
T1	231959	76
T2	64358	0
T3	62001	0
T8	0	92
T9	0	77
T11	0	53
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T46	0	63
T48	0	75
T60	0	69
T88	0	66
T89	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	7084	0	0
SrcPulseCheck_M	6185301	7085	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	7084
T1	231959	76
T2	64358	0
T3	62001	0
T8	0	92
T9	0	77
T11	0	53
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T46	0	63
T48	0	75
T60	0	69
T88	0	66
T89	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	7085
T1	46391	76
T2	673	0
T3	991	0
T8	0	92
T9	0	77
T11	0	53
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T46	0	63
T48	0	75
T60	0	69
T88	0	66
T89	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	7096	0	0
SrcPulseCheck_M	1089315730	7158	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	7096
T1	46391	94
T2	673	0
T3	991	0
T8	0	82
T9	0	71
T11	0	77
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T46	0	85
T48	0	76
T60	0	82
T88	0	66
T89	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	7158
T1	231959	94
T2	64358	0
T3	62001	0
T8	0	82
T9	0	71
T11	0	77
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T46	0	85
T48	0	76
T60	0	82
T88	0	66
T89	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	7150	0	0
SrcPulseCheck_M	6185301	7150	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	7150
T1	231959	94
T2	64358	0
T3	62001	0
T8	0	82
T9	0	71
T11	0	77
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T46	0	85
T48	0	76
T60	0	82
T88	0	66
T89	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	7150
T1	46391	94
T2	673	0
T3	991	0
T8	0	82
T9	0	71
T11	0	77
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T46	0	85
T48	0	76
T60	0	82
T88	0	66
T89	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1268	0	0
SrcPulseCheck_M	1089315730	1326	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1268
T1	46391	12
T2	673	0
T3	991	0
T8	0	10
T9	0	5
T11	0	3
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1326
T1	231959	12
T2	64358	0
T3	62001	0
T8	0	10
T9	0	5
T11	0	3
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1315	0	0
SrcPulseCheck_M	6185301	1315	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1315
T1	231959	12
T2	64358	0
T3	62001	0
T8	0	10
T9	0	5
T11	0	3
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1315
T1	46391	12
T2	673	0
T3	991	0
T8	0	10
T9	0	5
T11	0	3
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1234	0	0
SrcPulseCheck_M	1089315730	1298	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1234
T1	46391	12
T2	673	0
T3	991	0
T8	0	10
T9	0	5
T11	0	3
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1298
T1	231959	12
T2	64358	0
T3	62001	0
T8	0	10
T9	0	5
T11	0	3
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1288	0	0
SrcPulseCheck_M	6185301	1288	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1288
T1	231959	12
T2	64358	0
T3	62001	0
T8	0	10
T9	0	5
T11	0	3
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1288
T1	46391	12
T2	673	0
T3	991	0
T8	0	10
T9	0	5
T11	0	3
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1210	0	0
SrcPulseCheck_M	1089315730	1268	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1210
T1	46391	12
T2	673	0
T3	991	0
T8	0	10
T9	0	5
T11	0	3
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1268
T1	231959	12
T2	64358	0
T3	62001	0
T8	0	10
T9	0	5
T11	0	3
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1258	0	0
SrcPulseCheck_M	6185301	1258	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1258
T1	231959	12
T2	64358	0
T3	62001	0
T8	0	10
T9	0	5
T11	0	3
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1258
T1	46391	12
T2	673	0
T3	991	0
T8	0	10
T9	0	5
T11	0	3
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1230	0	0
SrcPulseCheck_M	1089315730	1289	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1230
T1	46391	12
T2	673	0
T3	991	0
T8	0	10
T9	0	5
T11	0	3
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1289
T1	231959	12
T2	64358	0
T3	62001	0
T8	0	10
T9	0	5
T11	0	3
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T18,T8
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T8
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1280	0	0
SrcPulseCheck_M	6185301	1280	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1280
T1	231959	12
T2	64358	0
T3	62001	0
T8	0	10
T9	0	5
T11	0	3
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1280
T1	46391	12
T2	673	0
T3	991	0
T8	0	10
T9	0	5
T11	0	3
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T46	0	1
T48	0	2
T60	0	4
T88	0	1
T89	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	7705	0	0
SrcPulseCheck_M	1089315730	7764	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	7705
T1	46391	78
T2	673	0
T3	991	0
T7	0	17
T8	0	83
T9	0	61
T11	0	77
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T33	0	1
T45	0	9
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	7764
T1	231959	78
T2	64358	0
T3	62001	0
T7	0	17
T8	0	83
T9	0	61
T11	0	77
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T33	0	1
T45	0	9
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	7754	0	0
SrcPulseCheck_M	6185301	7754	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	7754
T1	231959	78
T2	64358	0
T3	62001	0
T7	0	17
T8	0	83
T9	0	61
T11	0	77
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T33	0	1
T45	0	9
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	7754
T1	46391	78
T2	673	0
T3	991	0
T7	0	17
T8	0	83
T9	0	61
T11	0	77
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T33	0	1
T45	0	9
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	7566	0	0
SrcPulseCheck_M	1089315730	7633	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	7566
T1	46391	78
T2	673	0
T3	991	0
T7	0	17
T8	0	69
T9	0	72
T11	0	77
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T45	0	9
T46	0	66
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	7633
T1	231959	78
T2	64358	0
T3	62001	0
T7	0	17
T8	0	69
T9	0	72
T11	0	77
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T45	0	9
T46	0	66
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	7622	0	0
SrcPulseCheck_M	6185301	7622	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	7622
T1	231959	78
T2	64358	0
T3	62001	0
T7	0	17
T8	0	69
T9	0	72
T11	0	77
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T45	0	9
T46	0	66
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	7622
T1	46391	78
T2	673	0
T3	991	0
T7	0	17
T8	0	69
T9	0	72
T11	0	77
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T45	0	9
T46	0	66
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	7576	0	0
SrcPulseCheck_M	1089315730	7640	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	7576
T1	46391	76
T2	673	0
T3	991	0
T7	0	17
T8	0	92
T9	0	77
T11	0	53
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T45	0	9
T46	0	63
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	7640
T1	231959	76
T2	64358	0
T3	62001	0
T7	0	17
T8	0	92
T9	0	77
T11	0	53
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T45	0	9
T46	0	63
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	7628	0	0
SrcPulseCheck_M	6185301	7628	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	7628
T1	231959	76
T2	64358	0
T3	62001	0
T7	0	17
T8	0	92
T9	0	77
T11	0	53
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T45	0	9
T46	0	63
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	7628
T1	46391	76
T2	673	0
T3	991	0
T7	0	17
T8	0	92
T9	0	77
T11	0	53
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T45	0	9
T46	0	63
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	7584	0	0
SrcPulseCheck_M	1089315730	7644	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	7584
T1	46391	94
T2	673	0
T3	991	0
T7	0	17
T8	0	82
T9	0	71
T11	0	77
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T45	0	9
T46	0	85
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	7644
T1	231959	94
T2	64358	0
T3	62001	0
T7	0	17
T8	0	82
T9	0	71
T11	0	77
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T45	0	9
T46	0	85
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T1,T18,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T8
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	7636	0	0
SrcPulseCheck_M	6185301	7636	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	7636
T1	231959	94
T2	64358	0
T3	62001	0
T7	0	17
T8	0	82
T9	0	71
T11	0	77
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	51
T19	103754	0
T20	123431	0
T45	0	9
T46	0	85
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	7636
T1	46391	94
T2	673	0
T3	991	0
T7	0	17
T8	0	82
T9	0	71
T11	0	77
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	51
T19	423	0
T20	503	0
T45	0	9
T46	0	85
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1772	0	0
SrcPulseCheck_M	1089315730	1833	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1772
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T33	0	1
T45	0	9
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1833
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T33	0	1
T45	0	9
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1822	0	0
SrcPulseCheck_M	6185301	1822	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1822
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T33	0	1
T45	0	9
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1822
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T33	0	1
T45	0	9
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1766	0	0
SrcPulseCheck_M	1089315730	1824	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1766
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T45	0	9
T46	0	1
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1824
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T45	0	9
T46	0	1
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1813	0	0
SrcPulseCheck_M	6185301	1814	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1813
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T45	0	9
T46	0	1
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1814
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T45	0	9
T46	0	1
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1761	0	0
SrcPulseCheck_M	1089315730	1818	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1761
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T45	0	9
T46	0	1
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1818
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T45	0	9
T46	0	1
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1809	0	0
SrcPulseCheck_M	6185301	1809	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1809
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T45	0	9
T46	0	1
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1809
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T45	0	9
T46	0	1
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1734	0	0
SrcPulseCheck_M	1089315730	1792	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1734
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T45	0	9
T46	0	1
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1792
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T45	0	9
T46	0	1
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1781	0	0
SrcPulseCheck_M	6185301	1781	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1781
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T45	0	9
T46	0	1
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1781
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T45	0	9
T46	0	1
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1798	0	0
SrcPulseCheck_M	1089315730	1858	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1798
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T33	0	1
T45	0	9
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1858
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T33	0	1
T45	0	9
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1849	0	0
SrcPulseCheck_M	6185301	1849	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1849
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T33	0	1
T45	0	9
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1849
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T33	0	1
T45	0	9
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1773	0	0
SrcPulseCheck_M	1089315730	1834	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1773
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T45	0	9
T46	0	1
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1834
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T45	0	9
T46	0	1
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1823	0	0
SrcPulseCheck_M	6185301	1823	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1823
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T45	0	9
T46	0	1
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1823
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T45	0	9
T46	0	1
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1752	0	0
SrcPulseCheck_M	1089315730	1808	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1752
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T45	0	9
T46	0	1
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1808
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T45	0	9
T46	0	1
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1799	0	0
SrcPulseCheck_M	6185301	1799	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1799
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T45	0	9
T46	0	1
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1799
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T45	0	9
T46	0	1
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6185301	1710	0	0
SrcPulseCheck_M	1089315730	1764	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6185301	1710
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T45	0	9
T46	0	1
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1089315730	1764
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T45	0	9
T46	0	1
T47	0	17

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T1,T18,T7
1	1	Covered	T59,T117,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T18,T7
1	0	Covered	T59,T117,T35
1	1	Covered	T1,T18,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1089315730	1755	0	0
SrcPulseCheck_M	6185301	1755	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1089315730	1755
T1	231959	12
T2	64358	0
T3	62001	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	101742	0
T15	240715	0
T16	265838	0
T17	76787	0
T18	106996	1
T19	103754	0
T20	123431	0
T45	0	9
T46	0	1
T47	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6185301	1755
T1	46391	12
T2	673	0
T3	991	0
T7	0	17
T8	0	10
T9	0	5
T11	0	3
T12	0	6
T14	424	0
T15	501	0
T16	1062	0
T17	667	0
T18	4367	1
T19	423	0
T20	503	0
T45	0	9
T46	0	1
T47	0	17

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc