Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1909

1

T7

7

T8

9

T27

15

auto[1]

673

1

T7

10

T8

9

T27

5

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1951

1

T7

15

T27

20

T9

27

auto[1]

631

1

T7

2

T8

18

T9

5

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1905

1

T7

13

T8

15

T27

20

auto[1]

677

1

T7

4

T8

3

T9

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1938

1

T7

4

T8

9

T27

19

auto[1]

644

1

T7

13

T8

9

T27

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2389

1

T7

17

T8

18

T27

19

auto[1]

193

1

T27

1

T36

8

T35

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2333

1

T7

17

T8

18

T27

20

auto[1]

249

1

T9

3

T12

3

T36

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2339

1

T7

17

T8

18

T27

15

auto[1]

243

1

T27

5

T9

5

T36

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2325

1

T7

17

T8

18

T27

20

auto[1]

257

1

T9

3

T36

5

T38

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2302

1

T7

17

T8

18

T27

20

auto[1]

280

1

T9

8

T12

11

T36

7

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2001

1

T7

6

T8

18

T27

19

auto[1]

581

1

T7

11

T27

1

T53

6

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

787

1

T7

7

T8

18

T53

15

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

66

1

T79

1

T92

2

T122

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

85

1

T12

8

T35

9

T344

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T35

1

T323

7

T345

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

87

1

T346

5

T347

2

T348

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T36

2

T38

1

T220

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

23

1

T36

3

T80

1

T346

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T349

6

-

-

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

76

1

T38

2

T122

4

T347

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

5

1

T35

2

T164

1

T350

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

34

1

T9

5

T351

2

T323

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T352

4

T334

1

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

20

1

T38

1

T346

2

T353

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T133

4

T352

2

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21

1

T332

4

T333

15

T354

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

109

1

T164

1

T92

3

T344

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T352

9

T345

4

T355

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

25

1

T12

3

T93

4

T356

13

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T36

4

T220

1

T90

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

19

1

T249

10

T328

3

T357

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T324

2

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T9

3

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

17

1

T164

1

T133

9

T234

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T36

2

T237

1

T345

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

16

1

T133

3

T356

13

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

12

1

T249

6

T358

3

T328

3

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

119

1

T53

9

T35

9

T164

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

78

1

T38

2

T133

9

T237

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

64

1

T53

6

T37

4

T121

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

64

1

T12

3

T133

3

T323

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

80

1

T74

4

T351

2

T359

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

67

1

T7

5

T36

2

T234

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T323

7

T226

4

T326

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

113

1

T80

1

T120

10

T122

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

58

1

T9

3

T249

10

T250

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

65

1

T39

5

T164

1

T74

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T120

3

T121

6

T344

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

78

1

T36

4

T92

3

T74

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

38

1

T120

3

T121

3

T351

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

47

1

T319

3

T237

5

T360

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T319

6

T360

1

T326

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

146

1

T35

2

T122

4

T133

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

71

1

T8

6

T360

5

T359

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T36

2

T37

4

T220

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T38

2

T121

3

T74

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

66

1

T8

6

T9

5

T37

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T8

3

T12

4

T225

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

21

1

T7

2

T39

2

T164

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T105

3

T348

4

T345

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

65

1

T8

3

T36

3

T239

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T12

4

T329

3

T226

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

13

1

T79

1

T107

4

T325

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T224

4

T347

2

T251

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

23

1

T35

1

T323

7

T361

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T225

2

T331

2

T362

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T321

3

T229

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T363

2

T362

1

T230

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded