Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

701

1

T5

12

T62

10

T76

9

auto[1]

679

1

T5

8

T62

10

T76

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

333

1

T5

4

T62

6

T76

5

from_0to1

337

1

T5

5

T62

6

T76

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

695

1

T5

7

T62

8

T76

8

auto[1]

685

1

T5

13

T62

12

T76

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

678

1

T5

11

T62

11

T76

8

auto[1]

702

1

T5

9

T62

9

T76

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

49

1

T5

1

T62

1

T76

1

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T62

1

T76

1

T318

1

auto[0]

from_1to0

auto[1]

auto[0]

31

1

T62

4

T24

1

T78

2

auto[0]

from_1to0

auto[1]

auto[1]

46

1

T5

1

T76

1

T78

3

auto[0]

from_0to1

auto[0]

auto[0]

45

1

T24

1

T78

2

T318

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T5

1

T62

2

T76

1

auto[0]

from_0to1

auto[1]

auto[0]

44

1

T5

3

T76

1

T78

1

auto[0]

from_0to1

auto[1]

auto[1]

44

1

T76

1

T78

2

T318

2

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T5

1

T78

1

T161

1

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T78

1

T318

1

T376

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T78

1

T318

1

T161

1

auto[1]

from_1to0

auto[1]

auto[1]

43

1

T5

1

T76

2

T24

2

auto[1]

from_0to1

auto[0]

auto[0]

44

1

T78

1

T248

1

T377

1

auto[1]

from_0to1

auto[0]

auto[1]

33

1

T62

1

T195

1

T250

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T5

1

T62

2

T78

1

auto[1]

from_0to1

auto[1]

auto[1]

44

1

T62

1

T76

2

T24

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

686

1

T5

10

T62

7

T76

11

auto[1]

694

1

T5

10

T62

13

T76

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

335

1

T5

3

T62

7

T76

5

from_0to1

326

1

T5

3

T62

6

T76

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687

1

T5

13

T62

7

T76

11

auto[1]

693

1

T5

7

T62

13

T76

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659

1

T5

12

T62

9

T76

11

auto[1]

721

1

T5

8

T62

11

T76

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

43

1

T5

1

T76

1

T318

2

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T5

1

T76

1

T318

1

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T78

2

T318

1

T161

1

auto[0]

from_1to0

auto[1]

auto[1]

45

1

T62

1

T78

2

T318

2

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T76

1

T318

1

T376

1

auto[0]

from_0to1

auto[0]

auto[1]

41

1

T5

1

T62

1

T248

1

auto[0]

from_0to1

auto[1]

auto[0]

38

1

T62

1

T76

1

T78

1

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T62

1

T76

2

T78

1

auto[1]

from_1to0

auto[0]

auto[0]

32

1

T62

1

T78

2

T248

1

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T62

2

T76

1

T24

2

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T5

1

T62

1

T76

1

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T62

2

T76

1

T24

1

auto[1]

from_0to1

auto[0]

auto[0]

47

1

T5

2

T76

1

T24

4

auto[1]

from_0to1

auto[0]

auto[1]

30

1

T62

1

T78

2

T376

1

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T24

1

T318

1

T376

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T62

2

T78

2

T318

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

701

1

T5

9

T62

10

T76

13

auto[1]

679

1

T5

11

T62

10

T76

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

324

1

T5

3

T62

5

T76

6

from_0to1

322

1

T5

3

T62

4

T76

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

682

1

T5

8

T62

11

T76

9

auto[1]

698

1

T5

12

T62

9

T76

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

702

1

T5

10

T62

8

T76

12

auto[1]

678

1

T5

10

T62

12

T76

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

45

1

T5

1

T76

3

T78

1

auto[0]

from_1to0

auto[0]

auto[1]

45

1

T62

2

T24

1

T161

1

auto[0]

from_1to0

auto[1]

auto[0]

35

1

T5

1

T62

1

T76

1

auto[0]

from_1to0

auto[1]

auto[1]

42

1

T62

1

T76

1

T318

2

auto[0]

from_0to1

auto[0]

auto[0]

37

1

T62

1

T78

1

T318

2

auto[0]

from_0to1

auto[0]

auto[1]

34

1

T78

1

T195

1

T73

1

auto[0]

from_0to1

auto[1]

auto[0]

45

1

T5

1

T76

2

T78

1

auto[0]

from_0to1

auto[1]

auto[1]

40

1

T5

1

T62

1

T76

1

auto[1]

from_1to0

auto[0]

auto[0]

34

1

T76

1

T24

1

T78

1

auto[1]

from_1to0

auto[0]

auto[1]

40

1

T5

1

T62

1

T78

1

auto[1]

from_1to0

auto[1]

auto[0]

47

1

T24

1

T78

3

T248

2

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T78

2

T161

1

T378

1

auto[1]

from_0to1

auto[0]

auto[0]

35

1

T24

1

T318

1

T248

1

auto[1]

from_0to1

auto[0]

auto[1]

37

1

T62

1

T76

1

T24

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T5

1

T76

1

T78

3

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T62

1

T76

1

T24

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

709

1

T5

13

T62

7

T76

12

auto[1]

671

1

T5

7

T62

13

T76

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

334

1

T5

5

T62

7

T76

4

from_0to1

337

1

T5

5

T62

6

T76

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687

1

T5

4

T62

11

T76

16

auto[1]

693

1

T5

16

T62

9

T76

4

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687

1

T5

11

T62

11

T76

12

auto[1]

693

1

T5

9

T62

9

T76

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T62

1

T73

2

T378

1

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T76

2

T318

2

T248

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T5

1

T62

1

T78

2

auto[0]

from_1to0

auto[1]

auto[1]

36

1

T5

1

T78

2

T248

1

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T62

1

T76

1

T318

1

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T5

1

T62

1

T76

1

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T5

1

T78

2

T318

1

auto[0]

from_0to1

auto[1]

auto[1]

35

1

T5

1

T24

1

T78

1

auto[1]

from_1to0

auto[0]

auto[0]

34

1

T5

1

T76

2

T24

1

auto[1]

from_1to0

auto[0]

auto[1]

40

1

T62

2

T24

3

T78

4

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T5

1

T62

2

T78

1

auto[1]

from_1to0

auto[1]

auto[1]

44

1

T5

1

T62

1

T24

1

auto[1]

from_0to1

auto[0]

auto[0]

32

1

T5

1

T62

1

T24

1

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T62

1

T76

2

T24

1

auto[1]

from_0to1

auto[1]

auto[0]

39

1

T62

1

T248

1

T376

1

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T5

1

T62

1

T24

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

679

1

T5

10

T62

8

T76

10

auto[1]

701

1

T5

10

T62

12

T76

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

319

1

T5

6

T62

6

T76

5

from_0to1

324

1

T5

6

T62

5

T76

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

666

1

T5

6

T62

14

T76

7

auto[1]

714

1

T5

14

T62

6

T76

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

697

1

T5

15

T62

7

T76

11

auto[1]

683

1

T5

5

T62

13

T76

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

35

1

T5

1

T62

1

T78

1

auto[0]

from_1to0

auto[0]

auto[1]

44

1

T62

1

T24

2

T318

1

auto[0]

from_1to0

auto[1]

auto[0]

38

1

T5

1

T76

1

T24

1

auto[0]

from_1to0

auto[1]

auto[1]

39

1

T5

2

T62

1

T76

1

auto[0]

from_0to1

auto[0]

auto[0]

36

1

T5

2

T62

1

T24

2

auto[0]

from_0to1

auto[0]

auto[1]

27

1

T318

2

T376

2

T377

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T5

1

T24

1

T78

2

auto[0]

from_0to1

auto[1]

auto[1]

39

1

T62

1

T76

2

T161

2

auto[1]

from_1to0

auto[0]

auto[0]

41

1

T76

1

T78

2

T376

1

auto[1]

from_1to0

auto[0]

auto[1]

38

1

T62

3

T161

2

T73

1

auto[1]

from_1to0

auto[1]

auto[0]

46

1

T5

2

T76

1

T24

1

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T76

1

T78

3

T318

1

auto[1]

from_0to1

auto[0]

auto[0]

46

1

T62

1

T24

1

T318

2

auto[1]

from_0to1

auto[0]

auto[1]

39

1

T62

1

T24

1

T195

1

auto[1]

from_0to1

auto[1]

auto[0]

42

1

T5

3

T76

2

T78

1

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T62

1

T76

1

T78

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

712

1

T5

10

T62

6

T76

10

auto[1]

668

1

T5

10

T62

14

T76

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

334

1

T5

6

T62

5

T76

4

from_0to1

322

1

T5

5

T62

5

T76

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

692

1

T5

10

T62

14

T76

11

auto[1]

688

1

T5

10

T62

6

T76

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

729

1

T5

12

T62

9

T76

13

auto[1]

651

1

T5

8

T62

11

T76

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

49

1

T76

1

T24

1

T78

4

auto[0]

from_1to0

auto[0]

auto[1]

39

1

T5

1

T62

1

T318

1

auto[0]

from_1to0

auto[1]

auto[0]

45

1

T5

1

T78

1

T377

1

auto[0]

from_1to0

auto[1]

auto[1]

37

1

T24

1

T78

1

T248

1

auto[0]

from_0to1

auto[0]

auto[0]

46

1

T76

2

T248

1

T377

2

auto[0]

from_0to1

auto[0]

auto[1]

31

1

T5

2

T24

2

T248

1

auto[0]

from_0to1

auto[1]

auto[0]

38

1

T62

1

T318

1

T248

2

auto[0]

from_0to1

auto[1]

auto[1]

40

1

T78

2

T318

1

T67

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T5

1

T62

4

T76

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T5

1

T76

1

T24

1

auto[1]

from_1to0

auto[1]

auto[0]

38

1

T5

2

T24

1

T78

1

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T76

1

T78

2

T73

1

auto[1]

from_0to1

auto[0]

auto[0]

40

1

T5

2

T62

2

T376

2

auto[1]

from_0to1

auto[0]

auto[1]

43

1

T62

1

T24

1

T78

4

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T5

1

T76

1

T78

3

auto[1]

from_0to1

auto[1]

auto[1]

38

1

T62

1

T24

2

T78

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

719

1

T5

9

T62

11

T76

13

auto[1]

661

1

T5

11

T62

9

T76

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

342

1

T5

5

T62

3

T76

6

from_0to1

352

1

T5

5

T62

4

T76

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

684

1

T5

7

T62

9

T76

13

auto[1]

696

1

T5

13

T62

11

T76

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

707

1

T5

10

T62

10

T76

13

auto[1]

673

1

T5

10

T62

10

T76

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T5

1

T62

1

T76

1

auto[0]

from_1to0

auto[0]

auto[1]

34

1

T78

1

T161

1

T195

1

auto[0]

from_1to0

auto[1]

auto[0]

45

1

T62

1

T76

2

T78

1

auto[0]

from_1to0

auto[1]

auto[1]

45

1

T5

1

T24

1

T78

1

auto[0]

from_0to1

auto[0]

auto[0]

47

1

T76

2

T24

1

T318

1

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T5

1

T76

2

T24

1

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T62

1

T76

1

T78

2

auto[0]

from_0to1

auto[1]

auto[1]

46

1

T62

1

T76

1

T78

2

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T76

1

T24

1

T78

2

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T5

1

T62

1

T76

2

auto[1]

from_1to0

auto[1]

auto[0]

35

1

T5

1

T78

2

T376

2

auto[1]

from_1to0

auto[1]

auto[1]

42

1

T5

1

T24

1

T78

2

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T62

1

T76

1

T318

1

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T5

1

T24

1

T78

1

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T5

3

T62

1

T24

1

auto[1]

from_0to1

auto[1]

auto[1]

28

1

T24

1

T78

1

T376

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

650

1

T5

7

T62

14

T76

9

auto[1]

730

1

T5

13

T62

6

T76

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

345

1

T5

5

T62

8

T76

3

from_0to1

346

1

T5

5

T62

7

T76

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

691

1

T5

8

T62

9

T76

9

auto[1]

689

1

T5

12

T62

11

T76

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

663

1

T5

11

T62

10

T76

10

auto[1]

717

1

T5

9

T62

10

T76

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T62

2

T78

1

T376

2

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T5

1

T24

1

T318

2

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T62

1

T248

1

T161

1

auto[0]

from_1to0

auto[1]

auto[1]

47

1

T62

2

T24

2

T78

2

auto[0]

from_0to1

auto[0]

auto[0]

44

1

T62

2

T24

1

T78

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T62

2

T76

1

T78

2

auto[0]

from_0to1

auto[1]

auto[0]

34

1

T62

1

T78

1

T318

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T62

1

T78

3

T318

1

auto[1]

from_1to0

auto[0]

auto[0]

41

1

T5

2

T76

1

T24

1

auto[1]

from_1to0

auto[0]

auto[1]

38

1

T62

1

T24

1

T78

1

auto[1]

from_1to0

auto[1]

auto[0]

48

1

T5

1

T62

1

T24

1

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T5

1

T62

1

T76

2

auto[1]

from_0to1

auto[0]

auto[0]

33

1

T5

1

T76

1

T78

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T5

1

T76

1

T24

2

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T5

2

T24

1

T78

1

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T5

1

T62

1

T24

2