Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	138456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

105594

1

T4

1

T1

9

T5

144

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	126964	1			T4	3		T1	13		T5	233
values[0x0]	57935	1			T4	1		T1	7		T5	48
values[0x1]	59151	1			T4	1		T1	2		T5	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	111812	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

132238

1

T4

1

T1

11

T5

183

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	791	1			T1	1		T7	5		T57	8
valid_sources[0x01]	796	1			T13	1		T14	2		T7	1
valid_sources[0x02]	1841	1			T5	1		T17	1		T7	5
valid_sources[0x03]	958	1			T7	2		T76	2		T8	2
valid_sources[0x04]	1718	1			T5	1		T14	1		T7	3
valid_sources[0x05]	784	1			T5	1		T7	1		T10	1
valid_sources[0x06]	798	1			T5	1		T7	3		T57	6
valid_sources[0x07]	778	1			T5	3		T17	1		T8	7
valid_sources[0x08]	1978	1			T5	1		T7	1		T57	15
valid_sources[0x09]	1004	1			T8	5		T24	87		T10	1
valid_sources[0x0a]	746	1			T5	1		T14	4		T7	6
valid_sources[0x0b]	972	1			T5	1		T16	9		T7	2
valid_sources[0x0c]	781	1			T5	3		T14	1		T7	1
valid_sources[0x0d]	795	1			T1	2		T14	2		T8	6
valid_sources[0x0e]	1032	1			T7	3		T57	1		T62	4
valid_sources[0x0f]	967	1			T7	1		T76	2		T8	2
valid_sources[0x10]	1453	1			T7	3		T57	1		T62	3
valid_sources[0x11]	1235	1			T5	4		T7	5		T59	2
valid_sources[0x12]	1799	1			T5	3		T17	1		T57	2
valid_sources[0x13]	850	1			T2	2		T7	3		T57	8
valid_sources[0x14]	814	1			T5	1		T7	1		T25	1
valid_sources[0x15]	1102	1			T7	2		T57	2		T63	1
valid_sources[0x16]	788	1			T5	3		T7	2		T57	1
valid_sources[0x17]	1797	1			T5	2		T2	5		T7	2
valid_sources[0x18]	815	1			T7	5		T57	2		T8	3
valid_sources[0x19]	798	1			T7	2		T8	1		T12	2
valid_sources[0x1a]	1069	1			T5	3		T13	2		T7	1
valid_sources[0x1b]	920	1			T5	3		T7	3		T76	2
valid_sources[0x1c]	900	1			T7	2		T63	2		T12	3
valid_sources[0x1d]	842	1			T5	3		T7	3		T57	11
valid_sources[0x1e]	764	1			T5	2		T15	23		T7	1
valid_sources[0x1f]	886	1			T5	1		T14	1		T7	4
valid_sources[0x20]	858	1			T5	1		T13	2		T7	3
valid_sources[0x21]	912	1			T5	2		T14	2		T7	5
valid_sources[0x22]	809	1			T7	2		T8	1		T11	1
valid_sources[0x23]	995	1			T5	1		T59	1		T81	20
valid_sources[0x24]	1264	1			T5	2		T14	2		T7	3
valid_sources[0x25]	1021	1			T5	3		T14	1		T7	1
valid_sources[0x26]	985	1			T5	2		T14	1		T7	4
valid_sources[0x27]	894	1			T7	4		T59	1		T8	6
valid_sources[0x28]	810	1			T5	1		T62	4		T76	1
valid_sources[0x29]	878	1			T5	1		T7	3		T59	1
valid_sources[0x2a]	797	1			T13	1		T7	3		T25	4
valid_sources[0x2b]	864	1			T5	1		T7	3		T25	4
valid_sources[0x2c]	760	1			T5	1		T7	1		T57	1
valid_sources[0x2d]	1036	1			T57	5		T8	1		T285	1
valid_sources[0x2e]	686	1			T1	2		T5	3		T285	3
valid_sources[0x2f]	1031	1			T1	4		T5	3		T13	1
valid_sources[0x30]	1006	1			T1	3		T7	1		T62	1
valid_sources[0x31]	910	1			T5	1		T7	1		T8	4
valid_sources[0x32]	784	1			T5	1		T7	5		T8	2
valid_sources[0x33]	986	1			T5	2		T7	2		T10	1
valid_sources[0x34]	715	1			T5	2		T13	1		T7	1
valid_sources[0x35]	804	1			T5	1		T17	1		T57	1
valid_sources[0x36]	831	1			T1	1		T5	3		T17	1
valid_sources[0x37]	943	1			T7	4		T57	2		T25	4
valid_sources[0x38]	699	1			T5	1		T14	1		T7	1
valid_sources[0x39]	795	1			T5	1		T7	1		T57	3
valid_sources[0x3a]	1203	1			T57	4		T59	1		T8	1
valid_sources[0x3b]	786	1			T5	1		T7	1		T62	1
valid_sources[0x3c]	805	1			T7	1		T62	1		T8	7
valid_sources[0x3d]	785	1			T5	3		T7	1		T25	4
valid_sources[0x3e]	1068	1			T5	2		T17	1		T76	4
valid_sources[0x3f]	1256	1			T4	4		T5	1		T25	2
valid_sources[0x40]	852	1			T5	3		T14	3		T7	2
valid_sources[0x41]	990	1			T62	2		T76	1		T8	5
valid_sources[0x42]	1070	1			T5	2		T13	1		T7	1
valid_sources[0x43]	738	1			T5	1		T17	1		T7	5
valid_sources[0x44]	924	1			T5	2		T7	2		T76	1
valid_sources[0x45]	648	1			T5	1		T14	1		T6	1
valid_sources[0x46]	924	1			T5	2		T7	2		T57	1
valid_sources[0x47]	1042	1			T5	1		T7	2		T57	16
valid_sources[0x48]	806	1			T7	2		T8	2		T24	1
valid_sources[0x49]	796	1			T5	1		T62	3		T63	3
valid_sources[0x4a]	986	1			T5	1		T7	2		T57	2
valid_sources[0x4b]	959	1			T5	2		T7	3		T57	1
valid_sources[0x4c]	813	1			T1	1		T5	3		T7	1
valid_sources[0x4d]	892	1			T7	2		T59	1		T10	1
valid_sources[0x4e]	691	1			T7	2		T57	2		T10	1
valid_sources[0x4f]	782	1			T17	1		T7	2		T59	1
valid_sources[0x50]	698	1			T5	4		T76	3		T12	8
valid_sources[0x51]	913	1			T17	1		T57	1		T25	1
valid_sources[0x52]	1116	1			T5	4		T13	1		T14	4
valid_sources[0x53]	738	1			T5	1		T7	8		T59	3
valid_sources[0x54]	1221	1			T7	3		T76	1		T78	2
valid_sources[0x55]	954	1			T5	1		T14	3		T7	3
valid_sources[0x56]	892	1			T5	1		T13	2		T7	3
valid_sources[0x57]	821	1			T7	4		T57	2		T59	1
valid_sources[0x58]	1198	1			T5	3		T7	1		T25	1
valid_sources[0x59]	840	1			T5	1		T6	1		T7	2
valid_sources[0x5a]	732	1			T5	4		T7	3		T57	5
valid_sources[0x5b]	2371	1			T7	2		T76	1		T8	10
valid_sources[0x5c]	809	1			T14	2		T7	1		T32	1
valid_sources[0x5d]	714	1			T7	2		T57	1		T8	1
valid_sources[0x5e]	857	1			T5	7		T7	1		T57	1
valid_sources[0x5f]	884	1			T5	1		T57	2		T59	1
valid_sources[0x60]	937	1			T14	3		T7	3		T57	2
valid_sources[0x61]	923	1			T5	2		T17	1		T7	1
valid_sources[0x62]	796	1			T5	4		T7	3		T76	1
valid_sources[0x63]	718	1			T5	2		T7	3		T8	3
valid_sources[0x64]	758	1			T5	1		T7	3		T59	2
valid_sources[0x65]	820	1			T7	3		T76	1		T270	1
valid_sources[0x66]	1807	1			T14	1		T7	4		T57	3
valid_sources[0x67]	968	1			T5	1		T7	3		T59	1
valid_sources[0x68]	957	1			T5	2		T7	4		T57	1
valid_sources[0x69]	1031	1			T7	5		T57	3		T10	1
valid_sources[0x6a]	713	1			T7	2		T57	6		T59	1
valid_sources[0x6b]	902	1			T2	1		T7	4		T76	2
valid_sources[0x6c]	712	1			T5	1		T7	4		T57	2
valid_sources[0x6d]	841	1			T57	1		T81	15		T218	2
valid_sources[0x6e]	1006	1			T26	4		T7	3		T57	3
valid_sources[0x6f]	768	1			T5	1		T14	1		T7	1
valid_sources[0x70]	886	1			T13	2		T14	2		T7	1
valid_sources[0x71]	737	1			T5	3		T14	1		T7	1
valid_sources[0x72]	822	1			T5	1		T17	1		T50	16
valid_sources[0x73]	1334	1			T3	19		T7	2		T76	1
valid_sources[0x74]	779	1			T5	1		T6	1		T7	2
valid_sources[0x75]	1341	1			T13	2		T7	1		T57	1
valid_sources[0x76]	714	1			T7	3		T76	1		T11	1
valid_sources[0x77]	899	1			T5	1		T62	2		T8	4
valid_sources[0x78]	749	1			T5	1		T7	1		T57	1
valid_sources[0x79]	725	1			T5	3		T13	1		T7	1
valid_sources[0x7a]	1119	1			T5	1		T57	4		T59	1
valid_sources[0x7b]	829	1			T7	1		T285	1		T12	5
valid_sources[0x7c]	929	1			T6	1		T7	4		T76	2
valid_sources[0x7d]	876	1			T1	1		T5	2		T7	2
valid_sources[0x7e]	749	1			T7	3		T8	2		T10	1
valid_sources[0x7f]	1079	1			T14	2		T7	3		T57	1
valid_sources[0x80]	942	1			T5	2		T14	5		T7	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

57048

1

T4

1

T1

7

T5

108

values[0x0]

all_enables

biggest_size

28315

1

T1

2

T5

25

T13

8

values[0x1]

all_enables

biggest_size

20231

1

T5

11

T13

2

T2

1