Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T5,T26,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T5,T26,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T5,T26,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T26,T7
1	0	Covered	T1,T5,T13
1	1	Covered	T5,T26,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T7
0	1	Covered	T50,T91,T114
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T7
0	1	Covered	T5,T26,T7
1	0	Covered	T22

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T26,T7
1	-	Covered	T5,T26,T7

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T26,T7
DetectSt	168	Covered	T5,T26,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T5,T26,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T26,T7
DebounceSt->IdleSt	163	Covered	T50,T51,T52
DetectSt->IdleSt	186	Covered	T50,T91,T114
DetectSt->StableSt	191	Covered	T5,T26,T7
IdleSt->DebounceSt	148	Covered	T5,T26,T7
StableSt->IdleSt	206	Covered	T5,T26,T7

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T26,T7
0	1	Covered	T5,T26,T7
0	0	Excluded	T4,T1,T5	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T5,T26,T7
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T26,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T64
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T26,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T51,T135
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T26,T7
DetectSt	-	-	-	-	1	-	-	Covered	T50,T91,T114
DetectSt	-	-	-	-	0	1	-	Covered	T5,T26,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T26,T7
StableSt	-	-	-	-	-	-	0	Covered	T5,T26,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	160	0	0
CntIncr_A	7086443	170007	0	0
CntNoWrap_A	7086443	6620403	0	0
DetectStDropOut_A	7086443	3	0	0
DetectedOut_A	7086443	499	0	0
DetectedPulseOut_A	7086443	72	0	0
DisabledIdleSt_A	7086443	6446969	0	0
DisabledNoDetection_A	7086443	6448822	0	0
EnterDebounceSt_A	7086443	86	0	0
EnterDetectSt_A	7086443	75	0	0
EnterStableSt_A	7086443	72	0	0
PulseIsPulse_A	7086443	72	0	0
StayInStableSt	7086443	427	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7086443	5522	0	0
gen_low_level_sva.LowLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	71	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7086443	160
T2	515	0
T3	280535	0
T5	3643	2
T6	896	0
T7	0	4
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	2
T26	778	4
T50	0	5
T51	0	3
T52	0	2
T56	0	4
T102	0	2
T103	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	7086443	170007
T2	515	0
T3	280535	0
T5	3643	85
T6	896	0
T7	0	124
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	24
T26	778	166
T50	0	126
T51	0	136
T52	0	120
T56	0	97
T102	0	31
T103	0	66

CntNoWrap_A

Name	Attempts	Real Successes
Total	7086443	6620403
T1	916	515
T2	515	114
T3	280535	280134
T4	591	190
T5	3643	1596
T13	492	91
T14	1418	216
T15	1003	602
T16	443	42
T17	420	19

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7086443	3
T8	19403	0
T25	522	0
T50	622	1
T58	410	0
T59	522	0
T60	403	0
T61	516	0
T62	502	0
T63	407	0
T76	502	0
T91	0	1
T114	0	1

DetectedOut_A

Name	Attempts	Real Successes
Total	7086443	499
T2	515	0
T3	280535	0
T5	3643	2
T6	896	0
T7	0	20
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	14
T26	778	17
T50	0	2
T51	0	3
T52	0	7
T56	0	5
T102	0	12
T103	0	14

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7086443	72
T2	515	0
T3	280535	0
T5	3643	1
T6	896	0
T7	0	2
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	1
T26	778	2
T50	0	1
T51	0	1
T52	0	1
T56	0	2
T102	0	1
T103	0	2

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7086443	6446969
T1	916	515
T2	515	114
T3	280535	280134
T4	591	190
T5	3643	1464
T13	492	91
T14	1418	216
T15	1003	602
T16	443	42
T17	420	19

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7086443	6448822
T1	916	516
T2	515	115
T3	280535	280135
T4	591	191
T5	3643	1472
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7086443	86
T2	515	0
T3	280535	0
T5	3643	1
T6	896	0
T7	0	2
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	1
T26	778	2
T50	0	3
T51	0	2
T52	0	2
T56	0	2
T102	0	1
T103	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7086443	75
T2	515	0
T3	280535	0
T5	3643	1
T6	896	0
T7	0	2
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	1
T26	778	2
T50	0	2
T51	0	1
T52	0	1
T56	0	2
T102	0	1
T103	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	7086443	72
T2	515	0
T3	280535	0
T5	3643	1
T6	896	0
T7	0	2
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	1
T26	778	2
T50	0	1
T51	0	1
T52	0	1
T56	0	2
T102	0	1
T103	0	2

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7086443	72
T2	515	0
T3	280535	0
T5	3643	1
T6	896	0
T7	0	2
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	1
T26	778	2
T50	0	1
T51	0	1
T52	0	1
T56	0	2
T102	0	1
T103	0	2

StayInStableSt

Name	Attempts	Real Successes
Total	7086443	427
T2	515	0
T3	280535	0
T5	3643	1
T6	896	0
T7	0	18
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	13
T26	778	15
T50	0	1
T51	0	2
T52	0	6
T56	0	3
T102	0	11
T103	0	12

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7086443	5522
T1	916	2
T2	515	1
T3	280535	4
T5	3643	7
T6	896	1
T13	492	7
T14	1418	13
T15	1003	4
T16	443	0
T17	420	2
T26	0	3

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7086443	6622447
T1	916	516
T2	515	115
T3	280535	280135
T4	591	191
T5	3643	1606
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7086443	71
T2	515	0
T3	280535	0
T5	3643	1
T6	896	0
T7	0	2
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T26	778	2
T50	0	1
T51	0	1
T52	0	1
T56	0	2
T102	0	1
T103	0	2
T123	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T33,T67

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T22,T23
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T67
0	1	Covered	T94,T101
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T67
0	1	Unreachable
1	0	Covered	T3,T33,T67

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T22,T23
DetectSt	168	Covered	T3,T33,T67
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T33,T67

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T33,T67
DebounceSt->IdleSt	163	Covered	T22,T23,T66
DetectSt->IdleSt	186	Covered	T94,T101
DetectSt->StableSt	191	Covered	T3,T33,T67
IdleSt->DebounceSt	148	Covered	T3,T22,T23
StableSt->IdleSt	206	Covered	T3,T33,T67

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T22,T23
0	1	Covered	T3,T22,T23
0	0	Excluded	T4,T1,T5	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T33,T67
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T22,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T33,T67
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T66,T68
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T94,T101
DetectSt	-	-	-	-	0	1	-	Covered	T3,T33,T67
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T33,T67
StableSt	-	-	-	-	-	-	0	Covered	T3,T33,T67
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	134	0	0
CntIncr_A	7086443	757861	0	0
CntNoWrap_A	7086443	6620429	0	0
DetectStDropOut_A	7086443	6	0	0
DetectedOut_A	7086443	377907	0	0
DetectedPulseOut_A	7086443	29	0	0
DisabledIdleSt_A	7086443	5188338	0	0
DisabledNoDetection_A	7086443	5190218	0	0
EnterDebounceSt_A	7086443	99	0	0
EnterDetectSt_A	7086443	35	0	0
EnterStableSt_A	7086443	29	0	0
PulseIsPulse_A	7086443	29	0	0
StayInStableSt	7086443	377878	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7086443	5522	0	0
gen_low_level_sva.LowLevelEvent_A	7086443	6622447	0	0
gen_sticky_sva.StableStDropOut_A	7086443	214811	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7086443	134
T3	280535	2
T6	896	0
T7	16682	0
T17	420	0
T22	0	2
T23	0	6
T25	522	0
T26	778	0
T33	0	2
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T66	0	5
T67	0	2
T68	0	1
T86	0	2
T87	0	2
T88	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7086443	757861
T3	280535	62293
T6	896	0
T7	16682	0
T17	420	0
T22	0	45
T23	0	552
T25	522	0
T26	778	0
T33	0	29
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T66	0	345
T67	0	25
T68	0	92
T86	0	51
T87	0	11
T88	0	72

CntNoWrap_A

Name	Attempts	Real Successes
Total	7086443	6620429
T1	916	515
T2	515	114
T3	280535	280132
T4	591	190
T5	3643	1598
T13	492	91
T14	1418	216
T15	1003	602
T16	443	42
T17	420	19

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7086443	6
T91	750	0
T94	915	1
T101	0	5
T106	5372	0
T125	1286	0
T136	524	0
T137	522	0
T138	26371	0
T139	490	0
T140	753	0
T141	8423	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7086443	377907
T3	280535	217712
T6	896	0
T7	16682	0
T17	420	0
T25	522	0
T26	778	0
T33	0	95
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	21
T86	0	248
T87	0	98
T88	0	79
T94	0	36
T95	0	41
T98	0	122
T124	0	246

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7086443	29
T3	280535	1
T6	896	0
T7	16682	0
T17	420	0
T25	522	0
T26	778	0
T33	0	1
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	1
T86	0	1
T87	0	1
T88	0	1
T94	0	1
T95	0	2
T98	0	1
T124	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7086443	5188338
T1	916	515
T2	515	114
T3	280535	24
T4	591	190
T5	3643	1598
T13	492	91
T14	1418	216
T15	1003	602
T16	443	42
T17	420	19

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7086443	5190218
T1	916	516
T2	515	115
T3	280535	25
T4	591	191
T5	3643	1606
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7086443	99
T3	280535	1
T6	896	0
T7	16682	0
T17	420	0
T22	0	2
T23	0	6
T25	522	0
T26	778	0
T33	0	1
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T66	0	5
T67	0	1
T68	0	1
T86	0	1
T87	0	1
T88	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7086443	35
T3	280535	1
T6	896	0
T7	16682	0
T17	420	0
T25	522	0
T26	778	0
T33	0	1
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	1
T86	0	1
T87	0	1
T88	0	1
T94	0	2
T95	0	2
T98	0	1
T124	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7086443	29
T3	280535	1
T6	896	0
T7	16682	0
T17	420	0
T25	522	0
T26	778	0
T33	0	1
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	1
T86	0	1
T87	0	1
T88	0	1
T94	0	1
T95	0	2
T98	0	1
T124	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7086443	29
T3	280535	1
T6	896	0
T7	16682	0
T17	420	0
T25	522	0
T26	778	0
T33	0	1
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	1
T86	0	1
T87	0	1
T88	0	1
T94	0	1
T95	0	2
T98	0	1
T124	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7086443	377878
T3	280535	217711
T6	896	0
T7	16682	0
T17	420	0
T25	522	0
T26	778	0
T33	0	94
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	20
T86	0	247
T87	0	97
T88	0	78
T94	0	35
T95	0	39
T98	0	121
T124	0	245

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7086443	5522
T1	916	2
T2	515	1
T3	280535	4
T5	3643	7
T6	896	1
T13	492	7
T14	1418	13
T15	1003	4
T16	443	0
T17	420	2
T26	0	3

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7086443	6622447
T1	916	516
T2	515	115
T3	280535	280135
T4	591	191
T5	3643	1606
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7086443	214811
T3	280535	82
T6	896	0
T7	16682	0
T17	420	0
T25	522	0
T26	778	0
T33	0	124699
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	111
T86	0	144
T87	0	240
T88	0	200
T94	0	124
T95	0	173
T98	0	107
T124	0	120

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T23,T67

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T22,T23
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T67
0	1	Covered	T98,T99,T100
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T67
0	1	Unreachable
1	0	Covered	T3,T23,T67

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T22,T23
DetectSt	168	Covered	T3,T23,T67
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T23,T67

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T23,T67
DebounceSt->IdleSt	163	Covered	T22,T66,T33
DetectSt->IdleSt	186	Covered	T98,T99,T100
DetectSt->StableSt	191	Covered	T3,T23,T67
IdleSt->DebounceSt	148	Covered	T3,T22,T23
StableSt->IdleSt	206	Covered	T3,T23,T67

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T22,T23
0	1	Covered	T3,T22,T23
0	0	Excluded	T4,T1,T5	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T23,T67
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T22,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T23,T67
DebounceSt	-	0	1	0	-	-	-	Covered	T66,T33,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T98,T99,T100
DetectSt	-	-	-	-	0	1	-	Covered	T3,T23,T67
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T23,T67
StableSt	-	-	-	-	-	-	0	Covered	T3,T23,T67
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	132	0	0
CntIncr_A	7086443	84576	0	0
CntNoWrap_A	7086443	6620431	0	0
DetectStDropOut_A	7086443	4	0	0
DetectedOut_A	7086443	87709	0	0
DetectedPulseOut_A	7086443	31	0	0
DisabledIdleSt_A	7086443	5188338	0	0
DisabledNoDetection_A	7086443	5190218	0	0
EnterDebounceSt_A	7086443	97	0	0
EnterDetectSt_A	7086443	35	0	0
EnterStableSt_A	7086443	31	0	0
PulseIsPulse_A	7086443	31	0	0
StayInStableSt	7086443	87678	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_sticky_sva.StableStDropOut_A	7086443	343677	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7086443	132
T3	280535	2
T6	896	0
T7	16682	0
T17	420	0
T22	0	2
T23	0	6
T25	522	0
T26	778	0
T33	0	3
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T66	0	5
T67	0	2
T68	0	2
T86	0	4
T87	0	5
T88	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7086443	84576
T3	280535	95
T6	896	0
T7	16682	0
T17	420	0
T22	0	44
T23	0	162
T25	522	0
T26	778	0
T33	0	168
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T66	0	265
T67	0	39
T68	0	80
T86	0	276
T87	0	190
T88	0	96

CntNoWrap_A

Name	Attempts	Real Successes
Total	7086443	6620431
T1	916	515
T2	515	114
T3	280535	280132
T4	591	190
T5	3643	1598
T13	492	91
T14	1418	216
T15	1003	602
T16	443	42
T17	420	19

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7086443	4
T95	979	0
T98	1431	1
T99	0	1
T100	0	1
T142	0	1
T143	632	0
T144	436	0
T145	15321	0
T146	498	0
T147	660	0
T148	913	0
T149	7150	0
T150	435	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7086443	87709
T3	280535	618
T6	896	0
T7	16682	0
T17	420	0
T23	0	233
T25	522	0
T26	778	0
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	21
T68	0	44
T86	0	94
T94	0	230
T124	0	292
T125	0	244
T126	0	38259
T127	0	92

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7086443	31
T3	280535	1
T6	896	0
T7	16682	0
T17	420	0
T23	0	3
T25	522	0
T26	778	0
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	1
T68	0	1
T86	0	1
T94	0	1
T124	0	1
T125	0	2
T126	0	1
T127	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7086443	5188338
T1	916	515
T2	515	114
T3	280535	24
T4	591	190
T5	3643	1598
T13	492	91
T14	1418	216
T15	1003	602
T16	443	42
T17	420	19

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7086443	5190218
T1	916	516
T2	515	115
T3	280535	25
T4	591	191
T5	3643	1606
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7086443	97
T3	280535	1
T6	896	0
T7	16682	0
T17	420	0
T22	0	2
T23	0	3
T25	522	0
T26	778	0
T33	0	3
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T66	0	5
T67	0	1
T68	0	1
T86	0	3
T87	0	5
T88	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7086443	35
T3	280535	1
T6	896	0
T7	16682	0
T17	420	0
T23	0	3
T25	522	0
T26	778	0
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	1
T68	0	1
T86	0	1
T94	0	1
T124	0	1
T125	0	2
T126	0	1
T127	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7086443	31
T3	280535	1
T6	896	0
T7	16682	0
T17	420	0
T23	0	3
T25	522	0
T26	778	0
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	1
T68	0	1
T86	0	1
T94	0	1
T124	0	1
T125	0	2
T126	0	1
T127	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7086443	31
T3	280535	1
T6	896	0
T7	16682	0
T17	420	0
T23	0	3
T25	522	0
T26	778	0
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	1
T68	0	1
T86	0	1
T94	0	1
T124	0	1
T125	0	2
T126	0	1
T127	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7086443	87678
T3	280535	617
T6	896	0
T7	16682	0
T17	420	0
T23	0	230
T25	522	0
T26	778	0
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	20
T68	0	43
T86	0	93
T94	0	229
T124	0	291
T125	0	242
T126	0	38258
T127	0	91

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7086443	6622447
T1	916	516
T2	515	115
T3	280535	280135
T4	591	191
T5	3643	1606
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7086443	343677
T3	280535	279384
T6	896	0
T7	16682	0
T17	420	0
T23	0	481
T25	522	0
T26	778	0
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T67	0	106
T68	0	52
T86	0	52
T94	0	77
T124	0	90
T125	0	452
T126	0	123
T127	0	501

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T33,T68

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T22,T23
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T68,T86
0	1	Covered	T3,T94,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T68,T86
0	1	Unreachable
1	0	Covered	T33,T68,T86

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T22,T23
DetectSt	168	Covered	T3,T33,T68
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T33,T68,T86

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T33,T68
DebounceSt->IdleSt	163	Covered	T3,T22,T23
DetectSt->IdleSt	186	Covered	T3,T94,T95
DetectSt->StableSt	191	Covered	T33,T68,T86
IdleSt->DebounceSt	148	Covered	T3,T22,T23
StableSt->IdleSt	206	Covered	T33,T68,T86

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T22,T23
0	1	Covered	T3,T22,T23
0	0	Excluded	T4,T1,T5	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T33,T68
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T22,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T33,T68
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T23,T66
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T3,T94,T95
DetectSt	-	-	-	-	0	1	-	Covered	T33,T68,T86
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T68,T86
StableSt	-	-	-	-	-	-	0	Covered	T33,T68,T86
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	151	0	0
CntIncr_A	7086443	41929	0	0
CntNoWrap_A	7086443	6620412	0	0
DetectStDropOut_A	7086443	16	0	0
DetectedOut_A	7086443	94285	0	0
DetectedPulseOut_A	7086443	29	0	0
DisabledIdleSt_A	7086443	5188338	0	0
DisabledNoDetection_A	7086443	5190218	0	0
EnterDebounceSt_A	7086443	106	0	0
EnterDetectSt_A	7086443	45	0	0
EnterStableSt_A	7086443	29	0	0
PulseIsPulse_A	7086443	29	0	0
StayInStableSt	7086443	94256	0	0
gen_high_event_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_sticky_sva.StableStDropOut_A	7086443	354879	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7086443	151
T3	280535	7
T6	896	0
T7	16682	0
T17	420	0
T22	0	2
T23	0	6
T25	522	0
T26	778	0
T33	0	2
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T66	0	5
T67	0	1
T68	0	2
T86	0	2
T87	0	5
T88	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7086443	41929
T3	280535	332
T6	896	0
T7	16682	0
T17	420	0
T22	0	46
T23	0	588
T25	522	0
T26	778	0
T33	0	35196
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T66	0	465
T67	0	95
T68	0	62
T86	0	99
T87	0	310
T88	0	75

CntNoWrap_A

Name	Attempts	Real Successes
Total	7086443	6620412
T1	916	515
T2	515	114
T3	280535	280127
T4	591	190
T5	3643	1598
T13	492	91
T14	1418	216
T15	1003	602
T16	443	42
T17	420	19

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7086443	16
T3	280535	3
T6	896	0
T7	16682	0
T17	420	0
T25	522	0
T26	778	0
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T94	0	3
T95	0	1
T142	0	1
T148	0	3
T151	0	1
T152	0	1
T153	0	3

DetectedOut_A

Name	Attempts	Real Successes
Total	7086443	94285
T33	129212	89559
T68	0	17
T86	0	298
T88	0	216
T95	0	1
T98	0	193
T103	672	0
T123	684	0
T124	0	195
T125	0	530
T126	0	64
T127	0	255
T128	423	0
T129	402	0
T130	526	0
T131	79704	0
T132	687	0
T133	31541	0
T134	651	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7086443	29
T33	129212	1
T68	0	1
T86	0	1
T88	0	1
T95	0	1
T98	0	1
T103	672	0
T123	684	0
T124	0	1
T125	0	2
T126	0	1
T127	0	1
T128	423	0
T129	402	0
T130	526	0
T131	79704	0
T132	687	0
T133	31541	0
T134	651	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7086443	5188338
T1	916	515
T2	515	114
T3	280535	24
T4	591	190
T5	3643	1598
T13	492	91
T14	1418	216
T15	1003	602
T16	443	42
T17	420	19

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7086443	5190218
T1	916	516
T2	515	115
T3	280535	25
T4	591	191
T5	3643	1606
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7086443	106
T3	280535	4
T6	896	0
T7	16682	0
T17	420	0
T22	0	2
T23	0	6
T25	522	0
T26	778	0
T33	0	1
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T66	0	5
T67	0	1
T68	0	1
T86	0	1
T87	0	5
T88	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7086443	45
T3	280535	3
T6	896	0
T7	16682	0
T17	420	0
T25	522	0
T26	778	0
T33	0	1
T50	622	0
T57	1154	0
T58	410	0
T59	522	0
T68	0	1
T86	0	1
T88	0	1
T94	0	3
T124	0	1
T125	0	2
T126	0	1
T127	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7086443	29
T33	129212	1
T68	0	1
T86	0	1
T88	0	1
T95	0	1
T98	0	1
T103	672	0
T123	684	0
T124	0	1
T125	0	2
T126	0	1
T127	0	1
T128	423	0
T129	402	0
T130	526	0
T131	79704	0
T132	687	0
T133	31541	0
T134	651	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7086443	29
T33	129212	1
T68	0	1
T86	0	1
T88	0	1
T95	0	1
T98	0	1
T103	672	0
T123	684	0
T124	0	1
T125	0	2
T126	0	1
T127	0	1
T128	423	0
T129	402	0
T130	526	0
T131	79704	0
T132	687	0
T133	31541	0
T134	651	0

StayInStableSt

Name	Attempts	Real Successes
Total	7086443	94256
T33	129212	89558
T68	0	16
T86	0	297
T88	0	215
T98	0	192
T103	672	0
T123	684	0
T124	0	194
T125	0	528
T126	0	63
T127	0	254
T128	423	0
T129	402	0
T130	526	0
T131	79704	0
T132	687	0
T133	31541	0
T134	651	0
T154	0	38

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7086443	6622447
T1	916	516
T2	515	115
T3	280535	280135
T4	591	191
T5	3643	1606
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7086443	6622447
T1	916	516
T2	515	115
T3	280535	280135
T4	591	191
T5	3643	1606
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7086443	354879
T33	129212	76
T68	0	117
T86	0	60
T88	0	65
T95	0	48
T98	0	37
T103	672	0
T123	684	0
T124	0	182
T125	0	101
T126	0	76538
T127	0	290
T128	423	0
T129	402	0
T130	526	0
T131	79704	0
T132	687	0
T133	31541	0
T134	651	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T48,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T22,T48,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T48,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T22,T40
1	0	Covered	T4,T1,T5
1	1	Covered	T22,T48,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T48,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T48,T33
0	1	Covered	T33,T155,T156
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T48,T33
1	-	Covered	T33,T155,T156

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T48,T33
DetectSt	168	Covered	T22,T48,T33
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T22,T48,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T48,T33
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T22,T48,T33
IdleSt->DebounceSt	148	Covered	T22,T48,T33
StableSt->IdleSt	206	Covered	T22,T33,T64

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T48,T33
0	1	Covered	T22,T48,T33
0	0	Excluded	T4,T1,T5	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T22,T48,T33
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T48,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T48,T33
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T48,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T22,T48,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T33,T64
StableSt	-	-	-	-	-	-	0	Covered	T22,T48,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	32	0	0
CntIncr_A	7086443	885	0	0
CntNoWrap_A	7086443	6620531	0	0
DetectStDropOut_A	7086443	0	0	0
DetectedOut_A	7086443	836	0	0
DetectedPulseOut_A	7086443	16	0	0
DisabledIdleSt_A	7086443	6530214	0	0
DisabledNoDetection_A	7086443	6532070	0	0
EnterDebounceSt_A	7086443	16	0	0
EnterDetectSt_A	7086443	16	0	0
EnterStableSt_A	7086443	16	0	0
PulseIsPulse_A	7086443	16	0	0
StayInStableSt	7086443	810	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	4	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7086443	32
T22	8418	2
T33	0	2
T40	3408	0
T48	898	2
T49	0	2
T56	716	0
T64	0	2
T72	496	0
T155	0	2
T157	0	2
T158	0	2
T159	0	2
T160	0	2
T161	503	0
T162	425	0
T163	414	0
T164	11176	0
T165	812	0

CntIncr_A

Name	Attempts	Real Successes
Total	7086443	885
T22	8418	35
T33	0	44
T40	3408	0
T48	898	100
T49	0	52
T56	716	0
T64	0	26
T72	496	0
T155	0	60
T157	0	64
T158	0	73
T159	0	59
T160	0	60
T161	503	0
T162	425	0
T163	414	0
T164	11176	0
T165	812	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	7086443	6620531
T1	916	515
T2	515	114
T3	280535	280134
T4	591	190
T5	3643	1598
T13	492	91
T14	1418	216
T15	1003	602
T16	443	42
T17	420	19

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7086443	836
T22	8418	11
T33	0	113
T40	3408	0
T48	898	45
T49	0	39
T56	716	0
T64	0	10
T72	496	0
T155	0	135
T157	0	38
T158	0	39
T159	0	45
T160	0	47
T161	503	0
T162	425	0
T163	414	0
T164	11176	0
T165	812	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7086443	16
T22	8418	1
T33	0	1
T40	3408	0
T48	898	1
T49	0	1
T56	716	0
T64	0	1
T72	496	0
T155	0	1
T157	0	1
T158	0	1
T159	0	1
T160	0	1
T161	503	0
T162	425	0
T163	414	0
T164	11176	0
T165	812	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7086443	6530214
T1	916	515
T2	515	114
T3	280535	280134
T4	591	190
T5	3643	1598
T13	492	91
T14	1418	216
T15	1003	602
T16	443	42
T17	420	19

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7086443	6532070
T1	916	516
T2	515	115
T3	280535	280135
T4	591	191
T5	3643	1606
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7086443	16
T22	8418	1
T33	0	1
T40	3408	0
T48	898	1
T49	0	1
T56	716	0
T64	0	1
T72	496	0
T155	0	1
T157	0	1
T158	0	1
T159	0	1
T160	0	1
T161	503	0
T162	425	0
T163	414	0
T164	11176	0
T165	812	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7086443	16
T22	8418	1
T33	0	1
T40	3408	0
T48	898	1
T49	0	1
T56	716	0
T64	0	1
T72	496	0
T155	0	1
T157	0	1
T158	0	1
T159	0	1
T160	0	1
T161	503	0
T162	425	0
T163	414	0
T164	11176	0
T165	812	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	7086443	16
T22	8418	1
T33	0	1
T40	3408	0
T48	898	1
T49	0	1
T56	716	0
T64	0	1
T72	496	0
T155	0	1
T157	0	1
T158	0	1
T159	0	1
T160	0	1
T161	503	0
T162	425	0
T163	414	0
T164	11176	0
T165	812	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7086443	16
T22	8418	1
T33	0	1
T40	3408	0
T48	898	1
T49	0	1
T56	716	0
T64	0	1
T72	496	0
T155	0	1
T157	0	1
T158	0	1
T159	0	1
T160	0	1
T161	503	0
T162	425	0
T163	414	0
T164	11176	0
T165	812	0

StayInStableSt

Name	Attempts	Real Successes
Total	7086443	810
T22	8418	10
T33	0	112
T40	3408	0
T48	898	43
T49	0	37
T56	716	0
T64	0	9
T72	496	0
T155	0	134
T157	0	36
T158	0	37
T159	0	43
T160	0	45
T161	503	0
T162	425	0
T163	414	0
T164	11176	0
T165	812	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7086443	6622447
T1	916	516
T2	515	115
T3	280535	280135
T4	591	191
T5	3643	1606
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7086443	4
T33	129212	1
T103	672	0
T123	684	0
T128	423	0
T129	402	0
T130	526	0
T131	79704	0
T132	687	0
T133	31541	0
T134	651	0
T155	0	1
T156	0	1
T166	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T2,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T5,T13,T14
1	1	Covered	T1,T2,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T10
0	1	Covered	T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T10
0	1	Covered	T1,T2,T10
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T10
1	-	Covered	T1,T2,T10

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T10
DetectSt	168	Covered	T1,T2,T10
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T2,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T10
DebounceSt->IdleSt	163	Covered	T43,T167,T168
DetectSt->IdleSt	186	Covered	T166
DetectSt->StableSt	191	Covered	T1,T2,T10
IdleSt->DebounceSt	148	Covered	T1,T2,T10
StableSt->IdleSt	206	Covered	T1,T2,T10

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T10
0	1	Covered	T1,T2,T10
0	0	Excluded	T4,T1,T5	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T167,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T10
DetectSt	-	-	-	-	1	-	-	Covered	T166
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	77	0	0
CntIncr_A	7086443	244493	0	0
CntNoWrap_A	7086443	6620486	0	0
DetectStDropOut_A	7086443	1	0	0
DetectedOut_A	7086443	235467	0	0
DetectedPulseOut_A	7086443	36	0	0
DisabledIdleSt_A	7086443	5880402	0	0
DisabledNoDetection_A	7086443	5882254	0	0
EnterDebounceSt_A	7086443	40	0	0
EnterDetectSt_A	7086443	37	0	0
EnterStableSt_A	7086443	36	0	0
PulseIsPulse_A	7086443	36	0	0
StayInStableSt	7086443	235416	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7086443	1629	0	0
gen_low_level_sva.LowLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	19	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7086443	77
T1	916	2
T2	515	2
T3	280535	0
T5	3643	0
T6	896	0
T10	0	2
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	2
T40	0	2
T42	0	2
T43	0	1
T48	0	2
T49	0	2
T131	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7086443	244493
T1	916	59
T2	515	30
T3	280535	0
T5	3643	0
T6	896	0
T10	0	13
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	35
T40	0	536
T42	0	85
T43	0	74
T48	0	100
T49	0	52
T131	0	28043

CntNoWrap_A

Name	Attempts	Real Successes
Total	7086443	6620486
T1	916	513
T2	515	112
T3	280535	280134
T4	591	190
T5	3643	1598
T13	492	91
T14	1418	216
T15	1003	602
T16	443	42
T17	420	19

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7086443	1
T90	15257	0
T166	6708	1
T169	549	0
T170	21572	0
T171	5367	0
T172	502	0
T173	694	0
T174	402	0
T175	8897	0
T176	405	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7086443	235467
T1	916	270
T2	515	3
T3	280535	0
T5	3643	0
T6	896	0
T10	0	62
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	12
T40	0	2463
T42	0	316
T48	0	243
T49	0	31
T131	0	40
T177	0	10

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7086443	36
T1	916	1
T2	515	1
T3	280535	0
T5	3643	0
T6	896	0
T10	0	1
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	1
T40	0	1
T42	0	1
T48	0	1
T49	0	1
T131	0	1
T177	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7086443	5880402
T1	916	3
T2	515	4
T3	280535	280134
T4	591	190
T5	3643	1598
T13	492	91
T14	1418	216
T15	1003	602
T16	443	42
T17	420	19

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7086443	5882254
T1	916	3
T2	515	4
T3	280535	280135
T4	591	191
T5	3643	1606
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7086443	40
T1	916	1
T2	515	1
T3	280535	0
T5	3643	0
T6	896	0
T10	0	1
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	1
T40	0	1
T42	0	1
T43	0	1
T48	0	1
T49	0	1
T131	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7086443	37
T1	916	1
T2	515	1
T3	280535	0
T5	3643	0
T6	896	0
T10	0	1
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	1
T40	0	1
T42	0	1
T48	0	1
T49	0	1
T131	0	1
T177	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7086443	36
T1	916	1
T2	515	1
T3	280535	0
T5	3643	0
T6	896	0
T10	0	1
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	1
T40	0	1
T42	0	1
T48	0	1
T49	0	1
T131	0	1
T177	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7086443	36
T1	916	1
T2	515	1
T3	280535	0
T5	3643	0
T6	896	0
T10	0	1
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	1
T40	0	1
T42	0	1
T48	0	1
T49	0	1
T131	0	1
T177	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7086443	235416
T1	916	269
T2	515	2
T3	280535	0
T5	3643	0
T6	896	0
T10	0	61
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T22	0	11
T40	0	2461
T42	0	314
T48	0	242
T49	0	30
T131	0	38
T177	0	9

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7086443	1629
T1	916	1
T2	515	1
T3	280535	0
T5	3643	6
T6	896	2
T13	492	6
T14	1418	10
T15	1003	0
T16	443	0
T17	420	2
T25	0	7
T58	0	1
T59	0	6

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7086443	6622447
T1	916	516
T2	515	115
T3	280535	280135
T4	591	191
T5	3643	1606
T13	492	92
T14	1418	218
T15	1003	603
T16	443	43
T17	420	20

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7086443	19
T1	916	1
T2	515	1
T3	280535	0
T5	3643	0
T6	896	0
T10	0	1
T13	492	0
T14	1418	0
T15	1003	0
T16	443	0
T17	420	0
T48	0	1
T49	0	1
T157	0	1
T158	0	1
T177	0	1
T178	0	2
T179	0	1

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr