Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T6,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T6,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T6,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T4,T1,T5
1	1	Covered	T1,T6,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T22
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T22
0	1	Covered	T1,T6,T178
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T22
1	-	Covered	T1,T6,T178

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T22
DetectSt	168	Covered	T1,T6,T22
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T6,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T22
DebounceSt->IdleSt	163	Covered	T33,T180
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T6,T22
IdleSt->DebounceSt	148	Covered	T1,T6,T22
StableSt->IdleSt	206	Covered	T1,T6,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T22
0	1	Covered	T1,T6,T22
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T22
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T22
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T22
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	50	0	0
CntIncr_A	7086443	57422	0	0
CntNoWrap_A	7086443	6620513	0	0
DetectStDropOut_A	7086443	0	0	0
DetectedOut_A	7086443	8346	0	0
DetectedPulseOut_A	7086443	24	0	0
DisabledIdleSt_A	7086443	6291427	0	0
DisabledNoDetection_A	7086443	6293279	0	0
EnterDebounceSt_A	7086443	26	0	0
EnterDetectSt_A	7086443	24	0	0
EnterStableSt_A	7086443	24	0	0
PulseIsPulse_A	7086443	24	0	0
StayInStableSt	7086443	8309	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	50	0	0
T1	916	4	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	2	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	2	0	0
T33	0	3	0	0
T41	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T134	0	2	0	0
T181	0	2	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	57422	0	0
T1	916	118	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	53	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	35	0	0
T33	0	88	0	0
T41	0	40	0	0
T45	0	75	0	0
T46	0	47	0	0
T134	0	33	0	0
T181	0	68	0	0
T182	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6620513	0	0
T1	916	511	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	8346	0	0
T1	916	217	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	26	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	12	0	0
T33	0	51	0	0
T41	0	321	0	0
T45	0	101	0	0
T46	0	39	0	0
T134	0	37	0	0
T181	0	39	0	0
T182	0	158	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	24	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T134	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6291427	0	0
T1	916	3	0	0
T2	515	4	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6293279	0	0
T1	916	3	0	0
T2	515	4	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	26	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T134	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	24	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T134	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	24	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T134	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	24	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T134	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	8309	0	0
T1	916	214	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	25	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	11	0	0
T33	0	49	0	0
T41	0	319	0	0
T45	0	99	0	0
T46	0	37	0	0
T134	0	35	0	0
T181	0	37	0	0
T182	0	156	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	9	0	0
T1	916	1	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T166	0	1	0	0
T168	0	1	0	0
T178	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T43,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T43,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T43,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T43,T22
1	0	Covered	T4,T5,T13
1	1	Covered	T1,T43,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T43,T22
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T43,T22
0	1	Covered	T1,T33,T45
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T43,T22
1	-	Covered	T1,T33,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T43,T22
DetectSt	168	Covered	T1,T43,T22
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T43,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T43,T22
DebounceSt->IdleSt	163	Covered	T187
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T43,T22
IdleSt->DebounceSt	148	Covered	T1,T43,T22
StableSt->IdleSt	206	Covered	T1,T22,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T43,T22
0	1	Covered	T1,T43,T22
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T43,T22
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T43,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T43,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T187
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T43,T22
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T43,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T22,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T43,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	69	0	0
CntIncr_A	7086443	51321	0	0
CntNoWrap_A	7086443	6620494	0	0
DetectStDropOut_A	7086443	0	0	0
DetectedOut_A	7086443	53724	0	0
DetectedPulseOut_A	7086443	34	0	0
DisabledIdleSt_A	7086443	6475056	0	0
DisabledNoDetection_A	7086443	6476911	0	0
EnterDebounceSt_A	7086443	35	0	0
EnterDetectSt_A	7086443	34	0	0
EnterStableSt_A	7086443	34	0	0
PulseIsPulse_A	7086443	34	0	0
StayInStableSt	7086443	53676	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7086443	1873	0	0
gen_low_level_sva.LowLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	69	0	0
T1	916	4	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	2	0	0
T33	0	4	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T47	0	2	0	0
T131	0	2	0	0
T157	0	2	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	51321	0	0
T1	916	118	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	35	0	0
T33	0	88	0	0
T43	0	74	0	0
T44	0	81	0	0
T45	0	75	0	0
T47	0	21518	0	0
T131	0	28043	0	0
T157	0	64	0	0
T188	0	93	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6620494	0	0
T1	916	511	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	53724	0	0
T1	916	51	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	11	0	0
T33	0	134	0	0
T43	0	112	0	0
T44	0	39	0	0
T45	0	166	0	0
T47	0	38	0	0
T131	0	51252	0	0
T157	0	39	0	0
T188	0	153	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	34	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T131	0	1	0	0
T157	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6475056	0	0
T1	916	3	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6476911	0	0
T1	916	3	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	35	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T131	0	1	0	0
T157	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	34	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T131	0	1	0	0
T157	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	34	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T131	0	1	0	0
T157	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	34	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T131	0	1	0	0
T157	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	53676	0	0
T1	916	49	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	10	0	0
T33	0	132	0	0
T43	0	110	0	0
T44	0	37	0	0
T45	0	165	0	0
T47	0	36	0	0
T131	0	51250	0	0
T157	0	38	0	0
T188	0	151	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1873	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T4	591	3	0	0
T5	3643	9	0	0
T6	0	2	0	0
T13	492	6	0	0
T14	1418	11	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	2	0	0
T25	0	6	0	0
T58	0	1	0	0
T59	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	18	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T33	0	2	0	0
T45	0	1	0	0
T96	0	1	0	0
T157	0	1	0	0
T178	0	2	0	0
T181	0	1	0	0
T182	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T41,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T22,T41,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T41,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T43,T22,T41
1	0	Covered	T1,T5,T13
1	1	Covered	T22,T41,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T41,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T41,T46
0	1	Covered	T41,T46,T45
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T41,T46
1	-	Covered	T41,T46,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T41,T46
DetectSt	168	Covered	T22,T41,T46
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T22,T41,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T41,T46
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T22,T41,T46
IdleSt->DebounceSt	148	Covered	T22,T41,T46
StableSt->IdleSt	206	Covered	T22,T41,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T41,T46
0	1	Covered	T22,T41,T46
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T41,T46
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T41,T46
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T41,T46
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T41,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T22,T41,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T41,T46
StableSt	-	-	-	-	-	-	0	Covered	T22,T41,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	56	0	0
CntIncr_A	7086443	22917	0	0
CntNoWrap_A	7086443	6620507	0	0
DetectStDropOut_A	7086443	0	0	0
DetectedOut_A	7086443	2213	0	0
DetectedPulseOut_A	7086443	28	0	0
DisabledIdleSt_A	7086443	6555065	0	0
DisabledNoDetection_A	7086443	6556922	0	0
EnterDebounceSt_A	7086443	28	0	0
EnterDetectSt_A	7086443	28	0	0
EnterStableSt_A	7086443	28	0	0
PulseIsPulse_A	7086443	28	0	0
StayInStableSt	7086443	2171	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	56	0	0
T22	8418	2	0	0
T40	3408	0	0	0
T41	0	4	0	0
T45	0	2	0	0
T46	0	4	0	0
T47	0	2	0	0
T48	898	0	0	0
T56	716	0	0	0
T72	496	0	0	0
T157	0	2	0	0
T161	503	0	0	0
T162	425	0	0	0
T163	414	0	0	0
T164	11176	0	0	0
T165	812	0	0	0
T178	0	2	0	0
T181	0	2	0	0
T182	0	2	0	0
T191	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	22917	0	0
T22	8418	35	0	0
T40	3408	0	0	0
T41	0	80	0	0
T45	0	75	0	0
T46	0	94	0	0
T47	0	21518	0	0
T48	898	0	0	0
T56	716	0	0	0
T72	496	0	0	0
T157	0	64	0	0
T161	503	0	0	0
T162	425	0	0	0
T163	414	0	0	0
T164	11176	0	0	0
T165	812	0	0	0
T178	0	58	0	0
T181	0	68	0	0
T182	0	79	0	0
T191	0	59	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6620507	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	2213	0	0
T22	8418	10	0	0
T40	3408	0	0	0
T41	0	256	0	0
T45	0	167	0	0
T46	0	109	0	0
T47	0	38	0	0
T48	898	0	0	0
T56	716	0	0	0
T72	496	0	0	0
T157	0	110	0	0
T161	503	0	0	0
T162	425	0	0	0
T163	414	0	0	0
T164	11176	0	0	0
T165	812	0	0	0
T178	0	44	0	0
T181	0	39	0	0
T182	0	222	0	0
T191	0	159	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	28	0	0
T22	8418	1	0	0
T40	3408	0	0	0
T41	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	898	0	0	0
T56	716	0	0	0
T72	496	0	0	0
T157	0	1	0	0
T161	503	0	0	0
T162	425	0	0	0
T163	414	0	0	0
T164	11176	0	0	0
T165	812	0	0	0
T178	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T191	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6555065	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6556922	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	28	0	0
T22	8418	1	0	0
T40	3408	0	0	0
T41	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	898	0	0	0
T56	716	0	0	0
T72	496	0	0	0
T157	0	1	0	0
T161	503	0	0	0
T162	425	0	0	0
T163	414	0	0	0
T164	11176	0	0	0
T165	812	0	0	0
T178	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T191	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	28	0	0
T22	8418	1	0	0
T40	3408	0	0	0
T41	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	898	0	0	0
T56	716	0	0	0
T72	496	0	0	0
T157	0	1	0	0
T161	503	0	0	0
T162	425	0	0	0
T163	414	0	0	0
T164	11176	0	0	0
T165	812	0	0	0
T178	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T191	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	28	0	0
T22	8418	1	0	0
T40	3408	0	0	0
T41	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	898	0	0	0
T56	716	0	0	0
T72	496	0	0	0
T157	0	1	0	0
T161	503	0	0	0
T162	425	0	0	0
T163	414	0	0	0
T164	11176	0	0	0
T165	812	0	0	0
T178	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T191	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	28	0	0
T22	8418	1	0	0
T40	3408	0	0	0
T41	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	898	0	0	0
T56	716	0	0	0
T72	496	0	0	0
T157	0	1	0	0
T161	503	0	0	0
T162	425	0	0	0
T163	414	0	0	0
T164	11176	0	0	0
T165	812	0	0	0
T178	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T191	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	2171	0	0
T22	8418	9	0	0
T40	3408	0	0	0
T41	0	253	0	0
T45	0	166	0	0
T46	0	106	0	0
T47	0	36	0	0
T48	898	0	0	0
T56	716	0	0	0
T72	496	0	0	0
T157	0	109	0	0
T161	503	0	0	0
T162	425	0	0	0
T163	414	0	0	0
T164	11176	0	0	0
T165	812	0	0	0
T178	0	43	0	0
T181	0	37	0	0
T182	0	221	0	0
T191	0	157	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	12	0	0
T41	826	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T73	2857	0	0	0
T96	0	1	0	0
T102	681	0	0	0
T122	9084	0	0	0
T157	0	1	0	0
T159	0	1	0	0
T166	0	2	0	0
T178	0	1	0	0
T182	0	1	0	0
T192	0	2	0	0
T193	409	0	0	0
T194	1522	0	0	0
T195	501	0	0	0
T196	927	0	0	0
T197	1388	0	0	0
T198	1353	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T11,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T11,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T11,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T43
1	0	Covered	T5,T13,T14
1	1	Covered	T1,T11,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T22
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T22
0	1	Covered	T1,T179,T199
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T22
1	-	Covered	T1,T179,T199

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T22
DetectSt	168	Covered	T1,T11,T22
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T11,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T22
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T11,T22
IdleSt->DebounceSt	148	Covered	T1,T11,T22
StableSt->IdleSt	206	Covered	T1,T22,T179

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T11,T22
0	1	Covered	T1,T11,T22
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T22
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T22
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T22
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T22,T179
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	36	0	0
CntIncr_A	7086443	138431	0	0
CntNoWrap_A	7086443	6620527	0	0
DetectStDropOut_A	7086443	0	0	0
DetectedOut_A	7086443	62152	0	0
DetectedPulseOut_A	7086443	18	0	0
DisabledIdleSt_A	7086443	6111066	0	0
DisabledNoDetection_A	7086443	6112923	0	0
EnterDebounceSt_A	7086443	18	0	0
EnterDetectSt_A	7086443	18	0	0
EnterStableSt_A	7086443	18	0	0
PulseIsPulse_A	7086443	18	0	0
StayInStableSt	7086443	62123	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7086443	5271	0	0
gen_low_level_sva.LowLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	5	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	36	0	0
T1	916	4	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	2	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	2	0	0
T45	0	2	0	0
T64	0	2	0	0
T157	0	2	0	0
T159	0	2	0	0
T178	0	2	0	0
T179	0	4	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	138431	0	0
T1	916	118	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	35687	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	35	0	0
T45	0	75	0	0
T64	0	26	0	0
T157	0	64	0	0
T159	0	59	0	0
T178	0	58	0	0
T179	0	101986	0	0
T182	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6620527	0	0
T1	916	511	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	62152	0	0
T1	916	138	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	39	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	10	0	0
T45	0	100	0	0
T64	0	11	0	0
T157	0	142	0	0
T159	0	45	0	0
T178	0	212	0	0
T179	0	60922	0	0
T182	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	18	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T45	0	1	0	0
T64	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T178	0	1	0	0
T179	0	2	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6111066	0	0
T1	916	3	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6112923	0	0
T1	916	3	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	18	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T45	0	1	0	0
T64	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T178	0	1	0	0
T179	0	2	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	18	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T45	0	1	0	0
T64	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T178	0	1	0	0
T179	0	2	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	18	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T45	0	1	0	0
T64	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T178	0	1	0	0
T179	0	2	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	18	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T45	0	1	0	0
T64	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T178	0	1	0	0
T179	0	2	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	62123	0	0
T1	916	135	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	37	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	9	0	0
T45	0	98	0	0
T64	0	10	0	0
T157	0	140	0	0
T159	0	43	0	0
T178	0	210	0	0
T179	0	60919	0	0
T182	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	5271	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	4	0	0
T5	3643	4	0	0
T6	896	0	0	0
T7	0	10	0	0
T13	492	7	0	0
T14	1418	12	0	0
T15	1003	4	0	0
T16	443	0	0	0
T17	420	2	0	0
T25	0	4	0	0
T58	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	5	0	0
T1	916	1	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T166	0	1	0	0
T168	0	1	0	0
T179	0	1	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T6,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T6,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T6,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T5,T13,T2
1	1	Covered	T1,T6,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T33,T97
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T10
1	-	Covered	T1,T6,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T10
DetectSt	168	Covered	T1,T6,T10
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T6,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T10
DebounceSt->IdleSt	163	Covered	T33,T186,T187
DetectSt->IdleSt	186	Covered	T33,T97
DetectSt->StableSt	191	Covered	T1,T6,T10
IdleSt->DebounceSt	148	Covered	T1,T6,T10
StableSt->IdleSt	206	Covered	T1,T6,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T10
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T186,T187
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T10
DetectSt	-	-	-	-	1	-	-	Covered	T33,T97
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	76	0	0
CntIncr_A	7086443	114172	0	0
CntNoWrap_A	7086443	6620487	0	0
DetectStDropOut_A	7086443	2	0	0
DetectedOut_A	7086443	65361	0	0
DetectedPulseOut_A	7086443	34	0	0
DisabledIdleSt_A	7086443	6155694	0	0
DisabledNoDetection_A	7086443	6157545	0	0
EnterDebounceSt_A	7086443	40	0	0
EnterDetectSt_A	7086443	36	0	0
EnterStableSt_A	7086443	34	0	0
PulseIsPulse_A	7086443	34	0	0
StayInStableSt	7086443	65312	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	76	0	0
T1	916	4	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	6	0	0
T10	0	4	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	2	0	0
T33	0	4	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T48	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	114172	0	0
T1	916	118	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	159	0	0
T10	0	26	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	35	0	0
T33	0	132	0	0
T42	0	85	0	0
T43	0	74	0	0
T44	0	81	0	0
T48	0	100	0	0
T165	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6620487	0	0
T1	916	511	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	2	0	0
T33	129212	1	0	0
T97	0	1	0	0
T103	672	0	0	0
T123	684	0	0	0
T128	423	0	0	0
T129	402	0	0	0
T130	526	0	0	0
T131	79704	0	0	0
T132	687	0	0	0
T133	31541	0	0	0
T134	651	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	65361	0	0
T1	916	228	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	149	0	0
T10	0	83	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	12	0	0
T42	0	126	0	0
T43	0	41	0	0
T44	0	39	0	0
T48	0	141	0	0
T165	0	71	0	0
T177	0	118	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	34	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	3	0	0
T10	0	2	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6155694	0	0
T1	916	3	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6157545	0	0
T1	916	3	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	40	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	3	0	0
T10	0	2	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	3	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	36	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	3	0	0
T10	0	2	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	34	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	3	0	0
T10	0	2	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	34	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	3	0	0
T10	0	2	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T48	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	65312	0	0
T1	916	226	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	145	0	0
T10	0	80	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	11	0	0
T42	0	125	0	0
T43	0	39	0	0
T44	0	38	0	0
T48	0	140	0	0
T165	0	70	0	0
T177	0	116	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	17	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	2	0	0
T10	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T165	0	1	0	0
T182	0	1	0	0
T200	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T2,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T5,T13,T14
1	1	Covered	T1,T2,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T22
0	1	Covered	T1
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T22
0	1	Covered	T33,T178,T179
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T22
1	-	Covered	T33,T178,T179

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T22
DetectSt	168	Covered	T1,T2,T22
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T2,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T22
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1,T2,T22
IdleSt->DebounceSt	148	Covered	T1,T2,T22
StableSt->IdleSt	206	Covered	T22,T33,T178

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T22
0	1	Covered	T1,T2,T22
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T22
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T22
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T22
DetectSt	-	-	-	-	1	-	-	Covered	T1
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T33,T178
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	56	0	0
CntIncr_A	7086443	164489	0	0
CntNoWrap_A	7086443	6620507	0	0
DetectStDropOut_A	7086443	1	0	0
DetectedOut_A	7086443	163117	0	0
DetectedPulseOut_A	7086443	27	0	0
DisabledIdleSt_A	7086443	5787759	0	0
DisabledNoDetection_A	7086443	5789604	0	0
EnterDebounceSt_A	7086443	28	0	0
EnterDetectSt_A	7086443	28	0	0
EnterStableSt_A	7086443	27	0	0
PulseIsPulse_A	7086443	27	0	0
StayInStableSt	7086443	163075	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7086443	5070	0	0
gen_low_level_sva.LowLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	56	0	0
T1	916	4	0	0
T2	515	2	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	2	0	0
T33	0	6	0	0
T44	0	2	0	0
T134	0	2	0	0
T178	0	2	0	0
T179	0	2	0	0
T182	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	164489	0	0
T1	916	118	0	0
T2	515	30	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	35	0	0
T33	0	132	0	0
T44	0	81	0	0
T134	0	33	0	0
T178	0	58	0	0
T179	0	50993	0	0
T182	0	79	0	0
T201	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6620507	0	0
T1	916	511	0	0
T2	515	112	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1	0	0
T1	916	1	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	163117	0	0
T1	916	39	0	0
T2	515	42	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	11	0	0
T33	0	137	0	0
T44	0	40	0	0
T134	0	38	0	0
T178	0	43	0	0
T179	0	105624	0	0
T182	0	39	0	0
T201	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	27	0	0
T1	916	1	0	0
T2	515	1	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	3	0	0
T44	0	1	0	0
T134	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T182	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	5787759	0	0
T1	916	3	0	0
T2	515	4	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	5789604	0	0
T1	916	3	0	0
T2	515	4	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	28	0	0
T1	916	2	0	0
T2	515	1	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	3	0	0
T44	0	1	0	0
T134	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T182	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	28	0	0
T1	916	2	0	0
T2	515	1	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	3	0	0
T44	0	1	0	0
T134	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T182	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	27	0	0
T1	916	1	0	0
T2	515	1	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	3	0	0
T44	0	1	0	0
T134	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T182	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	27	0	0
T1	916	1	0	0
T2	515	1	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	3	0	0
T44	0	1	0	0
T134	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T182	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	163075	0	0
T1	916	37	0	0
T2	515	40	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	10	0	0
T33	0	133	0	0
T44	0	38	0	0
T134	0	36	0	0
T178	0	42	0	0
T179	0	105623	0	0
T182	0	37	0	0
T201	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	5070	0	0
T1	916	2	0	0
T2	515	1	0	0
T3	280535	0	0	0
T5	3643	6	0	0
T6	896	2	0	0
T7	0	14	0	0
T13	492	7	0	0
T14	1418	13	0	0
T15	1003	0	0	0
T16	443	1	0	0
T17	420	1	0	0
T58	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	10	0	0
T33	129212	2	0	0
T96	0	1	0	0
T103	672	0	0	0
T123	684	0	0	0
T128	423	0	0	0
T129	402	0	0	0
T130	526	0	0	0
T131	79704	0	0	0
T132	687	0	0	0
T133	31541	0	0	0
T134	651	0	0	0
T166	0	2	0	0
T168	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T183	0	1	0	0
T186	0	1	0	0