Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T11,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T11,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T11,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T42
1	0	Covered	T5,T13,T2
1	1	Covered	T1,T11,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T42
0	1	Covered	T1,T165,T41
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T42
1	-	Covered	T1,T165,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T42
DetectSt	168	Covered	T1,T11,T42
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T11,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T42
DebounceSt->IdleSt	163	Covered	T42,T181,T166
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T11,T42
IdleSt->DebounceSt	148	Covered	T1,T11,T42
StableSt->IdleSt	206	Covered	T1,T22,T165

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T11,T42
0	1	Covered	T1,T11,T42
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T42
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T181,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T22,T165
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	91	0	0
CntIncr_A	7086443	301621	0	0
CntNoWrap_A	7086443	6620472	0	0
DetectStDropOut_A	7086443	0	0	0
DetectedOut_A	7086443	252890	0	0
DetectedPulseOut_A	7086443	44	0	0
DisabledIdleSt_A	7086443	5654579	0	0
DisabledNoDetection_A	7086443	5656429	0	0
EnterDebounceSt_A	7086443	47	0	0
EnterDetectSt_A	7086443	44	0	0
EnterStableSt_A	7086443	44	0	0
PulseIsPulse_A	7086443	44	0	0
StayInStableSt	7086443	252826	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	91	0	0
T1	916	4	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	2	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	2	0	0
T33	0	6	0	0
T41	0	2	0	0
T42	0	3	0	0
T47	0	2	0	0
T131	0	2	0	0
T165	0	2	0	0
T177	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	301621	0	0
T1	916	118	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	35687	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	35	0	0
T33	0	132	0	0
T41	0	40	0	0
T42	0	170	0	0
T47	0	21518	0	0
T131	0	28043	0	0
T165	0	81	0	0
T177	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6620472	0	0
T1	916	511	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	252890	0	0
T1	916	51	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	98544	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	12	0	0
T33	0	138	0	0
T41	0	106	0	0
T42	0	126	0	0
T47	0	39	0	0
T131	0	51252	0	0
T165	0	196	0	0
T177	0	83	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	44	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	0	1	0	0
T131	0	1	0	0
T165	0	1	0	0
T177	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	5654579	0	0
T1	916	3	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	5656429	0	0
T1	916	3	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	47	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	3	0	0
T41	0	1	0	0
T42	0	2	0	0
T47	0	1	0	0
T131	0	1	0	0
T165	0	1	0	0
T177	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	44	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	0	1	0	0
T131	0	1	0	0
T165	0	1	0	0
T177	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	44	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	0	1	0	0
T131	0	1	0	0
T165	0	1	0	0
T177	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	44	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T33	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	0	1	0	0
T131	0	1	0	0
T165	0	1	0	0
T177	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	252826	0	0
T1	916	49	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T11	0	98542	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	11	0	0
T33	0	134	0	0
T41	0	105	0	0
T42	0	124	0	0
T47	0	37	0	0
T131	0	51250	0	0
T165	0	195	0	0
T177	0	80	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	22	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T33	0	2	0	0
T41	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	2	0	0
T180	0	1	0	0
T182	0	1	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T6,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T42
1	0	Covered	T1,T5,T13
1	1	Covered	T6,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T42,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T42,T43
0	1	Covered	T6,T42,T177
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T42,T43
1	-	Covered	T6,T42,T177

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T42,T43
DetectSt	168	Covered	T6,T42,T43
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T42,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T42,T43
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T42,T43
IdleSt->DebounceSt	148	Covered	T6,T42,T43
StableSt->IdleSt	206	Covered	T6,T42,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T42,T43
0	1	Covered	T6,T42,T43
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T42,T43
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T42,T43
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T42,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T42,T22
StableSt	-	-	-	-	-	-	0	Covered	T6,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	62	0	0
CntIncr_A	7086443	103963	0	0
CntNoWrap_A	7086443	6620501	0	0
DetectStDropOut_A	7086443	0	0	0
DetectedOut_A	7086443	5356	0	0
DetectedPulseOut_A	7086443	31	0	0
DisabledIdleSt_A	7086443	6197181	0	0
DisabledNoDetection_A	7086443	6199028	0	0
EnterDebounceSt_A	7086443	31	0	0
EnterDetectSt_A	7086443	31	0	0
EnterStableSt_A	7086443	31	0	0
PulseIsPulse_A	7086443	31	0	0
StayInStableSt	7086443	5307	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7086443	5040	0	0
gen_low_level_sva.LowLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	62	0	0
T6	896	4	0	0
T7	16682	0	0	0
T22	0	2	0	0
T25	522	0	0	0
T26	778	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T49	0	2	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T134	0	2	0	0
T157	0	2	0	0
T165	0	2	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	103963	0	0
T6	896	106	0	0
T7	16682	0	0	0
T22	0	35	0	0
T25	522	0	0	0
T26	778	0	0	0
T40	0	536	0	0
T42	0	85	0	0
T43	0	74	0	0
T49	0	52	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T134	0	33	0	0
T157	0	64	0	0
T165	0	81	0	0
T177	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6620501	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	5356	0	0
T6	896	50	0	0
T7	16682	0	0	0
T22	0	11	0	0
T25	522	0	0	0
T26	778	0	0	0
T40	0	53	0	0
T42	0	41	0	0
T43	0	41	0	0
T49	0	38	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T134	0	38	0	0
T157	0	143	0	0
T165	0	44	0	0
T177	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	31	0	0
T6	896	2	0	0
T7	16682	0	0	0
T22	0	1	0	0
T25	522	0	0	0
T26	778	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T49	0	1	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T134	0	1	0	0
T157	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6197181	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6199028	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	31	0	0
T6	896	2	0	0
T7	16682	0	0	0
T22	0	1	0	0
T25	522	0	0	0
T26	778	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T49	0	1	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T134	0	1	0	0
T157	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	31	0	0
T6	896	2	0	0
T7	16682	0	0	0
T22	0	1	0	0
T25	522	0	0	0
T26	778	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T49	0	1	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T134	0	1	0	0
T157	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	31	0	0
T6	896	2	0	0
T7	16682	0	0	0
T22	0	1	0	0
T25	522	0	0	0
T26	778	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T49	0	1	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T134	0	1	0	0
T157	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	31	0	0
T6	896	2	0	0
T7	16682	0	0	0
T22	0	1	0	0
T25	522	0	0	0
T26	778	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T49	0	1	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T134	0	1	0	0
T157	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	5307	0	0
T6	896	47	0	0
T7	16682	0	0	0
T22	0	10	0	0
T25	522	0	0	0
T26	778	0	0	0
T40	0	51	0	0
T42	0	40	0	0
T43	0	39	0	0
T49	0	36	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T134	0	36	0	0
T157	0	142	0	0
T165	0	42	0	0
T177	0	9	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	5040	0	0
T1	916	2	0	0
T2	515	1	0	0
T3	280535	0	0	0
T5	3643	5	0	0
T6	896	2	0	0
T7	0	12	0	0
T13	492	8	0	0
T14	1418	13	0	0
T15	1003	0	0	0
T16	443	1	0	0
T17	420	1	0	0
T25	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	11	0	0
T6	896	1	0	0
T7	16682	0	0	0
T25	522	0	0	0
T26	778	0	0	0
T42	0	1	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T157	0	1	0	0
T166	0	2	0	0
T168	0	1	0	0
T177	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T183	0	1	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T10,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T10,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T10,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T42
1	0	Covered	T5,T13,T2
1	1	Covered	T1,T10,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T42
0	1	Covered	T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T22
0	1	Covered	T1,T10,T42
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T22
1	-	Covered	T1,T10,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T42
DetectSt	168	Covered	T1,T10,T42
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T10,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T42
DebounceSt->IdleSt	163	Covered	T202,T168
DetectSt->IdleSt	186	Covered	T96
DetectSt->StableSt	191	Covered	T1,T10,T42
IdleSt->DebounceSt	148	Covered	T1,T10,T42
StableSt->IdleSt	206	Covered	T1,T10,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T42
0	1	Covered	T1,T10,T42
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T42
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T202,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T42
DetectSt	-	-	-	-	1	-	-	Covered	T96
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T42
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	66	0	0
CntIncr_A	7086443	132031	0	0
CntNoWrap_A	7086443	6620497	0	0
DetectStDropOut_A	7086443	1	0	0
DetectedOut_A	7086443	2291	0	0
DetectedPulseOut_A	7086443	31	0	0
DisabledIdleSt_A	7086443	6201698	0	0
DisabledNoDetection_A	7086443	6203555	0	0
EnterDebounceSt_A	7086443	34	0	0
EnterDetectSt_A	7086443	32	0	0
EnterStableSt_A	7086443	31	0	0
PulseIsPulse_A	7086443	31	0	0
StayInStableSt	7086443	2248	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	66	0	0
T1	916	4	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T10	0	2	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	2	0	0
T131	0	2	0	0
T134	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	132031	0	0
T1	916	118	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T10	0	13	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	35	0	0
T40	0	536	0	0
T41	0	40	0	0
T42	0	85	0	0
T44	0	81	0	0
T131	0	28043	0	0
T134	0	33	0	0
T165	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6620497	0	0
T1	916	511	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1	0	0
T96	778	1	0	0
T111	6993	0	0	0
T180	882	0	0	0
T200	809	0	0	0
T203	422	0	0	0
T204	500	0	0	0
T205	650	0	0	0
T206	502	0	0	0
T207	788	0	0	0
T208	2195	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	2291	0	0
T1	916	26	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T10	0	59	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	10	0	0
T40	0	414	0	0
T41	0	97	0	0
T42	0	1	0	0
T44	0	162	0	0
T131	0	39	0	0
T134	0	75	0	0
T165	0	194	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	31	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T10	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T131	0	1	0	0
T134	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6201698	0	0
T1	916	3	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6203555	0	0
T1	916	3	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	34	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T10	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T131	0	1	0	0
T134	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	32	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T10	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T131	0	1	0	0
T134	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	31	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T10	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T131	0	1	0	0
T134	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	31	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T10	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T131	0	1	0	0
T134	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	2248	0	0
T1	916	24	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T10	0	58	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	9	0	0
T40	0	413	0	0
T41	0	96	0	0
T44	0	160	0	0
T131	0	37	0	0
T134	0	74	0	0
T157	0	139	0	0
T165	0	193	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	17	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	0	0	0
T10	0	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T134	0	1	0	0
T165	0	1	0	0
T179	0	1	0	0
T191	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T6,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T6,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T6,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T42
1	0	Covered	T5,T13,T2
1	1	Covered	T1,T6,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T42
0	1	Covered	T1,T6,T46
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T42
1	-	Covered	T1,T6,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T42
DetectSt	168	Covered	T1,T6,T42
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T6,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T42
DebounceSt->IdleSt	163	Covered	T159
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T6,T42
IdleSt->DebounceSt	148	Covered	T1,T6,T42
StableSt->IdleSt	206	Covered	T1,T6,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T42
0	1	Covered	T1,T6,T42
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T42
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T159
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T22
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	51	0	0
CntIncr_A	7086443	52850	0	0
CntNoWrap_A	7086443	6620512	0	0
DetectStDropOut_A	7086443	0	0	0
DetectedOut_A	7086443	116748	0	0
DetectedPulseOut_A	7086443	25	0	0
DisabledIdleSt_A	7086443	6140126	0	0
DisabledNoDetection_A	7086443	6141975	0	0
EnterDebounceSt_A	7086443	26	0	0
EnterDetectSt_A	7086443	25	0	0
EnterStableSt_A	7086443	25	0	0
PulseIsPulse_A	7086443	25	0	0
StayInStableSt	7086443	116708	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7086443	5132	0	0
gen_low_level_sva.LowLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	51	0	0
T1	916	4	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	2	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T134	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	52850	0	0
T1	916	118	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	53	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	35	0	0
T40	0	536	0	0
T41	0	40	0	0
T42	0	85	0	0
T45	0	75	0	0
T46	0	47	0	0
T134	0	33	0	0
T165	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6620512	0	0
T1	916	511	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	116748	0	0
T1	916	241	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	26	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	11	0	0
T40	0	54	0	0
T41	0	239	0	0
T42	0	40	0	0
T45	0	39	0	0
T46	0	44	0	0
T134	0	37	0	0
T165	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	25	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T134	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6140126	0	0
T1	916	3	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6141975	0	0
T1	916	3	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	26	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T134	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	25	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T134	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	25	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T134	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	25	0	0
T1	916	2	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T134	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	116708	0	0
T1	916	238	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	25	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	10	0	0
T40	0	52	0	0
T41	0	237	0	0
T42	0	38	0	0
T45	0	37	0	0
T46	0	43	0	0
T134	0	35	0	0
T165	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	5132	0	0
T1	916	2	0	0
T2	515	1	0	0
T3	280535	0	0	0
T5	3643	3	0	0
T6	896	1	0	0
T7	0	10	0	0
T13	492	8	0	0
T14	1418	11	0	0
T15	1003	0	0	0
T16	443	1	0	0
T17	420	0	0	0
T25	0	6	0	0
T58	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	8	0	0
T1	916	1	0	0
T2	515	0	0	0
T3	280535	0	0	0
T5	3643	0	0	0
T6	896	1	0	0
T13	492	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T46	0	1	0	0
T167	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T200	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T6,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T22
1	0	Covered	T1,T5,T13
1	1	Covered	T2,T6,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T22
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T22
0	1	Covered	T2,T6,T40
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T22
1	-	Covered	T2,T6,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T22
DetectSt	168	Covered	T2,T6,T22
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T6,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T22
DebounceSt->IdleSt	163	Covered	T182,T200,T168
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T6,T22
IdleSt->DebounceSt	148	Covered	T2,T6,T22
StableSt->IdleSt	206	Covered	T2,T6,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T22
0	1	Covered	T2,T6,T22
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T22
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T182,T200,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T22
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T22
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	64	0	0
CntIncr_A	7086443	192034	0	0
CntNoWrap_A	7086443	6620499	0	0
DetectStDropOut_A	7086443	0	0	0
DetectedOut_A	7086443	17731	0	0
DetectedPulseOut_A	7086443	29	0	0
DisabledIdleSt_A	7086443	6233289	0	0
DisabledNoDetection_A	7086443	6235143	0	0
EnterDebounceSt_A	7086443	35	0	0
EnterDetectSt_A	7086443	29	0	0
EnterStableSt_A	7086443	29	0	0
PulseIsPulse_A	7086443	29	0	0
StayInStableSt	7086443	17685	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	64	0	0
T2	515	2	0	0
T3	280535	0	0	0
T6	896	4	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	2	0	0
T26	778	0	0	0
T40	0	2	0	0
T44	0	2	0	0
T47	0	2	0	0
T49	0	2	0	0
T57	1154	0	0	0
T158	0	2	0	0
T165	0	2	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	192034	0	0
T2	515	30	0	0
T3	280535	0	0	0
T6	896	106	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	35	0	0
T26	778	0	0	0
T40	0	536	0	0
T44	0	81	0	0
T47	0	21518	0	0
T49	0	52	0	0
T57	1154	0	0	0
T158	0	73	0	0
T165	0	81	0	0
T177	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6620499	0	0
T1	916	515	0	0
T2	515	112	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	17731	0	0
T2	515	2	0	0
T3	280535	0	0	0
T6	896	206	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	11	0	0
T26	778	0	0	0
T40	0	414	0	0
T44	0	40	0	0
T47	0	14966	0	0
T49	0	32	0	0
T57	1154	0	0	0
T158	0	151	0	0
T165	0	168	0	0
T177	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	29	0	0
T2	515	1	0	0
T3	280535	0	0	0
T6	896	2	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T26	778	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T57	1154	0	0	0
T158	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6233289	0	0
T1	916	515	0	0
T2	515	4	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6235143	0	0
T1	916	516	0	0
T2	515	4	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	35	0	0
T2	515	1	0	0
T3	280535	0	0	0
T6	896	2	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T26	778	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T57	1154	0	0	0
T158	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	29	0	0
T2	515	1	0	0
T3	280535	0	0	0
T6	896	2	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T26	778	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T57	1154	0	0	0
T158	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	29	0	0
T2	515	1	0	0
T3	280535	0	0	0
T6	896	2	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T26	778	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T57	1154	0	0	0
T158	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	29	0	0
T2	515	1	0	0
T3	280535	0	0	0
T6	896	2	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T26	778	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T57	1154	0	0	0
T158	0	1	0	0
T165	0	1	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	17685	0	0
T2	515	1	0	0
T3	280535	0	0	0
T6	896	203	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	10	0	0
T26	778	0	0	0
T40	0	413	0	0
T44	0	38	0	0
T47	0	14965	0	0
T49	0	31	0	0
T57	1154	0	0	0
T158	0	149	0	0
T165	0	166	0	0
T177	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	10	0	0
T2	515	1	0	0
T3	280535	0	0	0
T6	896	1	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T26	778	0	0	0
T40	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T57	1154	0	0	0
T96	0	1	0	0
T166	0	1	0	0
T182	0	1	0	0
T190	0	1	0	0
T210	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T22,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T22,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T22,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T42,T22
1	0	Covered	T1,T5,T13
1	1	Covered	T2,T22,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T22,T40
0	1	Covered	T190,T210
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T22,T40
0	1	Covered	T41,T179,T168
1	0	Covered	T22,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T22,T40
1	-	Covered	T41,T179,T168

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T22,T40
DetectSt	168	Covered	T2,T22,T40
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T22,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T22,T40
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T190,T210
DetectSt->StableSt	191	Covered	T2,T22,T40
IdleSt->DebounceSt	148	Covered	T2,T22,T40
StableSt->IdleSt	206	Covered	T22,T41,T179

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T22,T40
0	1	Covered	T2,T22,T40
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T22,T40
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T22,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T22,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T22,T40
DetectSt	-	-	-	-	1	-	-	Covered	T190,T210
DetectSt	-	-	-	-	0	1	-	Covered	T2,T22,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T41,T179
StableSt	-	-	-	-	-	-	0	Covered	T2,T22,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	44	0	0
CntIncr_A	7086443	52271	0	0
CntNoWrap_A	7086443	6620519	0	0
DetectStDropOut_A	7086443	2	0	0
DetectedOut_A	7086443	11818	0	0
DetectedPulseOut_A	7086443	20	0	0
DisabledIdleSt_A	7086443	6279649	0	0
DisabledNoDetection_A	7086443	6281502	0	0
EnterDebounceSt_A	7086443	22	0	0
EnterDetectSt_A	7086443	22	0	0
EnterStableSt_A	7086443	20	0	0
PulseIsPulse_A	7086443	20	0	0
StayInStableSt	7086443	11787	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7086443	5522	0	0
gen_low_level_sva.LowLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	7	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	44	0	0
T2	515	2	0	0
T3	280535	0	0	0
T6	896	0	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	2	0	0
T26	778	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T49	0	2	0	0
T57	1154	0	0	0
T96	0	2	0	0
T178	0	2	0	0
T179	0	2	0	0
T190	0	2	0	0
T200	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	52271	0	0
T2	515	30	0	0
T3	280535	0	0	0
T6	896	0	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	35	0	0
T26	778	0	0	0
T40	0	536	0	0
T41	0	80	0	0
T49	0	52	0	0
T57	1154	0	0	0
T96	0	33	0	0
T178	0	58	0	0
T179	0	50993	0	0
T190	0	12	0	0
T200	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6620519	0	0
T1	916	515	0	0
T2	515	112	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	2	0	0
T96	778	0	0	0
T99	930	0	0	0
T180	882	0	0	0
T190	2055	1	0	0
T203	422	0	0	0
T204	500	0	0	0
T210	0	1	0	0
T211	451	0	0	0
T212	2464	0	0	0
T213	422	0	0	0
T214	496	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	11818	0	0
T2	515	42	0	0
T3	280535	0	0	0
T6	896	0	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	11	0	0
T26	778	0	0	0
T40	0	54	0	0
T41	0	35	0	0
T49	0	39	0	0
T57	1154	0	0	0
T64	0	11	0	0
T96	0	224	0	0
T178	0	314	0	0
T179	0	9846	0	0
T200	0	328	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	20	0	0
T2	515	1	0	0
T3	280535	0	0	0
T6	896	0	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T26	778	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T49	0	1	0	0
T57	1154	0	0	0
T64	0	1	0	0
T96	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6279649	0	0
T1	916	515	0	0
T2	515	4	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6281502	0	0
T1	916	516	0	0
T2	515	4	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	22	0	0
T2	515	1	0	0
T3	280535	0	0	0
T6	896	0	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T26	778	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T49	0	1	0	0
T57	1154	0	0	0
T96	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T190	0	1	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	22	0	0
T2	515	1	0	0
T3	280535	0	0	0
T6	896	0	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T26	778	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T49	0	1	0	0
T57	1154	0	0	0
T96	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T190	0	1	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	20	0	0
T2	515	1	0	0
T3	280535	0	0	0
T6	896	0	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T26	778	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T49	0	1	0	0
T57	1154	0	0	0
T64	0	1	0	0
T96	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	20	0	0
T2	515	1	0	0
T3	280535	0	0	0
T6	896	0	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	1	0	0
T26	778	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T49	0	1	0	0
T57	1154	0	0	0
T64	0	1	0	0
T96	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	11787	0	0
T2	515	40	0	0
T3	280535	0	0	0
T6	896	0	0	0
T7	16682	0	0	0
T14	1418	0	0	0
T15	1003	0	0	0
T16	443	0	0	0
T17	420	0	0	0
T22	0	10	0	0
T26	778	0	0	0
T40	0	52	0	0
T41	0	33	0	0
T49	0	37	0	0
T57	1154	0	0	0
T64	0	10	0	0
T96	0	222	0	0
T178	0	312	0	0
T179	0	9845	0	0
T200	0	326	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	5522	0	0
T1	916	2	0	0
T2	515	1	0	0
T3	280535	4	0	0
T5	3643	7	0	0
T6	896	1	0	0
T13	492	7	0	0
T14	1418	13	0	0
T15	1003	4	0	0
T16	443	0	0	0
T17	420	2	0	0
T26	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	7	0	0
T41	826	2	0	0
T73	2857	0	0	0
T102	681	0	0	0
T122	9084	0	0	0
T156	0	2	0	0
T166	0	1	0	0
T168	0	1	0	0
T179	0	1	0	0
T193	409	0	0	0
T194	1522	0	0	0
T195	501	0	0	0
T196	927	0	0	0
T197	1388	0	0	0
T198	1353	0	0	0