Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T9,T12
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T9,T12
1	0	Covered	T27,T9,T12
1	1	Covered	T27,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T9,T12
0	1	Covered	T9,T54,T79
1	0	Covered	T9,T79,T22

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T12,T36
0	1	Covered	T27,T12,T36
1	0	Covered	T92,T93,T215

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T12,T36
1	-	Covered	T27,T12,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T9,T12
DetectSt	168	Covered	T27,T9,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T27,T12,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T9,T12
DebounceSt->IdleSt	163	Covered	T22,T216,T64
DetectSt->IdleSt	186	Covered	T9,T54,T79
DetectSt->StableSt	191	Covered	T27,T12,T36
IdleSt->DebounceSt	148	Covered	T27,T9,T12
StableSt->IdleSt	206	Covered	T27,T12,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T9,T12
0	1	Covered	T27,T9,T12
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T9,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T27,T9,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T22,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T216,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T9,T54,T79
DetectSt	-	-	-	-	0	1	-	Covered	T27,T12,T36
DetectSt	-	-	-	-	0	0	-	Covered	T27,T9,T12
StableSt	-	-	-	-	-	-	1	Covered	T27,T12,T36
StableSt	-	-	-	-	-	-	0	Covered	T27,T12,T36
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	2837	0	0
CntIncr_A	7086443	92614	0	0
CntNoWrap_A	7086443	6617726	0	0
DetectStDropOut_A	7086443	379	0	0
DetectedOut_A	7086443	67604	0	0
DetectedPulseOut_A	7086443	865	0	0
DisabledIdleSt_A	7086443	6197513	0	0
DisabledNoDetection_A	7086443	6199198	0	0
EnterDebounceSt_A	7086443	1424	0	0
EnterDetectSt_A	7086443	1413	0	0
EnterStableSt_A	7086443	865	0	0
PulseIsPulse_A	7086443	865	0	0
StayInStableSt	7086443	66629	0	0
gen_high_event_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	746	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	2837	0	0
T9	23616	28	0	0
T10	2362	0	0	0
T12	0	46	0	0
T24	6849	0	0	0
T27	9153	12	0	0
T32	1131	0	0	0
T34	0	2	0	0
T35	0	28	0	0
T36	0	16	0	0
T38	0	30	0	0
T54	0	54	0	0
T79	0	52	0	0
T80	0	24	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	92614	0	0
T9	23616	743	0	0
T10	2362	0	0	0
T12	0	897	0	0
T24	6849	0	0	0
T27	9153	330	0	0
T32	1131	0	0	0
T34	0	21	0	0
T35	0	546	0	0
T36	0	320	0	0
T38	0	705	0	0
T54	0	1080	0	0
T79	0	1717	0	0
T80	0	540	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6617726	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	379	0	0
T9	23616	9	0	0
T10	2362	0	0	0
T11	170329	0	0	0
T22	0	1	0	0
T51	717	0	0	0
T54	0	27	0	0
T77	526	0	0	0
T79	0	11	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	1	0	0
T104	0	18	0	0
T106	0	30	0	0
T108	0	3	0	0
T109	0	29	0	0
T110	0	24	0	0
T217	406	0	0	0
T218	428	0	0	0
T219	414	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	67604	0	0
T9	23616	0	0	0
T10	2362	0	0	0
T12	0	1846	0	0
T22	0	438	0	0
T24	6849	0	0	0
T27	9153	274	0	0
T32	1131	0	0	0
T34	0	81	0	0
T35	0	204	0	0
T36	0	758	0	0
T38	0	466	0	0
T80	0	813	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	2	0	0
T164	0	313	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	865	0	0
T9	23616	0	0	0
T10	2362	0	0	0
T12	0	23	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	6	0	0
T32	1131	0	0	0
T34	0	1	0	0
T35	0	14	0	0
T36	0	8	0	0
T38	0	15	0	0
T80	0	12	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	2	0	0
T164	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6197513	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6199198	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1424	0	0
T9	23616	14	0	0
T10	2362	0	0	0
T12	0	23	0	0
T24	6849	0	0	0
T27	9153	6	0	0
T32	1131	0	0	0
T34	0	1	0	0
T35	0	14	0	0
T36	0	8	0	0
T38	0	15	0	0
T54	0	27	0	0
T79	0	26	0	0
T80	0	12	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1413	0	0
T9	23616	14	0	0
T10	2362	0	0	0
T12	0	23	0	0
T24	6849	0	0	0
T27	9153	6	0	0
T32	1131	0	0	0
T34	0	1	0	0
T35	0	14	0	0
T36	0	8	0	0
T38	0	15	0	0
T54	0	27	0	0
T79	0	26	0	0
T80	0	12	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	865	0	0
T9	23616	0	0	0
T10	2362	0	0	0
T12	0	23	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	6	0	0
T32	1131	0	0	0
T34	0	1	0	0
T35	0	14	0	0
T36	0	8	0	0
T38	0	15	0	0
T80	0	12	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	2	0	0
T164	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	865	0	0
T9	23616	0	0	0
T10	2362	0	0	0
T12	0	23	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	6	0	0
T32	1131	0	0	0
T34	0	1	0	0
T35	0	14	0	0
T36	0	8	0	0
T38	0	15	0	0
T80	0	12	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	2	0	0
T164	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	66629	0	0
T9	23616	0	0	0
T10	2362	0	0	0
T12	0	1819	0	0
T22	0	433	0	0
T24	6849	0	0	0
T27	9153	268	0	0
T32	1131	0	0	0
T34	0	79	0	0
T35	0	189	0	0
T36	0	749	0	0
T38	0	450	0	0
T80	0	801	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T122	0	1310	0	0
T164	0	304	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	746	0	0
T9	23616	0	0	0
T10	2362	0	0	0
T12	0	18	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	6	0	0
T32	1131	0	0	0
T35	0	13	0	0
T36	0	7	0	0
T38	0	14	0	0
T80	0	12	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T122	0	29	0	0
T133	0	5	0	0
T164	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T7,T8
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T16,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T16,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T7,T8
1	0	Covered	T5,T14,T7
1	1	Covered	T16,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T10
0	1	Covered	T37,T74,T107
1	0	Covered	T22,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T10
0	1	Covered	T7,T8,T10
1	0	Covered	T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T10
1	-	Covered	T7,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T7,T8
DetectSt	168	Covered	T7,T8,T10
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T10
DebounceSt->IdleSt	163	Covered	T16,T24,T53
DetectSt->IdleSt	186	Covered	T37,T22,T74
DetectSt->StableSt	191	Covered	T7,T8,T10
IdleSt->DebounceSt	148	Covered	T16,T7,T8
StableSt->IdleSt	206	Covered	T7,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T7,T8
0	1	Covered	T16,T7,T8
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T10
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T22,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T24,T53
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T37,T22,T74
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T10
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	887	0	0
CntIncr_A	7086443	48723	0	0
CntNoWrap_A	7086443	6619676	0	0
DetectStDropOut_A	7086443	37	0	0
DetectedOut_A	7086443	14012	0	0
DetectedPulseOut_A	7086443	374	0	0
DisabledIdleSt_A	7086443	6271207	0	0
DisabledNoDetection_A	7086443	6272458	0	0
EnterDebounceSt_A	7086443	473	0	0
EnterDetectSt_A	7086443	415	0	0
EnterStableSt_A	7086443	374	0	0
PulseIsPulse_A	7086443	374	0	0
StayInStableSt	7086443	13607	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	340	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	887	0	0
T3	280535	0	0	0
T6	896	0	0	0
T7	16682	8	0	0
T8	0	6	0	0
T10	0	2	0	0
T16	443	1	0	0
T17	420	0	0	0
T24	0	1	0	0
T25	522	0	0	0
T26	778	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T50	622	0	0	0
T53	0	19	0	0
T57	1154	0	0	0
T58	410	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	48723	0	0
T3	280535	0	0	0
T6	896	0	0	0
T7	16682	392	0	0
T8	0	345	0	0
T10	0	25	0	0
T16	443	20	0	0
T17	420	0	0	0
T24	0	20	0	0
T25	522	0	0	0
T26	778	0	0	0
T34	0	25	0	0
T35	0	54	0	0
T37	0	143	0	0
T38	0	40	0	0
T50	622	0	0	0
T53	0	664	0	0
T57	1154	0	0	0
T58	410	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6619676	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	41	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	37	0	0
T35	29792	0	0	0
T37	26322	1	0	0
T38	15668	0	0	0
T54	4622	0	0	0
T70	494	0	0	0
T74	0	5	0	0
T79	9361	0	0	0
T107	0	10	0	0
T111	0	6	0	0
T112	0	6	0	0
T113	0	4	0	0
T115	0	5	0	0
T116	447	0	0	0
T117	422	0	0	0
T118	426	0	0	0
T119	652	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	14012	0	0
T7	16682	33	0	0
T8	0	192	0	0
T10	0	3	0	0
T22	0	109	0	0
T25	522	0	0	0
T34	0	3	0	0
T35	0	76	0	0
T38	0	279	0	0
T50	622	0	0	0
T53	0	50	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T80	0	218	0	0
T120	0	213	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	374	0	0
T7	16682	4	0	0
T8	0	3	0	0
T10	0	1	0	0
T22	0	1	0	0
T25	522	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T50	622	0	0	0
T53	0	9	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T80	0	3	0	0
T120	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6271207	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	3	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6272458	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	3	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	473	0	0
T3	280535	0	0	0
T6	896	0	0	0
T7	16682	4	0	0
T8	0	3	0	0
T10	0	1	0	0
T16	443	1	0	0
T17	420	0	0	0
T24	0	1	0	0
T25	522	0	0	0
T26	778	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T50	622	0	0	0
T53	0	10	0	0
T57	1154	0	0	0
T58	410	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	415	0	0
T7	16682	4	0	0
T8	0	3	0	0
T10	0	1	0	0
T22	0	3	0	0
T25	522	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T50	622	0	0	0
T53	0	9	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T80	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	374	0	0
T7	16682	4	0	0
T8	0	3	0	0
T10	0	1	0	0
T22	0	1	0	0
T25	522	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T50	622	0	0	0
T53	0	9	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T80	0	3	0	0
T120	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	374	0	0
T7	16682	4	0	0
T8	0	3	0	0
T10	0	1	0	0
T22	0	1	0	0
T25	522	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T50	622	0	0	0
T53	0	9	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T80	0	3	0	0
T120	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	13607	0	0
T7	16682	29	0	0
T8	0	188	0	0
T10	0	2	0	0
T22	0	108	0	0
T25	522	0	0	0
T34	0	2	0	0
T35	0	75	0	0
T38	0	277	0	0
T50	622	0	0	0
T53	0	41	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T80	0	215	0	0
T120	0	209	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	340	0	0
T7	16682	4	0	0
T8	0	2	0	0
T10	0	1	0	0
T25	522	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T50	622	0	0	0
T53	0	9	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T80	0	3	0	0
T120	0	4	0	0
T121	0	6	0	0
T122	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T9,T12
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T9,T12
1	0	Covered	T27,T9,T12
1	1	Covered	T27,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T9,T12
0	1	Covered	T54,T79,T80
1	0	Covered	T79,T80,T22

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T9,T12
0	1	Covered	T27,T9,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T9,T12
1	-	Covered	T27,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T9,T12
DetectSt	168	Covered	T27,T9,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T27,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T9,T12
DebounceSt->IdleSt	163	Covered	T22,T216,T64
DetectSt->IdleSt	186	Covered	T54,T79,T80
DetectSt->StableSt	191	Covered	T27,T9,T12
IdleSt->DebounceSt	148	Covered	T27,T9,T12
StableSt->IdleSt	206	Covered	T27,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T9,T12
0	1	Covered	T27,T9,T12
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T9,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T27,T9,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T22,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T216,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T54,T79,T80
DetectSt	-	-	-	-	0	1	-	Covered	T27,T9,T12
DetectSt	-	-	-	-	0	0	-	Covered	T27,T9,T12
StableSt	-	-	-	-	-	-	1	Covered	T27,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T27,T9,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	3108	0	0
CntIncr_A	7086443	103334	0	0
CntNoWrap_A	7086443	6617455	0	0
DetectStDropOut_A	7086443	298	0	0
DetectedOut_A	7086443	85467	0	0
DetectedPulseOut_A	7086443	1083	0	0
DisabledIdleSt_A	7086443	6183069	0	0
DisabledNoDetection_A	7086443	6184736	0	0
EnterDebounceSt_A	7086443	1560	0	0
EnterDetectSt_A	7086443	1548	0	0
EnterStableSt_A	7086443	1083	0	0
PulseIsPulse_A	7086443	1083	0	0
StayInStableSt	7086443	84257	0	0
gen_high_event_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	955	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	3108	0	0
T9	23616	22	0	0
T10	2362	0	0	0
T12	0	46	0	0
T22	0	16	0	0
T24	6849	0	0	0
T27	9153	42	0	0
T32	1131	0	0	0
T35	0	24	0	0
T36	0	6	0	0
T38	0	52	0	0
T54	0	20	0	0
T79	0	52	0	0
T80	0	24	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	103334	0	0
T9	23616	396	0	0
T10	2362	0	0	0
T12	0	1012	0	0
T22	0	634	0	0
T24	6849	0	0	0
T27	9153	1470	0	0
T32	1131	0	0	0
T35	0	384	0	0
T36	0	138	0	0
T38	0	988	0	0
T54	0	397	0	0
T79	0	1708	0	0
T80	0	806	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6617455	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	298	0	0
T22	0	1	0	0
T35	29792	0	0	0
T38	15668	0	0	0
T54	4622	10	0	0
T79	9361	11	0	0
T80	9509	4	0	0
T93	0	14	0	0
T104	0	15	0	0
T106	0	28	0	0
T109	0	15	0	0
T117	422	0	0	0
T118	426	0	0	0
T119	652	0	0	0
T220	0	1	0	0
T221	0	5	0	0
T222	425	0	0	0
T223	681	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	85467	0	0
T9	23616	1992	0	0
T10	2362	0	0	0
T12	0	1731	0	0
T22	0	495	0	0
T24	6849	0	0	0
T27	9153	1413	0	0
T32	1131	0	0	0
T35	0	956	0	0
T36	0	215	0	0
T38	0	4034	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	1571	0	0
T122	0	1270	0	0
T164	0	509	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1083	0	0
T9	23616	11	0	0
T10	2362	0	0	0
T12	0	23	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	21	0	0
T32	1131	0	0	0
T35	0	12	0	0
T36	0	3	0	0
T38	0	26	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	31	0	0
T122	0	24	0	0
T164	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6183069	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6184736	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1560	0	0
T9	23616	11	0	0
T10	2362	0	0	0
T12	0	23	0	0
T22	0	9	0	0
T24	6849	0	0	0
T27	9153	21	0	0
T32	1131	0	0	0
T35	0	12	0	0
T36	0	3	0	0
T38	0	26	0	0
T54	0	10	0	0
T79	0	26	0	0
T80	0	12	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1548	0	0
T9	23616	11	0	0
T10	2362	0	0	0
T12	0	23	0	0
T22	0	7	0	0
T24	6849	0	0	0
T27	9153	21	0	0
T32	1131	0	0	0
T35	0	12	0	0
T36	0	3	0	0
T38	0	26	0	0
T54	0	10	0	0
T79	0	26	0	0
T80	0	12	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1083	0	0
T9	23616	11	0	0
T10	2362	0	0	0
T12	0	23	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	21	0	0
T32	1131	0	0	0
T35	0	12	0	0
T36	0	3	0	0
T38	0	26	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	31	0	0
T122	0	24	0	0
T164	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1083	0	0
T9	23616	11	0	0
T10	2362	0	0	0
T12	0	23	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	21	0	0
T32	1131	0	0	0
T35	0	12	0	0
T36	0	3	0	0
T38	0	26	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	31	0	0
T122	0	24	0	0
T164	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	84257	0	0
T9	23616	1976	0	0
T10	2362	0	0	0
T12	0	1704	0	0
T22	0	490	0	0
T24	6849	0	0	0
T27	9153	1392	0	0
T32	1131	0	0	0
T35	0	942	0	0
T36	0	211	0	0
T38	0	4006	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	1537	0	0
T122	0	1245	0	0
T164	0	500	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	955	0	0
T9	23616	6	0	0
T10	2362	0	0	0
T12	0	18	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	21	0	0
T32	1131	0	0	0
T35	0	10	0	0
T36	0	2	0	0
T38	0	24	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	28	0	0
T122	0	23	0	0
T164	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T8,T27
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T8,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T5,T14,T7
1	1	Covered	T7,T8,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T27
0	1	Covered	T74,T105,T224
1	0	Covered	T22,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T27
0	1	Covered	T7,T8,T27
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T27
1	-	Covered	T7,T8,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T27
DetectSt	168	Covered	T7,T8,T27
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T8,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T27
DebounceSt->IdleSt	163	Covered	T7,T8,T27
DetectSt->IdleSt	186	Covered	T22,T74,T105
DetectSt->StableSt	191	Covered	T7,T8,T27
IdleSt->DebounceSt	148	Covered	T7,T8,T27
StableSt->IdleSt	206	Covered	T7,T8,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T27
0	1	Covered	T7,T8,T27
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T27
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T22,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T8,T27
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T27
DetectSt	-	-	-	-	1	-	-	Covered	T22,T74,T105
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T27
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T27
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T27
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	838	0	0
CntIncr_A	7086443	43502	0	0
CntNoWrap_A	7086443	6619725	0	0
DetectStDropOut_A	7086443	49	0	0
DetectedOut_A	7086443	16177	0	0
DetectedPulseOut_A	7086443	341	0	0
DisabledIdleSt_A	7086443	6250438	0	0
DisabledNoDetection_A	7086443	6251695	0	0
EnterDebounceSt_A	7086443	444	0	0
EnterDetectSt_A	7086443	394	0	0
EnterStableSt_A	7086443	341	0	0
PulseIsPulse_A	7086443	341	0	0
StayInStableSt	7086443	15810	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	314	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	838	0	0
T7	16682	5	0	0
T8	0	13	0	0
T9	0	10	0	0
T12	0	4	0	0
T25	522	0	0	0
T27	0	3	0	0
T35	0	4	0	0
T36	0	2	0	0
T37	0	12	0	0
T39	0	4	0	0
T50	622	0	0	0
T53	0	13	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	43502	0	0
T7	16682	207	0	0
T8	0	688	0	0
T9	0	210	0	0
T12	0	92	0	0
T25	522	0	0	0
T27	0	120	0	0
T35	0	84	0	0
T36	0	55	0	0
T37	0	636	0	0
T39	0	276	0	0
T50	622	0	0	0
T53	0	256	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6619725	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	49	0	0
T49	585	0	0	0
T67	4222	0	0	0
T74	20996	10	0	0
T75	493	0	0	0
T104	5216	0	0	0
T105	0	5	0	0
T145	0	1	0	0
T224	0	4	0	0
T225	0	6	0	0
T226	0	2	0	0
T227	0	4	0	0
T228	0	2	0	0
T229	0	2	0	0
T230	0	13	0	0
T231	883	0	0	0
T232	407	0	0	0
T233	484	0	0	0
T234	17140	0	0	0
T235	856	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	16177	0	0
T7	16682	46	0	0
T8	0	477	0	0
T9	0	366	0	0
T12	0	109	0	0
T25	522	0	0	0
T27	0	66	0	0
T35	0	178	0	0
T36	0	53	0	0
T37	0	220	0	0
T39	0	41	0	0
T50	622	0	0	0
T53	0	222	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	341	0	0
T7	16682	2	0	0
T8	0	6	0	0
T9	0	5	0	0
T12	0	2	0	0
T25	522	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	6	0	0
T39	0	2	0	0
T50	622	0	0	0
T53	0	6	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6250438	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6251695	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	444	0	0
T7	16682	3	0	0
T8	0	7	0	0
T9	0	5	0	0
T12	0	2	0	0
T25	522	0	0	0
T27	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	6	0	0
T39	0	2	0	0
T50	622	0	0	0
T53	0	7	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	394	0	0
T7	16682	2	0	0
T8	0	6	0	0
T9	0	5	0	0
T12	0	2	0	0
T25	522	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	6	0	0
T39	0	2	0	0
T50	622	0	0	0
T53	0	6	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	341	0	0
T7	16682	2	0	0
T8	0	6	0	0
T9	0	5	0	0
T12	0	2	0	0
T25	522	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	6	0	0
T39	0	2	0	0
T50	622	0	0	0
T53	0	6	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	341	0	0
T7	16682	2	0	0
T8	0	6	0	0
T9	0	5	0	0
T12	0	2	0	0
T25	522	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	6	0	0
T39	0	2	0	0
T50	622	0	0	0
T53	0	6	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	15810	0	0
T7	16682	44	0	0
T8	0	471	0	0
T9	0	356	0	0
T12	0	107	0	0
T25	522	0	0	0
T27	0	65	0	0
T35	0	176	0	0
T36	0	52	0	0
T37	0	214	0	0
T39	0	39	0	0
T50	622	0	0	0
T53	0	216	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	314	0	0
T7	16682	2	0	0
T8	0	6	0	0
T12	0	2	0	0
T22	0	1	0	0
T25	522	0	0	0
T27	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	6	0	0
T39	0	2	0	0
T50	622	0	0	0
T53	0	6	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T9,T12
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T9,T12
1	0	Covered	T27,T9,T12
1	1	Covered	T27,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T9,T12
0	1	Covered	T54,T35,T22
1	0	Covered	T35,T79,T22

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T9,T12
0	1	Covered	T27,T9,T12
1	0	Covered	T236

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T9,T12
1	-	Covered	T27,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T9,T12
DetectSt	168	Covered	T27,T9,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T27,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T9,T12
DebounceSt->IdleSt	163	Covered	T22,T216,T64
DetectSt->IdleSt	186	Covered	T54,T35,T79
DetectSt->StableSt	191	Covered	T27,T9,T12
IdleSt->DebounceSt	148	Covered	T27,T9,T12
StableSt->IdleSt	206	Covered	T27,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T9,T12
0	1	Covered	T27,T9,T12
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T9,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T27,T9,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T22,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T216,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T54,T35,T79
DetectSt	-	-	-	-	0	1	-	Covered	T27,T9,T12
DetectSt	-	-	-	-	0	0	-	Covered	T27,T9,T12
StableSt	-	-	-	-	-	-	1	Covered	T27,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T27,T9,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	2915	0	0
CntIncr_A	7086443	95919	0	0
CntNoWrap_A	7086443	6617648	0	0
DetectStDropOut_A	7086443	338	0	0
DetectedOut_A	7086443	64388	0	0
DetectedPulseOut_A	7086443	856	0	0
DisabledIdleSt_A	7086443	6198588	0	0
DisabledNoDetection_A	7086443	6200293	0	0
EnterDebounceSt_A	7086443	1463	0	0
EnterDetectSt_A	7086443	1452	0	0
EnterStableSt_A	7086443	856	0	0
PulseIsPulse_A	7086443	856	0	0
StayInStableSt	7086443	63442	0	0
gen_high_event_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	758	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	2915	0	0
T9	23616	12	0	0
T10	2362	0	0	0
T12	0	24	0	0
T22	0	17	0	0
T24	6849	0	0	0
T27	9153	44	0	0
T32	1131	0	0	0
T35	0	52	0	0
T36	0	12	0	0
T38	0	18	0	0
T54	0	14	0	0
T79	0	28	0	0
T80	0	6	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	95919	0	0
T9	23616	312	0	0
T10	2362	0	0	0
T12	0	324	0	0
T22	0	599	0	0
T24	6849	0	0	0
T27	9153	1496	0	0
T32	1131	0	0	0
T35	0	1092	0	0
T36	0	342	0	0
T38	0	288	0	0
T54	0	274	0	0
T79	0	921	0	0
T80	0	186	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6617648	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	338	0	0
T22	0	1	0	0
T35	29792	4	0	0
T38	15668	0	0	0
T54	4622	7	0	0
T79	9361	0	0	0
T80	9509	0	0	0
T89	0	29	0	0
T104	0	12	0	0
T106	0	6	0	0
T109	0	29	0	0
T117	422	0	0	0
T118	426	0	0	0
T119	652	0	0	0
T222	425	0	0	0
T223	681	0	0	0
T234	0	19	0	0
T237	0	7	0	0
T238	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	64388	0	0
T9	23616	403	0	0
T10	2362	0	0	0
T12	0	758	0	0
T22	0	534	0	0
T24	6849	0	0	0
T27	9153	2246	0	0
T32	1131	0	0	0
T36	0	368	0	0
T38	0	872	0	0
T80	0	21	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	141	0	0
T133	0	1615	0	0
T164	0	787	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	856	0	0
T9	23616	6	0	0
T10	2362	0	0	0
T12	0	12	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	22	0	0
T32	1131	0	0	0
T36	0	6	0	0
T38	0	9	0	0
T80	0	3	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	5	0	0
T133	0	14	0	0
T164	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6198588	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6200293	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1463	0	0
T9	23616	6	0	0
T10	2362	0	0	0
T12	0	12	0	0
T22	0	10	0	0
T24	6849	0	0	0
T27	9153	22	0	0
T32	1131	0	0	0
T35	0	26	0	0
T36	0	6	0	0
T38	0	9	0	0
T54	0	7	0	0
T79	0	14	0	0
T80	0	3	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1452	0	0
T9	23616	6	0	0
T10	2362	0	0	0
T12	0	12	0	0
T22	0	7	0	0
T24	6849	0	0	0
T27	9153	22	0	0
T32	1131	0	0	0
T35	0	26	0	0
T36	0	6	0	0
T38	0	9	0	0
T54	0	7	0	0
T79	0	14	0	0
T80	0	3	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	856	0	0
T9	23616	6	0	0
T10	2362	0	0	0
T12	0	12	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	22	0	0
T32	1131	0	0	0
T36	0	6	0	0
T38	0	9	0	0
T80	0	3	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	5	0	0
T133	0	14	0	0
T164	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	856	0	0
T9	23616	6	0	0
T10	2362	0	0	0
T12	0	12	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	22	0	0
T32	1131	0	0	0
T36	0	6	0	0
T38	0	9	0	0
T80	0	3	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	5	0	0
T133	0	14	0	0
T164	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	63442	0	0
T9	23616	394	0	0
T10	2362	0	0	0
T12	0	743	0	0
T22	0	529	0	0
T24	6849	0	0	0
T27	9153	2224	0	0
T32	1131	0	0	0
T36	0	360	0	0
T38	0	862	0	0
T80	0	18	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	136	0	0
T133	0	1592	0	0
T164	0	764	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	758	0	0
T9	23616	3	0	0
T10	2362	0	0	0
T12	0	9	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	22	0	0
T32	1131	0	0	0
T36	0	4	0	0
T38	0	8	0	0
T80	0	3	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	5	0	0
T133	0	5	0	0
T164	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T8,T27
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T8,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T5,T14,T7
1	1	Covered	T7,T8,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T27
0	1	Covered	T53,T22,T239
1	0	Covered	T22,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T27
0	1	Covered	T7,T8,T27
1	0	Covered	T64,T90

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T27
1	-	Covered	T7,T8,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T27
DetectSt	168	Covered	T7,T8,T27
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T8,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T27
DebounceSt->IdleSt	163	Covered	T7,T8,T39
DetectSt->IdleSt	186	Covered	T53,T22,T239
DetectSt->StableSt	191	Covered	T7,T8,T27
IdleSt->DebounceSt	148	Covered	T7,T8,T27
StableSt->IdleSt	206	Covered	T7,T8,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T27
0	1	Covered	T7,T8,T27
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T27
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T22,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T8,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T27
DetectSt	-	-	-	-	1	-	-	Covered	T53,T22,T239
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T27
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T27
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T27
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	822	0	0
CntIncr_A	7086443	48732	0	0
CntNoWrap_A	7086443	6619741	0	0
DetectStDropOut_A	7086443	43	0	0
DetectedOut_A	7086443	14236	0	0
DetectedPulseOut_A	7086443	338	0	0
DisabledIdleSt_A	7086443	6271474	0	0
DisabledNoDetection_A	7086443	6272768	0	0
EnterDebounceSt_A	7086443	438	0	0
EnterDetectSt_A	7086443	384	0	0
EnterStableSt_A	7086443	338	0	0
PulseIsPulse_A	7086443	338	0	0
StayInStableSt	7086443	13872	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	308	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	822	0	0
T7	16682	13	0	0
T8	0	13	0	0
T9	0	6	0	0
T12	0	4	0	0
T25	522	0	0	0
T27	0	4	0	0
T36	0	4	0	0
T37	0	8	0	0
T38	0	2	0	0
T39	0	2	0	0
T50	622	0	0	0
T53	0	2	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	48732	0	0
T7	16682	617	0	0
T8	0	1048	0	0
T9	0	135	0	0
T12	0	96	0	0
T25	522	0	0	0
T27	0	108	0	0
T36	0	118	0	0
T37	0	480	0	0
T38	0	51	0	0
T39	0	94	0	0
T50	622	0	0	0
T53	0	76	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6619741	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	43	0	0
T22	0	1	0	0
T34	507	0	0	0
T36	11872	0	0	0
T39	20977	0	0	0
T42	810	0	0	0
T53	23550	1	0	0
T69	492	0	0	0
T145	0	2	0	0
T224	0	7	0	0
T239	0	1	0	0
T240	0	4	0	0
T241	0	1	0	0
T242	0	4	0	0
T243	0	8	0	0
T244	0	8	0	0
T245	406	0	0	0
T246	564	0	0	0
T247	425	0	0	0
T248	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	14236	0	0
T7	16682	62	0	0
T8	0	117	0	0
T9	0	215	0	0
T12	0	103	0	0
T22	0	109	0	0
T25	522	0	0	0
T27	0	499	0	0
T36	0	98	0	0
T37	0	89	0	0
T38	0	269	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T164	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	338	0	0
T7	16682	6	0	0
T8	0	6	0	0
T9	0	3	0	0
T12	0	2	0	0
T22	0	1	0	0
T25	522	0	0	0
T27	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	1	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T164	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6271474	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6272768	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	438	0	0
T7	16682	7	0	0
T8	0	7	0	0
T9	0	3	0	0
T12	0	2	0	0
T25	522	0	0	0
T27	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	0	2	0	0
T50	622	0	0	0
T53	0	1	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	384	0	0
T7	16682	6	0	0
T8	0	6	0	0
T9	0	3	0	0
T12	0	2	0	0
T22	0	3	0	0
T25	522	0	0	0
T27	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	1	0	0
T50	622	0	0	0
T53	0	1	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	338	0	0
T7	16682	6	0	0
T8	0	6	0	0
T9	0	3	0	0
T12	0	2	0	0
T22	0	1	0	0
T25	522	0	0	0
T27	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	1	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T164	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	338	0	0
T7	16682	6	0	0
T8	0	6	0	0
T9	0	3	0	0
T12	0	2	0	0
T22	0	1	0	0
T25	522	0	0	0
T27	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	1	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T164	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	13872	0	0
T7	16682	56	0	0
T8	0	111	0	0
T9	0	212	0	0
T12	0	99	0	0
T22	0	108	0	0
T25	522	0	0	0
T27	0	497	0	0
T36	0	96	0	0
T37	0	85	0	0
T38	0	268	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T164	0	49	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	308	0	0
T7	16682	6	0	0
T8	0	6	0	0
T9	0	3	0	0
T25	522	0	0	0
T27	0	1	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	1	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T120	0	10	0	0
T121	0	3	0	0
T249	0	3	0	0