Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T9,T12
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T9,T12
1	0	Covered	T27,T9,T12
1	1	Covered	T27,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T9,T12
0	1	Covered	T9,T54,T22
1	0	Covered	T9,T12,T22

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T36,T35
0	1	Covered	T27,T36,T35
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T36,T35
1	-	Covered	T27,T36,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T9,T12
DetectSt	168	Covered	T27,T9,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T27,T36,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T9,T12
DebounceSt->IdleSt	163	Covered	T22,T216,T64
DetectSt->IdleSt	186	Covered	T9,T12,T54
DetectSt->StableSt	191	Covered	T27,T36,T35
IdleSt->DebounceSt	148	Covered	T27,T9,T12
StableSt->IdleSt	206	Covered	T27,T36,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T9,T12
0	1	Covered	T27,T9,T12
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T9,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T27,T9,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T22,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T216,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T9,T12,T54
DetectSt	-	-	-	-	0	1	-	Covered	T27,T36,T35
DetectSt	-	-	-	-	0	0	-	Covered	T27,T9,T12
StableSt	-	-	-	-	-	-	1	Covered	T27,T36,T35
StableSt	-	-	-	-	-	-	0	Covered	T27,T36,T35
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	3068	0	0
CntIncr_A	7086443	101553	0	0
CntNoWrap_A	7086443	6617495	0	0
DetectStDropOut_A	7086443	335	0	0
DetectedOut_A	7086443	81194	0	0
DetectedPulseOut_A	7086443	1072	0	0
DisabledIdleSt_A	7086443	6188815	0	0
DisabledNoDetection_A	7086443	6190499	0	0
EnterDebounceSt_A	7086443	1540	0	0
EnterDetectSt_A	7086443	1529	0	0
EnterStableSt_A	7086443	1072	0	0
PulseIsPulse_A	7086443	1072	0	0
StayInStableSt	7086443	80011	0	0
gen_high_event_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	960	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	3068	0	0
T9	23616	54	0	0
T10	2362	0	0	0
T12	0	18	0	0
T22	0	16	0	0
T24	6849	0	0	0
T27	9153	10	0	0
T32	1131	0	0	0
T35	0	50	0	0
T36	0	20	0	0
T38	0	18	0	0
T54	0	42	0	0
T79	0	52	0	0
T80	0	26	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	101553	0	0
T9	23616	1438	0	0
T10	2362	0	0	0
T12	0	483	0	0
T22	0	513	0	0
T24	6849	0	0	0
T27	9153	430	0	0
T32	1131	0	0	0
T35	0	825	0	0
T36	0	610	0	0
T38	0	306	0	0
T54	0	837	0	0
T79	0	1352	0	0
T80	0	494	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6617495	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	335	0	0
T9	23616	17	0	0
T10	2362	0	0	0
T11	170329	0	0	0
T22	0	1	0	0
T51	717	0	0	0
T54	0	21	0	0
T77	526	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T89	0	12	0	0
T104	0	23	0	0
T106	0	10	0	0
T109	0	18	0	0
T110	0	10	0	0
T217	406	0	0	0
T218	428	0	0	0
T219	414	0	0	0
T221	0	4	0	0
T234	0	19	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	81194	0	0
T9	23616	0	0	0
T10	2362	0	0	0
T22	0	435	0	0
T24	6849	0	0	0
T27	9153	72	0	0
T32	1131	0	0	0
T35	0	2269	0	0
T36	0	1080	0	0
T38	0	200	0	0
T79	0	1798	0	0
T80	0	1315	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	1342	0	0
T122	0	271	0	0
T164	0	1842	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1072	0	0
T9	23616	0	0	0
T10	2362	0	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	5	0	0
T32	1131	0	0	0
T35	0	25	0	0
T36	0	10	0	0
T38	0	9	0	0
T79	0	26	0	0
T80	0	13	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	26	0	0
T122	0	11	0	0
T164	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6188815	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6190499	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1540	0	0
T9	23616	27	0	0
T10	2362	0	0	0
T12	0	9	0	0
T22	0	9	0	0
T24	6849	0	0	0
T27	9153	5	0	0
T32	1131	0	0	0
T35	0	25	0	0
T36	0	10	0	0
T38	0	9	0	0
T54	0	21	0	0
T79	0	26	0	0
T80	0	13	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1529	0	0
T9	23616	27	0	0
T10	2362	0	0	0
T12	0	9	0	0
T22	0	7	0	0
T24	6849	0	0	0
T27	9153	5	0	0
T32	1131	0	0	0
T35	0	25	0	0
T36	0	10	0	0
T38	0	9	0	0
T54	0	21	0	0
T79	0	26	0	0
T80	0	13	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1072	0	0
T9	23616	0	0	0
T10	2362	0	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	5	0	0
T32	1131	0	0	0
T35	0	25	0	0
T36	0	10	0	0
T38	0	9	0	0
T79	0	26	0	0
T80	0	13	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	26	0	0
T122	0	11	0	0
T164	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	1072	0	0
T9	23616	0	0	0
T10	2362	0	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	5	0	0
T32	1131	0	0	0
T35	0	25	0	0
T36	0	10	0	0
T38	0	9	0	0
T79	0	26	0	0
T80	0	13	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	26	0	0
T122	0	11	0	0
T164	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	80011	0	0
T9	23616	0	0	0
T10	2362	0	0	0
T22	0	430	0	0
T24	6849	0	0	0
T27	9153	67	0	0
T32	1131	0	0	0
T35	0	2235	0	0
T36	0	1069	0	0
T38	0	191	0	0
T79	0	1771	0	0
T80	0	1301	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	1314	0	0
T122	0	260	0	0
T164	0	1820	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	960	0	0
T9	23616	0	0	0
T10	2362	0	0	0
T22	0	5	0	0
T24	6849	0	0	0
T27	9153	5	0	0
T32	1131	0	0	0
T35	0	16	0	0
T36	0	9	0	0
T38	0	9	0	0
T79	0	25	0	0
T80	0	12	0	0
T81	1683	0	0	0
T82	453	0	0	0
T83	423	0	0	0
T84	423	0	0	0
T85	227878	0	0	0
T92	0	24	0	0
T122	0	11	0	0
T164	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T8,T27
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T8,T53

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T5,T14,T7
1	1	Covered	T7,T8,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T53
0	1	Covered	T53,T224,T250
1	0	Covered	T22,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T39
0	1	Covered	T7,T8,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T39
1	-	Covered	T7,T8,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T53
DetectSt	168	Covered	T7,T8,T53
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T8,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T53
DebounceSt->IdleSt	163	Covered	T7,T39,T22
DetectSt->IdleSt	186	Covered	T53,T22,T224
DetectSt->StableSt	191	Covered	T7,T8,T39
IdleSt->DebounceSt	148	Covered	T7,T8,T53
StableSt->IdleSt	206	Covered	T7,T8,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T53
0	1	Covered	T7,T8,T53
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T53
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T53
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T22,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T39,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T53
DetectSt	-	-	-	-	1	-	-	Covered	T53,T22,T224
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T39
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T53
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T39
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7086443	776	0	0
CntIncr_A	7086443	46480	0	0
CntNoWrap_A	7086443	6619787	0	0
DetectStDropOut_A	7086443	85	0	0
DetectedOut_A	7086443	13133	0	0
DetectedPulseOut_A	7086443	277	0	0
DisabledIdleSt_A	7086443	6266187	0	0
DisabledNoDetection_A	7086443	6267474	0	0
EnterDebounceSt_A	7086443	410	0	0
EnterDetectSt_A	7086443	366	0	0
EnterStableSt_A	7086443	277	0	0
PulseIsPulse_A	7086443	277	0	0
StayInStableSt	7086443	12831	0	0
gen_high_level_sva.HighLevelEvent_A	7086443	6622447	0	0
gen_not_sticky_sva.StableStDropOut_A	7086443	250	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	776	0	0
T7	16682	11	0	0
T8	0	6	0	0
T22	0	8	0	0
T25	522	0	0	0
T35	0	16	0	0
T36	0	4	0	0
T37	0	8	0	0
T39	0	11	0	0
T50	622	0	0	0
T53	0	6	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T79	0	2	0	0
T80	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	46480	0	0
T7	16682	386	0	0
T8	0	294	0	0
T22	0	258	0	0
T25	522	0	0	0
T35	0	512	0	0
T36	0	100	0	0
T37	0	552	0	0
T39	0	747	0	0
T50	622	0	0	0
T53	0	228	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T79	0	62	0	0
T80	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6619787	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	85	0	0
T34	507	0	0	0
T36	11872	0	0	0
T39	20977	0	0	0
T42	810	0	0	0
T53	23550	3	0	0
T69	492	0	0	0
T111	0	8	0	0
T145	0	2	0	0
T224	0	3	0	0
T227	0	10	0	0
T240	0	5	0	0
T245	406	0	0	0
T246	564	0	0	0
T247	425	0	0	0
T248	502	0	0	0
T250	0	4	0	0
T251	0	6	0	0
T252	0	4	0	0
T253	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	13133	0	0
T7	16682	186	0	0
T8	0	244	0	0
T22	0	109	0	0
T25	522	0	0	0
T35	0	523	0	0
T36	0	117	0	0
T37	0	19	0	0
T39	0	93	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T79	0	60	0	0
T80	0	60	0	0
T120	0	259	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	277	0	0
T7	16682	5	0	0
T8	0	3	0	0
T22	0	1	0	0
T25	522	0	0	0
T35	0	8	0	0
T36	0	2	0	0
T37	0	4	0	0
T39	0	5	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T120	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6266187	0	0
T1	916	515	0	0
T2	515	114	0	0
T3	280535	280134	0	0
T4	591	190	0	0
T5	3643	1598	0	0
T13	492	91	0	0
T14	1418	216	0	0
T15	1003	602	0	0
T16	443	42	0	0
T17	420	19	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6267474	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	410	0	0
T7	16682	6	0	0
T8	0	3	0	0
T22	0	5	0	0
T25	522	0	0	0
T35	0	8	0	0
T36	0	2	0	0
T37	0	4	0	0
T39	0	6	0	0
T50	622	0	0	0
T53	0	3	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T79	0	1	0	0
T80	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	366	0	0
T7	16682	5	0	0
T8	0	3	0	0
T22	0	3	0	0
T25	522	0	0	0
T35	0	8	0	0
T36	0	2	0	0
T37	0	4	0	0
T39	0	5	0	0
T50	622	0	0	0
T53	0	3	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T79	0	1	0	0
T80	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	277	0	0
T7	16682	5	0	0
T8	0	3	0	0
T22	0	1	0	0
T25	522	0	0	0
T35	0	8	0	0
T36	0	2	0	0
T37	0	4	0	0
T39	0	5	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T120	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	277	0	0
T7	16682	5	0	0
T8	0	3	0	0
T22	0	1	0	0
T25	522	0	0	0
T35	0	8	0	0
T36	0	2	0	0
T37	0	4	0	0
T39	0	5	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T120	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	12831	0	0
T7	16682	181	0	0
T8	0	241	0	0
T22	0	108	0	0
T25	522	0	0	0
T35	0	507	0	0
T36	0	115	0	0
T37	0	15	0	0
T39	0	88	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T79	0	58	0	0
T80	0	58	0	0
T120	0	256	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	6622447	0	0
T1	916	516	0	0
T2	515	115	0	0
T3	280535	280135	0	0
T4	591	191	0	0
T5	3643	1606	0	0
T13	492	92	0	0
T14	1418	218	0	0
T15	1003	603	0	0
T16	443	43	0	0
T17	420	20	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7086443	250	0	0
T7	16682	5	0	0
T8	0	3	0	0
T25	522	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T39	0	5	0	0
T50	622	0	0	0
T57	1154	0	0	0
T58	410	0	0	0
T59	522	0	0	0
T60	403	0	0	0
T61	516	0	0	0
T62	502	0	0	0
T63	407	0	0	0
T74	0	5	0	0
T92	0	2	0	0
T120	0	3	0	0
T121	0	3	0	0
T133	0	3	0	0