Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1261519554	11543	0	0
auto_block_debounce_ctl_rd_A	1261519554	1563	0	0
auto_block_out_ctl_rd_A	1261519554	2231	0	0
com_det_ctl_0_rd_A	1261519554	3475	0	0
com_det_ctl_1_rd_A	1261519554	3491	0	0
com_det_ctl_2_rd_A	1261519554	3816	0	0
com_det_ctl_3_rd_A	1261519554	3744	0	0
com_out_ctl_0_rd_A	1261519554	4023	0	0
com_out_ctl_1_rd_A	1261519554	3929	0	0
com_out_ctl_2_rd_A	1261519554	4038	0	0
com_out_ctl_3_rd_A	1261519554	4095	0	0
com_pre_det_ctl_0_rd_A	1261519554	1372	0	0
com_pre_det_ctl_1_rd_A	1261519554	1458	0	0
com_pre_det_ctl_2_rd_A	1261519554	1240	0	0
com_pre_det_ctl_3_rd_A	1261519554	1241	0	0
com_pre_sel_ctl_0_rd_A	1261519554	4186	0	0
com_pre_sel_ctl_1_rd_A	1261519554	4162	0	0
com_pre_sel_ctl_2_rd_A	1261519554	4161	0	0
com_pre_sel_ctl_3_rd_A	1261519554	4174	0	0
com_sel_ctl_0_rd_A	1261519554	4160	0	0
com_sel_ctl_1_rd_A	1261519554	4167	0	0
com_sel_ctl_2_rd_A	1261519554	4364	0	0
com_sel_ctl_3_rd_A	1261519554	4208	0	0
ec_rst_ctl_rd_A	1261519554	2037	0	0
intr_enable_rd_A	1261519554	1762	0	0
key_intr_ctl_rd_A	1261519554	3022	0	0
key_intr_debounce_ctl_rd_A	1261519554	1265	0	0
key_invert_ctl_rd_A	1261519554	4490	0	0
pin_allowed_ctl_rd_A	1261519554	4133	0	0
pin_out_ctl_rd_A	1261519554	3348	0	0
pin_out_value_rd_A	1261519554	3418	0	0
regwen_rd_A	1261519554	1543	0	0
ulp_ac_debounce_ctl_rd_A	1261519554	1329	0	0
ulp_ctl_rd_A	1261519554	1447	0	0
ulp_lid_debounce_ctl_rd_A	1261519554	1410	0	0
ulp_pwrb_debounce_ctl_rd_A	1261519554	1393	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	11543	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	4	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T24	0	22	0	0
T26	365952	0	0	0
T52	0	6	0	0
T57	0	10	0	0
T78	0	10	0	0
T81	0	15	0	0
T267	0	2	0	0
T285	0	8	0	0
T286	0	11	0	0
T287	0	12	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	1563	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	14	0	0
T6	371155	0	0	0
T7	0	11	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T51	0	10	0	0
T57	0	22	0	0
T103	0	8	0	0
T124	0	17	0	0
T135	0	10	0	0
T267	0	14	0	0
T287	0	45	0	0
T288	0	14	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	2231	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	21	0	0
T6	371155	0	0	0
T7	0	13	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T51	0	12	0	0
T57	0	39	0	0
T103	0	9	0	0
T124	0	7	0	0
T135	0	8	0	0
T267	0	17	0	0
T287	0	37	0	0
T288	0	2	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	3475	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	12	0	0
T6	371155	0	0	0
T7	0	81	0	0
T12	0	58	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	28	0	0
T57	0	47	0	0
T92	0	58	0	0
T120	0	53	0	0
T122	0	37	0	0
T267	0	15	0	0
T287	0	27	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	3491	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	16	0	0
T6	371155	0	0	0
T7	0	62	0	0
T12	0	59	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	23	0	0
T57	0	39	0	0
T92	0	52	0	0
T120	0	54	0	0
T122	0	45	0	0
T267	0	12	0	0
T287	0	31	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	3816	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	14	0	0
T6	371155	0	0	0
T7	0	70	0	0
T12	0	50	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	23	0	0
T57	0	35	0	0
T92	0	46	0	0
T120	0	29	0	0
T122	0	61	0	0
T267	0	21	0	0
T287	0	34	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	3744	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	19	0	0
T6	371155	0	0	0
T7	0	55	0	0
T12	0	39	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	21	0	0
T57	0	48	0	0
T92	0	64	0	0
T120	0	45	0	0
T122	0	38	0	0
T267	0	12	0	0
T287	0	37	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4023	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	19	0	0
T6	371155	0	0	0
T7	0	82	0	0
T12	0	53	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	19	0	0
T57	0	32	0	0
T92	0	66	0	0
T120	0	48	0	0
T122	0	53	0	0
T267	0	18	0	0
T287	0	42	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	3929	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	7	0	0
T6	371155	0	0	0
T7	0	72	0	0
T12	0	51	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	26	0	0
T57	0	46	0	0
T92	0	52	0	0
T120	0	38	0	0
T122	0	21	0	0
T267	0	18	0	0
T287	0	28	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4038	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	17	0	0
T6	371155	0	0	0
T7	0	67	0	0
T12	0	69	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	38	0	0
T57	0	33	0	0
T92	0	45	0	0
T120	0	40	0	0
T122	0	45	0	0
T267	0	21	0	0
T287	0	37	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4095	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	19	0	0
T6	371155	0	0	0
T7	0	64	0	0
T12	0	61	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	15	0	0
T57	0	42	0	0
T92	0	63	0	0
T120	0	40	0	0
T122	0	29	0	0
T267	0	8	0	0
T287	0	55	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	1372	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	16	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	45	0	0
T124	0	7	0	0
T168	0	11	0	0
T267	0	19	0	0
T287	0	40	0	0
T289	0	37	0	0
T290	0	44	0	0
T291	0	23	0	0
T292	0	18	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	1458	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	21	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	26	0	0
T124	0	9	0	0
T168	0	20	0	0
T267	0	15	0	0
T287	0	24	0	0
T289	0	15	0	0
T290	0	46	0	0
T291	0	15	0	0
T292	0	16	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	1240	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	17	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	45	0	0
T124	0	7	0	0
T168	0	27	0	0
T267	0	20	0	0
T287	0	44	0	0
T289	0	25	0	0
T290	0	45	0	0
T291	0	19	0	0
T292	0	13	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	1241	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	13	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	64	0	0
T124	0	13	0	0
T168	0	11	0	0
T267	0	19	0	0
T287	0	34	0	0
T289	0	18	0	0
T290	0	41	0	0
T291	0	12	0	0
T292	0	5	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4186	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	6	0	0
T6	371155	0	0	0
T7	0	54	0	0
T12	0	59	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	27	0	0
T57	0	42	0	0
T92	0	48	0	0
T120	0	20	0	0
T122	0	60	0	0
T267	0	16	0	0
T287	0	36	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4162	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	29	0	0
T6	371155	0	0	0
T7	0	70	0	0
T12	0	31	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	27	0	0
T57	0	46	0	0
T92	0	48	0	0
T120	0	45	0	0
T122	0	41	0	0
T267	0	17	0	0
T287	0	22	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4161	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	22	0	0
T6	371155	0	0	0
T7	0	43	0	0
T12	0	52	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	49	0	0
T57	0	31	0	0
T92	0	59	0	0
T120	0	57	0	0
T122	0	49	0	0
T267	0	22	0	0
T287	0	32	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4174	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	10	0	0
T6	371155	0	0	0
T7	0	72	0	0
T12	0	43	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	25	0	0
T57	0	31	0	0
T92	0	64	0	0
T120	0	42	0	0
T122	0	34	0	0
T267	0	24	0	0
T287	0	28	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4160	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	15	0	0
T6	371155	0	0	0
T7	0	86	0	0
T12	0	47	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	20	0	0
T57	0	29	0	0
T92	0	61	0	0
T120	0	26	0	0
T122	0	47	0	0
T267	0	19	0	0
T287	0	30	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4167	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	24	0	0
T6	371155	0	0	0
T7	0	71	0	0
T12	0	42	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	18	0	0
T57	0	51	0	0
T92	0	69	0	0
T120	0	58	0	0
T122	0	52	0	0
T267	0	21	0	0
T287	0	41	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4364	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	13	0	0
T6	371155	0	0	0
T7	0	64	0	0
T12	0	49	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	22	0	0
T57	0	38	0	0
T92	0	49	0	0
T120	0	43	0	0
T122	0	56	0	0
T267	0	12	0	0
T287	0	36	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4208	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	14	0	0
T6	371155	0	0	0
T7	0	61	0	0
T12	0	50	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	17	0	0
T57	0	41	0	0
T92	0	102	0	0
T120	0	31	0	0
T122	0	17	0	0
T267	0	11	0	0
T287	0	23	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	2037	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	28	0	0
T6	371155	0	0	0
T7	0	21	0	0
T12	0	16	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T27	0	3	0	0
T54	0	3	0	0
T57	0	62	0	0
T120	0	10	0	0
T246	0	4	0	0
T267	0	20	0	0
T293	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	1762	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	27	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	44	0	0
T124	0	20	0	0
T159	0	11	0	0
T168	0	21	0	0
T267	0	9	0	0
T287	0	20	0	0
T289	0	18	0	0
T290	0	47	0	0
T294	0	41	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	3022	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	11	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T22	0	73	0	0
T26	365952	0	0	0
T45	0	2	0	0
T49	0	8	0	0
T57	0	33	0	0
T124	0	10	0	0
T191	0	2	0	0
T267	0	17	0	0
T287	0	28	0	0
T289	0	16	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	1265	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	12	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	32	0	0
T124	0	5	0	0
T168	0	6	0	0
T267	0	13	0	0
T287	0	30	0	0
T289	0	19	0	0
T290	0	43	0	0
T291	0	8	0	0
T292	0	17	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4490	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	10	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	51	0	0
T68	0	187	0	0
T71	0	39	0	0
T72	0	63	0	0
T75	0	73	0	0
T267	0	15	0	0
T287	0	30	0	0
T295	0	31	0	0
T296	0	41	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	4133	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	67	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	54	0	0
T124	0	3	0	0
T195	0	64	0	0
T267	0	17	0	0
T283	0	48	0	0
T287	0	32	0	0
T289	0	20	0	0
T297	0	66	0	0
T298	0	32	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	3348	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	56	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	38	0	0
T124	0	9	0	0
T195	0	69	0	0
T267	0	20	0	0
T283	0	47	0	0
T287	0	25	0	0
T289	0	20	0	0
T297	0	75	0	0
T298	0	37	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	3418	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	87	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	54	0	0
T124	0	5	0	0
T195	0	30	0	0
T267	0	25	0	0
T283	0	40	0	0
T287	0	27	0	0
T289	0	26	0	0
T297	0	82	0	0
T298	0	56	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	1543	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	9	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	47	0	0
T124	0	19	0	0
T168	0	15	0	0
T267	0	35	0	0
T287	0	32	0	0
T289	0	17	0	0
T290	0	35	0	0
T291	0	18	0	0
T292	0	16	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	1329	0	0
T2	108073	0	0	0
T3	216543	0	0	0
T5	127501	17	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	20	0	0
T66	0	3	0	0
T88	0	2	0	0
T124	0	9	0	0
T267	0	24	0	0
T287	0	32	0	0
T294	0	3	0	0
T298	0	2	0	0
T299	0	8	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	1447	0	0
T2	108073	0	0	0
T3	216543	1	0	0
T5	127501	14	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	24	0	0
T66	0	4	0	0
T68	0	3	0	0
T87	0	3	0	0
T88	0	5	0	0
T124	0	11	0	0
T267	0	20	0	0
T287	0	22	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	1410	0	0
T2	108073	0	0	0
T3	216543	2	0	0
T5	127501	18	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	32	0	0
T66	0	3	0	0
T88	0	3	0	0
T267	0	22	0	0
T287	0	19	0	0
T289	0	26	0	0
T294	0	3	0	0
T299	0	3	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1261519554	1393	0	0
T2	108073	0	0	0
T3	216543	4	0	0
T5	127501	20	0	0
T6	371155	0	0	0
T13	238774	0	0	0
T14	340415	0	0	0
T15	104251	0	0	0
T16	17755	0	0	0
T17	52562	0	0	0
T26	365952	0	0	0
T57	0	30	0	0
T66	0	4	0	0
T68	0	3	0	0
T87	0	3	0	0
T88	0	2	0	0
T124	0	14	0	0
T267	0	17	0	0
T287	0	21	0	0