SYSRST_CTRL Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 0 50 0.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 0 50 0.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 0 5 0.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 0 5 0.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 5.770s 4.018ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 6.400s 2.066ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.365m 66.194ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 13.930s 3.169ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.320s 2.041ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 6.400s 2.066ms 20 20 100.00
sysrst_ctrl_csr_aliasing 13.930s 3.169ms 5 5 100.00
V1 TOTAL 55 165 33.33
V2 combo_detect sysrst_ctrl_combo_detect 0 50 0.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 0 100 0.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 0 50 0.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 0 50 0.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 0 50 0.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 0 50 0.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 0 50 0.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 0 50 0.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 0 50 0.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 0 2 0.00
V2 stress_all sysrst_ctrl_stress_all 0 50 0.00
V2 alert_test sysrst_ctrl_alert_test 0 50 0.00
V2 intr_test sysrst_ctrl_intr_test 6.190s 2.011ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 7.910s 2.126ms 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 7.910s 2.126ms 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 5.770s 4.018ms 5 5 100.00
sysrst_ctrl_csr_rw 6.400s 2.066ms 20 20 100.00
sysrst_ctrl_csr_aliasing 13.930s 3.169ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 48.440s 10.697ms 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 5.770s 4.018ms 5 5 100.00
sysrst_ctrl_csr_rw 6.400s 2.066ms 20 20 100.00
sysrst_ctrl_csr_aliasing 13.930s 3.169ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 48.440s 10.697ms 20 20 100.00
V2 TOTAL 90 692 13.01
V2S tl_intg_err sysrst_ctrl_sec_cm 0 5 0.00
sysrst_ctrl_tl_intg_err 1.916m 42.482ms 20 20 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.916m 42.482ms 20 20 100.00
V2S TOTAL 20 25 80.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 165 932 17.70

Testplan Progress

Items Total Written Passing Progress
V1 9 9 5 55.56
V2 15 15 3 20.00
V2S 2 2 1 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
62.93 72.20 71.99 87.44 0.00 75.49 99.67 33.72

Failure Buckets

Past Results