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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.78 99.35 96.73 100.00 96.79 98.82 99.52 86.28


Total test records in report: 918
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T791 /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3773194007 Aug 15 05:22:15 PM PDT 24 Aug 15 05:22:22 PM PDT 24 2452865634 ps
T792 /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3022365107 Aug 15 05:23:54 PM PDT 24 Aug 15 05:27:50 PM PDT 24 92211572547 ps
T793 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3662253302 Aug 15 05:22:04 PM PDT 24 Aug 15 05:22:06 PM PDT 24 3572087922 ps
T18 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2648906747 Aug 15 04:35:02 PM PDT 24 Aug 15 04:35:31 PM PDT 24 7738929178 ps
T794 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1880639802 Aug 15 04:35:01 PM PDT 24 Aug 15 04:35:03 PM PDT 24 2034344614 ps
T30 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2263389844 Aug 15 04:35:06 PM PDT 24 Aug 15 04:35:13 PM PDT 24 2048591868 ps
T31 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3749905422 Aug 15 04:34:45 PM PDT 24 Aug 15 04:34:50 PM PDT 24 2820732873 ps
T795 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.102749149 Aug 15 04:35:12 PM PDT 24 Aug 15 04:35:18 PM PDT 24 2011524691 ps
T32 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.925665222 Aug 15 04:34:54 PM PDT 24 Aug 15 04:35:54 PM PDT 24 22202532876 ps
T796 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.3026344232 Aug 15 04:35:15 PM PDT 24 Aug 15 04:35:17 PM PDT 24 2028312896 ps
T33 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3192489095 Aug 15 04:35:03 PM PDT 24 Aug 15 04:35:07 PM PDT 24 2075802166 ps
T292 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3189004027 Aug 15 04:34:47 PM PDT 24 Aug 15 04:36:31 PM PDT 24 42452107538 ps
T797 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1260307722 Aug 15 04:35:03 PM PDT 24 Aug 15 04:35:04 PM PDT 24 2126548323 ps
T293 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.981985820 Aug 15 04:35:09 PM PDT 24 Aug 15 04:36:57 PM PDT 24 42437178601 ps
T301 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1508168030 Aug 15 04:35:06 PM PDT 24 Aug 15 04:35:13 PM PDT 24 2028292274 ps
T19 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3368879694 Aug 15 04:35:05 PM PDT 24 Aug 15 04:35:17 PM PDT 24 10177341115 ps
T300 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.804500103 Aug 15 04:34:58 PM PDT 24 Aug 15 04:36:49 PM PDT 24 42364188063 ps
T353 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2081095982 Aug 15 04:34:47 PM PDT 24 Aug 15 04:34:49 PM PDT 24 2084617853 ps
T366 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2313532942 Aug 15 04:35:06 PM PDT 24 Aug 15 04:35:11 PM PDT 24 2029123251 ps
T798 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.678691627 Aug 15 04:35:12 PM PDT 24 Aug 15 04:35:15 PM PDT 24 2039336707 ps
T799 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3891353045 Aug 15 04:35:16 PM PDT 24 Aug 15 04:35:22 PM PDT 24 2015053361 ps
T354 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3244787269 Aug 15 04:35:00 PM PDT 24 Aug 15 04:35:06 PM PDT 24 2034588386 ps
T355 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3288459165 Aug 15 04:34:49 PM PDT 24 Aug 15 04:34:55 PM PDT 24 2050672293 ps
T299 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.4185804067 Aug 15 04:35:01 PM PDT 24 Aug 15 04:35:03 PM PDT 24 2723189468 ps
T20 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1387555680 Aug 15 04:35:17 PM PDT 24 Aug 15 04:35:24 PM PDT 24 8829118583 ps
T302 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.4167277625 Aug 15 04:34:42 PM PDT 24 Aug 15 04:34:45 PM PDT 24 2314730905 ps
T308 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1599012787 Aug 15 04:34:39 PM PDT 24 Aug 15 04:35:21 PM PDT 24 22197879637 ps
T303 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2518949777 Aug 15 04:34:46 PM PDT 24 Aug 15 04:34:50 PM PDT 24 2375273524 ps
T306 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1106396211 Aug 15 04:35:01 PM PDT 24 Aug 15 04:35:05 PM PDT 24 2117951706 ps
T800 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1372707788 Aug 15 04:35:15 PM PDT 24 Aug 15 04:35:17 PM PDT 24 2173942137 ps
T367 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.382652934 Aug 15 04:34:43 PM PDT 24 Aug 15 04:35:03 PM PDT 24 4552234869 ps
T368 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3151924924 Aug 15 04:35:01 PM PDT 24 Aug 15 04:35:26 PM PDT 24 9488706130 ps
T356 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3786679221 Aug 15 04:35:01 PM PDT 24 Aug 15 04:35:05 PM PDT 24 2041163090 ps
T407 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1367860724 Aug 15 04:35:07 PM PDT 24 Aug 15 04:37:02 PM PDT 24 42355184212 ps
T801 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2294048354 Aug 15 04:35:17 PM PDT 24 Aug 15 04:35:19 PM PDT 24 2024578059 ps
T408 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.456002857 Aug 15 04:35:03 PM PDT 24 Aug 15 04:35:07 PM PDT 24 2066946759 ps
T802 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1493767855 Aug 15 04:35:13 PM PDT 24 Aug 15 04:35:44 PM PDT 24 42951578888 ps
T385 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1207637513 Aug 15 04:35:04 PM PDT 24 Aug 15 04:35:57 PM PDT 24 42415416348 ps
T803 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2092400447 Aug 15 04:35:13 PM PDT 24 Aug 15 04:35:15 PM PDT 24 2042207858 ps
T804 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2656213260 Aug 15 04:35:01 PM PDT 24 Aug 15 04:35:06 PM PDT 24 2012373045 ps
T805 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.4193838908 Aug 15 04:35:03 PM PDT 24 Aug 15 04:35:08 PM PDT 24 2014717825 ps
T806 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3383280829 Aug 15 04:35:04 PM PDT 24 Aug 15 04:35:06 PM PDT 24 2086842293 ps
T807 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2256623548 Aug 15 04:35:02 PM PDT 24 Aug 15 04:35:16 PM PDT 24 22525458013 ps
T808 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1617647893 Aug 15 04:35:10 PM PDT 24 Aug 15 04:35:12 PM PDT 24 2052592880 ps
T809 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.4067938372 Aug 15 04:34:54 PM PDT 24 Aug 15 04:34:55 PM PDT 24 2191714752 ps
T810 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3635238854 Aug 15 04:35:13 PM PDT 24 Aug 15 04:35:15 PM PDT 24 2034135976 ps
T811 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1509052035 Aug 15 04:35:05 PM PDT 24 Aug 15 04:35:35 PM PDT 24 22217973616 ps
T812 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2311226332 Aug 15 04:34:56 PM PDT 24 Aug 15 04:35:51 PM PDT 24 22234708893 ps
T813 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2062277460 Aug 15 04:35:06 PM PDT 24 Aug 15 04:35:08 PM PDT 24 2043079294 ps
T369 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3058853810 Aug 15 04:35:17 PM PDT 24 Aug 15 04:35:19 PM PDT 24 2114522259 ps
T814 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.437595188 Aug 15 04:35:10 PM PDT 24 Aug 15 04:35:12 PM PDT 24 2060602258 ps
T815 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.1772646336 Aug 15 04:35:06 PM PDT 24 Aug 15 04:35:10 PM PDT 24 2025040337 ps
T816 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1135026180 Aug 15 04:34:49 PM PDT 24 Aug 15 04:34:52 PM PDT 24 2023911859 ps
T817 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3948046602 Aug 15 04:34:48 PM PDT 24 Aug 15 04:35:03 PM PDT 24 22541508584 ps
T818 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.554436250 Aug 15 04:35:15 PM PDT 24 Aug 15 04:35:19 PM PDT 24 2022755835 ps
T819 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1136409814 Aug 15 04:35:08 PM PDT 24 Aug 15 04:35:18 PM PDT 24 5287559935 ps
T820 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2871048877 Aug 15 04:35:14 PM PDT 24 Aug 15 04:35:16 PM PDT 24 2038052903 ps
T821 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2879920662 Aug 15 04:35:35 PM PDT 24 Aug 15 04:35:41 PM PDT 24 2012460834 ps
T313 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.684068380 Aug 15 04:35:18 PM PDT 24 Aug 15 04:35:24 PM PDT 24 2062409864 ps
T822 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1791321951 Aug 15 04:34:58 PM PDT 24 Aug 15 04:35:02 PM PDT 24 2021336840 ps
T823 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2232270997 Aug 15 04:35:13 PM PDT 24 Aug 15 04:35:15 PM PDT 24 2069637059 ps
T824 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3000403632 Aug 15 04:35:08 PM PDT 24 Aug 15 04:35:09 PM PDT 24 2155562371 ps
T825 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3159223714 Aug 15 04:35:14 PM PDT 24 Aug 15 04:35:20 PM PDT 24 2061683784 ps
T311 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.211029102 Aug 15 04:34:45 PM PDT 24 Aug 15 04:36:33 PM PDT 24 42366681123 ps
T826 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1978377810 Aug 15 04:34:54 PM PDT 24 Aug 15 04:34:59 PM PDT 24 2726929913 ps
T827 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1848330638 Aug 15 04:35:13 PM PDT 24 Aug 15 04:35:17 PM PDT 24 2086916173 ps
T828 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2883012531 Aug 15 04:34:59 PM PDT 24 Aug 15 04:35:02 PM PDT 24 2044128344 ps
T829 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3084611527 Aug 15 04:35:01 PM PDT 24 Aug 15 04:35:08 PM PDT 24 5114897666 ps
T830 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.862888524 Aug 15 04:34:59 PM PDT 24 Aug 15 04:35:01 PM PDT 24 2073999832 ps
T386 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.561489090 Aug 15 04:35:02 PM PDT 24 Aug 15 04:35:19 PM PDT 24 42698429457 ps
T831 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1533177132 Aug 15 04:35:09 PM PDT 24 Aug 15 04:35:12 PM PDT 24 2029556971 ps
T832 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.855942626 Aug 15 04:35:11 PM PDT 24 Aug 15 04:35:18 PM PDT 24 2015154375 ps
T312 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3859150939 Aug 15 04:35:08 PM PDT 24 Aug 15 04:35:11 PM PDT 24 2113758663 ps
T833 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2788709221 Aug 15 04:34:38 PM PDT 24 Aug 15 04:34:44 PM PDT 24 2014100639 ps
T834 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.135253801 Aug 15 04:34:47 PM PDT 24 Aug 15 04:34:52 PM PDT 24 6078835580 ps
T835 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.4053533464 Aug 15 04:35:13 PM PDT 24 Aug 15 04:35:39 PM PDT 24 6518855952 ps
T836 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1658421913 Aug 15 04:35:09 PM PDT 24 Aug 15 04:35:18 PM PDT 24 4704811407 ps
T837 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1693886540 Aug 15 04:35:14 PM PDT 24 Aug 15 04:35:19 PM PDT 24 2175555271 ps
T838 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.601514998 Aug 15 04:35:06 PM PDT 24 Aug 15 04:35:12 PM PDT 24 2265595559 ps
T357 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.706470260 Aug 15 04:34:47 PM PDT 24 Aug 15 04:36:14 PM PDT 24 33186298612 ps
T839 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1471619113 Aug 15 04:34:58 PM PDT 24 Aug 15 04:35:03 PM PDT 24 4437248451 ps
T840 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.212061734 Aug 15 04:35:04 PM PDT 24 Aug 15 04:35:10 PM PDT 24 2083122778 ps
T841 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1996127758 Aug 15 04:34:46 PM PDT 24 Aug 15 04:34:49 PM PDT 24 4088029811 ps
T842 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.78218175 Aug 15 04:35:00 PM PDT 24 Aug 15 04:35:04 PM PDT 24 4765344586 ps
T843 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2544520709 Aug 15 04:35:07 PM PDT 24 Aug 15 04:35:10 PM PDT 24 2177510319 ps
T358 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3308479808 Aug 15 04:34:47 PM PDT 24 Aug 15 04:36:29 PM PDT 24 74314346978 ps
T844 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.785476001 Aug 15 04:34:59 PM PDT 24 Aug 15 04:35:05 PM PDT 24 2011323054 ps
T845 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.58177866 Aug 15 04:35:01 PM PDT 24 Aug 15 04:35:03 PM PDT 24 2042510719 ps
T846 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3030127858 Aug 15 04:35:09 PM PDT 24 Aug 15 04:35:14 PM PDT 24 2069277639 ps
T847 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3382114472 Aug 15 04:34:47 PM PDT 24 Aug 15 04:35:43 PM PDT 24 22261355909 ps
T848 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.1569720996 Aug 15 04:35:12 PM PDT 24 Aug 15 04:35:18 PM PDT 24 2012305480 ps
T359 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3929834784 Aug 15 04:34:51 PM PDT 24 Aug 15 04:36:01 PM PDT 24 33001254519 ps
T849 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1612356993 Aug 15 04:35:14 PM PDT 24 Aug 15 04:35:17 PM PDT 24 3013149907 ps
T850 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2291687340 Aug 15 04:35:03 PM PDT 24 Aug 15 04:35:09 PM PDT 24 5307482145 ps
T851 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2284753307 Aug 15 04:34:47 PM PDT 24 Aug 15 04:34:51 PM PDT 24 2077401202 ps
T852 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2443143694 Aug 15 04:35:06 PM PDT 24 Aug 15 04:35:09 PM PDT 24 2026330849 ps
T853 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1530290052 Aug 15 04:34:45 PM PDT 24 Aug 15 04:34:51 PM PDT 24 2055243755 ps
T854 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1592137617 Aug 15 04:35:16 PM PDT 24 Aug 15 04:35:19 PM PDT 24 2025367238 ps
T360 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2696427581 Aug 15 04:34:58 PM PDT 24 Aug 15 04:35:02 PM PDT 24 2026318099 ps
T855 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.994691024 Aug 15 04:35:01 PM PDT 24 Aug 15 04:35:05 PM PDT 24 2088522735 ps
T856 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1019655252 Aug 15 04:35:04 PM PDT 24 Aug 15 04:35:06 PM PDT 24 2082737797 ps
T857 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3862385882 Aug 15 04:35:05 PM PDT 24 Aug 15 04:35:07 PM PDT 24 2047892903 ps
T858 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2241430772 Aug 15 04:34:50 PM PDT 24 Aug 15 04:35:00 PM PDT 24 10199535582 ps
T859 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2898007302 Aug 15 04:35:27 PM PDT 24 Aug 15 04:35:29 PM PDT 24 2028224523 ps
T860 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2998118811 Aug 15 04:35:00 PM PDT 24 Aug 15 04:35:59 PM PDT 24 42612834777 ps
T861 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1819225177 Aug 15 04:35:13 PM PDT 24 Aug 15 04:35:15 PM PDT 24 2080619923 ps
T862 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.328693273 Aug 15 04:35:15 PM PDT 24 Aug 15 04:35:44 PM PDT 24 22322635689 ps
T863 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3154505937 Aug 15 04:35:05 PM PDT 24 Aug 15 04:35:07 PM PDT 24 2037164500 ps
T864 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2361643977 Aug 15 04:34:49 PM PDT 24 Aug 15 04:34:52 PM PDT 24 4342878647 ps
T865 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1608419522 Aug 15 04:34:49 PM PDT 24 Aug 15 04:34:54 PM PDT 24 2716046091 ps
T866 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2580304626 Aug 15 04:34:46 PM PDT 24 Aug 15 04:34:53 PM PDT 24 2057328633 ps
T867 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.20389425 Aug 15 04:34:54 PM PDT 24 Aug 15 04:34:56 PM PDT 24 2080718334 ps
T868 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1329173702 Aug 15 04:35:03 PM PDT 24 Aug 15 04:35:07 PM PDT 24 2456496203 ps
T869 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.1926112293 Aug 15 04:34:48 PM PDT 24 Aug 15 04:34:51 PM PDT 24 4916592380 ps
T870 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.243434227 Aug 15 04:34:49 PM PDT 24 Aug 15 04:34:52 PM PDT 24 2154470889 ps
T871 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2940564362 Aug 15 04:34:51 PM PDT 24 Aug 15 04:34:59 PM PDT 24 2112794850 ps
T872 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3617786408 Aug 15 04:34:41 PM PDT 24 Aug 15 04:34:47 PM PDT 24 2242152579 ps
T873 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3760006824 Aug 15 04:34:48 PM PDT 24 Aug 15 04:34:52 PM PDT 24 2173976357 ps
T874 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3536142038 Aug 15 04:35:01 PM PDT 24 Aug 15 04:35:05 PM PDT 24 2490034985 ps
T875 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3034919415 Aug 15 04:35:16 PM PDT 24 Aug 15 04:35:22 PM PDT 24 2015624084 ps
T876 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.477905087 Aug 15 04:35:09 PM PDT 24 Aug 15 04:35:38 PM PDT 24 10305480632 ps
T877 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4111578924 Aug 15 04:34:51 PM PDT 24 Aug 15 04:34:58 PM PDT 24 2056746413 ps
T361 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3572284295 Aug 15 04:35:06 PM PDT 24 Aug 15 04:35:08 PM PDT 24 2089814055 ps
T878 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.900992901 Aug 15 04:35:08 PM PDT 24 Aug 15 04:35:11 PM PDT 24 2159546427 ps
T362 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.593947047 Aug 15 04:35:01 PM PDT 24 Aug 15 04:35:07 PM PDT 24 2057320090 ps
T879 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.790888920 Aug 15 04:34:58 PM PDT 24 Aug 15 04:35:01 PM PDT 24 2081508960 ps
T880 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.924607840 Aug 15 04:35:04 PM PDT 24 Aug 15 04:35:10 PM PDT 24 2017747636 ps
T881 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2060907140 Aug 15 04:35:02 PM PDT 24 Aug 15 04:35:04 PM PDT 24 2025513623 ps
T882 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3659305868 Aug 15 04:35:20 PM PDT 24 Aug 15 04:35:22 PM PDT 24 2029094537 ps
T883 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.204696075 Aug 15 04:34:49 PM PDT 24 Aug 15 04:35:08 PM PDT 24 10544048041 ps
T884 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.447113542 Aug 15 04:34:50 PM PDT 24 Aug 15 04:34:53 PM PDT 24 2089505598 ps
T885 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.4027110756 Aug 15 04:35:14 PM PDT 24 Aug 15 04:35:21 PM PDT 24 2014827155 ps
T886 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1516766667 Aug 15 04:35:14 PM PDT 24 Aug 15 04:36:09 PM PDT 24 22218053756 ps
T887 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1035791026 Aug 15 04:34:46 PM PDT 24 Aug 15 04:34:49 PM PDT 24 2023146991 ps
T888 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.995498892 Aug 15 04:35:06 PM PDT 24 Aug 15 04:35:10 PM PDT 24 2052606662 ps
T889 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.2842303604 Aug 15 04:35:03 PM PDT 24 Aug 15 04:35:10 PM PDT 24 2060938430 ps
T363 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3132165260 Aug 15 04:34:49 PM PDT 24 Aug 15 04:34:58 PM PDT 24 2395689604 ps
T890 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1901000566 Aug 15 04:35:15 PM PDT 24 Aug 15 04:35:18 PM PDT 24 2019079074 ps
T891 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2062260487 Aug 15 04:35:17 PM PDT 24 Aug 15 04:35:19 PM PDT 24 2049535005 ps
T892 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3919497439 Aug 15 04:34:46 PM PDT 24 Aug 15 04:34:50 PM PDT 24 2816878713 ps
T893 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3617915099 Aug 15 04:34:46 PM PDT 24 Aug 15 04:36:21 PM PDT 24 38836230471 ps
T894 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.19875256 Aug 15 04:35:07 PM PDT 24 Aug 15 04:35:13 PM PDT 24 2013984441 ps
T895 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1515033804 Aug 15 04:35:08 PM PDT 24 Aug 15 04:35:35 PM PDT 24 7203739502 ps
T896 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3953769337 Aug 15 04:34:40 PM PDT 24 Aug 15 04:34:51 PM PDT 24 4015041855 ps
T364 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2815092896 Aug 15 04:34:47 PM PDT 24 Aug 15 04:34:49 PM PDT 24 6126465061 ps
T897 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1981687306 Aug 15 04:35:03 PM PDT 24 Aug 15 04:35:05 PM PDT 24 2042411940 ps
T898 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1351152372 Aug 15 04:35:04 PM PDT 24 Aug 15 04:35:11 PM PDT 24 5335085148 ps
T899 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2291777177 Aug 15 04:35:00 PM PDT 24 Aug 15 04:35:02 PM PDT 24 2039784959 ps
T900 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3057620461 Aug 15 04:35:11 PM PDT 24 Aug 15 04:35:17 PM PDT 24 2017853911 ps
T901 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1694181836 Aug 15 04:34:57 PM PDT 24 Aug 15 04:35:00 PM PDT 24 2119437328 ps
T902 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1205957823 Aug 15 04:34:58 PM PDT 24 Aug 15 04:35:02 PM PDT 24 2397669055 ps
T903 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2507315621 Aug 15 04:34:50 PM PDT 24 Aug 15 04:34:56 PM PDT 24 7898587064 ps
T904 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.220992055 Aug 15 04:35:10 PM PDT 24 Aug 15 04:35:13 PM PDT 24 2023978117 ps
T905 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1009804593 Aug 15 04:35:14 PM PDT 24 Aug 15 04:35:18 PM PDT 24 2080985343 ps
T365 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3568290126 Aug 15 04:34:49 PM PDT 24 Aug 15 04:38:30 PM PDT 24 40477963389 ps
T906 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3406245624 Aug 15 04:35:09 PM PDT 24 Aug 15 04:35:40 PM PDT 24 42795629822 ps
T907 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.470538821 Aug 15 04:34:46 PM PDT 24 Aug 15 04:35:02 PM PDT 24 6029338124 ps
T908 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.64222993 Aug 15 04:35:05 PM PDT 24 Aug 15 04:35:11 PM PDT 24 2029552773 ps
T909 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.517628557 Aug 15 04:34:49 PM PDT 24 Aug 15 04:34:56 PM PDT 24 2011377585 ps
T910 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3429348382 Aug 15 04:35:00 PM PDT 24 Aug 15 04:35:06 PM PDT 24 2063811510 ps
T911 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.4037114783 Aug 15 04:35:16 PM PDT 24 Aug 15 04:35:32 PM PDT 24 43420866655 ps
T912 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3416263271 Aug 15 04:35:05 PM PDT 24 Aug 15 04:35:11 PM PDT 24 2010799458 ps
T913 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1026753852 Aug 15 04:34:47 PM PDT 24 Aug 15 04:34:53 PM PDT 24 2038052444 ps
T914 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.4288331342 Aug 15 04:34:59 PM PDT 24 Aug 15 04:35:01 PM PDT 24 2031604679 ps
T915 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2556574790 Aug 15 04:35:21 PM PDT 24 Aug 15 04:35:23 PM PDT 24 2040129023 ps
T916 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3329709097 Aug 15 04:35:12 PM PDT 24 Aug 15 04:35:15 PM PDT 24 2016987004 ps
T917 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.900322048 Aug 15 04:34:53 PM PDT 24 Aug 15 04:35:00 PM PDT 24 2101124983 ps
T918 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2659743518 Aug 15 04:34:59 PM PDT 24 Aug 15 04:35:02 PM PDT 24 2119800466 ps

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2090045915
Short name T3
Test name
Test status
Simulation time 129686312940 ps
CPU time 326.97 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:28:42 PM PDT 24
Peak memory 201348 kb
Host smart-47098752-8813-444d-955c-71afa9eb8030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090045915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.2090045915
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.2182210035
Short name T39
Test name
Test status
Simulation time 111325276796 ps
CPU time 50.79 seconds
Started Aug 15 05:23:28 PM PDT 24
Finished Aug 15 05:24:19 PM PDT 24
Peak memory 201188 kb
Host smart-05f4883b-8dc1-45df-b679-f62c2ef6254f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182210035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.2182210035
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3073764098
Short name T47
Test name
Test status
Simulation time 10236511946 ps
CPU time 7.44 seconds
Started Aug 15 05:23:11 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201232 kb
Host smart-132748d3-56c4-485c-b0e2-66052851b624
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073764098 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.3073764098
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2990137566
Short name T26
Test name
Test status
Simulation time 2553546565 ps
CPU time 1.79 seconds
Started Aug 15 05:23:33 PM PDT 24
Finished Aug 15 05:23:35 PM PDT 24
Peak memory 201112 kb
Host smart-3d3397c7-63d1-4493-825d-8b1593925c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990137566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.2990137566
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.266745474
Short name T22
Test name
Test status
Simulation time 7354756435 ps
CPU time 8.05 seconds
Started Aug 15 05:23:06 PM PDT 24
Finished Aug 15 05:23:15 PM PDT 24
Peak memory 201088 kb
Host smart-9a23b963-9e02-45eb-b421-6ac9c1baf896
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266745474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_ultra_low_pwr.266745474
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.4180009400
Short name T105
Test name
Test status
Simulation time 35841082833 ps
CPU time 10.69 seconds
Started Aug 15 05:22:02 PM PDT 24
Finished Aug 15 05:22:13 PM PDT 24
Peak memory 201112 kb
Host smart-fc93db2e-1196-4c2a-b658-abe59ff84a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180009400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.4180009400
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.3364821118
Short name T56
Test name
Test status
Simulation time 13247923385 ps
CPU time 37.25 seconds
Started Aug 15 05:23:25 PM PDT 24
Finished Aug 15 05:24:03 PM PDT 24
Peak memory 201132 kb
Host smart-25d68cd2-2b4e-4d05-996a-fcff10660b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364821118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.3364821118
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1835618917
Short name T80
Test name
Test status
Simulation time 2501422804 ps
CPU time 2.03 seconds
Started Aug 15 05:22:51 PM PDT 24
Finished Aug 15 05:22:53 PM PDT 24
Peak memory 201100 kb
Host smart-8b0fcfd3-b967-493f-92ae-5975e11fa924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835618917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.1835618917
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3189004027
Short name T292
Test name
Test status
Simulation time 42452107538 ps
CPU time 103.78 seconds
Started Aug 15 04:34:47 PM PDT 24
Finished Aug 15 04:36:31 PM PDT 24
Peak memory 201252 kb
Host smart-723766f1-da13-407c-989e-12b2ccf234ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189004027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.3189004027
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.3318731259
Short name T1
Test name
Test status
Simulation time 100901112091 ps
CPU time 272.28 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:27:51 PM PDT 24
Peak memory 201300 kb
Host smart-b8c66276-fb6f-467b-ac8e-552081165d59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318731259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_combo_detect.3318731259
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.2068572790
Short name T45
Test name
Test status
Simulation time 4093519151 ps
CPU time 2.68 seconds
Started Aug 15 05:23:49 PM PDT 24
Finished Aug 15 05:23:52 PM PDT 24
Peak memory 201072 kb
Host smart-1435de8e-fd0d-4f73-8e3d-f445cccdfe51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068572790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.2068572790
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.30501294
Short name T73
Test name
Test status
Simulation time 540762529501 ps
CPU time 18.43 seconds
Started Aug 15 05:22:32 PM PDT 24
Finished Aug 15 05:22:51 PM PDT 24
Peak memory 209604 kb
Host smart-2bf8223a-15b8-4f6b-90f4-2ab20d141999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30501294 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.30501294
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1194863962
Short name T35
Test name
Test status
Simulation time 93154055147 ps
CPU time 242.47 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:27:54 PM PDT 24
Peak memory 201400 kb
Host smart-593fe35c-220c-4251-83f5-1e6f203a5384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194863962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.1194863962
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.436810287
Short name T189
Test name
Test status
Simulation time 11694314677 ps
CPU time 4.3 seconds
Started Aug 15 05:23:25 PM PDT 24
Finished Aug 15 05:23:29 PM PDT 24
Peak memory 209408 kb
Host smart-5dfd6bf2-6692-44f8-a323-e70e9783b232
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436810287 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.436810287
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.1880281168
Short name T36
Test name
Test status
Simulation time 118463856827 ps
CPU time 286.98 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:28:03 PM PDT 24
Peak memory 201156 kb
Host smart-61060a5e-dfae-4926-a1e1-62fcdafa73c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880281168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.1880281168
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2273537004
Short name T97
Test name
Test status
Simulation time 163375624657 ps
CPU time 203.99 seconds
Started Aug 15 05:23:49 PM PDT 24
Finished Aug 15 05:27:13 PM PDT 24
Peak memory 201380 kb
Host smart-c2eea232-f5b0-485d-9321-1bdc9ac6b0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273537004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.2273537004
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.4115590305
Short name T63
Test name
Test status
Simulation time 42011740160 ps
CPU time 93.48 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:23:41 PM PDT 24
Peak memory 220852 kb
Host smart-76397f4c-b0bb-4aeb-919a-d5a0aa8c8dd1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115590305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.4115590305
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1877524971
Short name T100
Test name
Test status
Simulation time 8159757498 ps
CPU time 2.3 seconds
Started Aug 15 05:23:57 PM PDT 24
Finished Aug 15 05:23:59 PM PDT 24
Peak memory 201080 kb
Host smart-a4c837cb-9e8e-47cd-b9ce-850e123d20ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877524971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.1877524971
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.3946097933
Short name T108
Test name
Test status
Simulation time 3373084923 ps
CPU time 7.27 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:15 PM PDT 24
Peak memory 201040 kb
Host smart-f6525720-f9bb-4354-a108-5d886cfa0d20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946097933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.3946097933
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.3167749943
Short name T193
Test name
Test status
Simulation time 6775494485 ps
CPU time 10.7 seconds
Started Aug 15 05:22:42 PM PDT 24
Finished Aug 15 05:22:52 PM PDT 24
Peak memory 209636 kb
Host smart-6f0aa9ab-cc8c-4d36-8306-274662452d69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167749943 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.3167749943
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.2665643889
Short name T4
Test name
Test status
Simulation time 3732128442 ps
CPU time 4.16 seconds
Started Aug 15 05:22:34 PM PDT 24
Finished Aug 15 05:22:38 PM PDT 24
Peak memory 201332 kb
Host smart-e5c267af-95e4-44d2-86b5-b82a5a15cbb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665643889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.2665643889
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.3883740495
Short name T289
Test name
Test status
Simulation time 260137950318 ps
CPU time 668.74 seconds
Started Aug 15 05:22:39 PM PDT 24
Finished Aug 15 05:33:48 PM PDT 24
Peak memory 201084 kb
Host smart-205c9762-7afc-4be4-9282-9510843297f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883740495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.3883740495
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.2336418988
Short name T215
Test name
Test status
Simulation time 64614937199 ps
CPU time 164.59 seconds
Started Aug 15 05:23:39 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 201184 kb
Host smart-ab74384f-c03a-4c19-872f-55e904d50c4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336418988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.2336418988
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.2176970857
Short name T305
Test name
Test status
Simulation time 251769848326 ps
CPU time 173.91 seconds
Started Aug 15 05:22:25 PM PDT 24
Finished Aug 15 05:25:19 PM PDT 24
Peak memory 201276 kb
Host smart-df764940-64b6-433c-bec6-f9dcffeb5934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176970857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.2176970857
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.4167277625
Short name T302
Test name
Test status
Simulation time 2314730905 ps
CPU time 3.2 seconds
Started Aug 15 04:34:42 PM PDT 24
Finished Aug 15 04:34:45 PM PDT 24
Peak memory 201244 kb
Host smart-be0bd747-3894-4ecc-9a36-00c979c02ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167277625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.4167277625
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.2732816603
Short name T228
Test name
Test status
Simulation time 3689441920 ps
CPU time 2.26 seconds
Started Aug 15 05:22:44 PM PDT 24
Finished Aug 15 05:22:46 PM PDT 24
Peak memory 201140 kb
Host smart-c76e7091-fb30-406f-b0a5-426ef6113da1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732816603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.2732816603
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1236892368
Short name T251
Test name
Test status
Simulation time 92471281786 ps
CPU time 135.47 seconds
Started Aug 15 05:23:58 PM PDT 24
Finished Aug 15 05:26:14 PM PDT 24
Peak memory 201272 kb
Host smart-8d137482-1bb3-4a01-9d8a-0b0d63de2d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236892368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.1236892368
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.739867282
Short name T258
Test name
Test status
Simulation time 13104717874 ps
CPU time 17.92 seconds
Started Aug 15 05:22:08 PM PDT 24
Finished Aug 15 05:22:26 PM PDT 24
Peak memory 201076 kb
Host smart-812f8065-2a67-46f4-b70b-fc427d614f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739867282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_str
ess_all.739867282
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.758150399
Short name T181
Test name
Test status
Simulation time 5794973825 ps
CPU time 3.69 seconds
Started Aug 15 05:22:50 PM PDT 24
Finished Aug 15 05:22:54 PM PDT 24
Peak memory 201088 kb
Host smart-41edf37f-511e-47f5-8b7c-abe6e4c9e29b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758150399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctr
l_edge_detect.758150399
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2081095982
Short name T353
Test name
Test status
Simulation time 2084617853 ps
CPU time 2.01 seconds
Started Aug 15 04:34:47 PM PDT 24
Finished Aug 15 04:34:49 PM PDT 24
Peak memory 200880 kb
Host smart-7fde5006-347b-4f67-bed0-031bf3120a06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081095982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.2081095982
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.2125503186
Short name T166
Test name
Test status
Simulation time 4438055126 ps
CPU time 11.53 seconds
Started Aug 15 05:22:45 PM PDT 24
Finished Aug 15 05:22:56 PM PDT 24
Peak memory 201076 kb
Host smart-f0d33ac4-98d1-49a1-8fc8-aaa427ce15dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125503186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.2125503186
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2143655413
Short name T134
Test name
Test status
Simulation time 3504735722 ps
CPU time 5.16 seconds
Started Aug 15 05:22:42 PM PDT 24
Finished Aug 15 05:22:47 PM PDT 24
Peak memory 201080 kb
Host smart-ac9c2d1f-a702-4600-84d1-981a276e8431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143655413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.2
143655413
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.1425057402
Short name T230
Test name
Test status
Simulation time 345076451821 ps
CPU time 143.8 seconds
Started Aug 15 05:23:03 PM PDT 24
Finished Aug 15 05:25:27 PM PDT 24
Peak memory 201180 kb
Host smart-fc012faf-2bc5-46f8-85a1-ea2ed054281e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425057402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.1425057402
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2071714740
Short name T247
Test name
Test status
Simulation time 13744370131 ps
CPU time 10.08 seconds
Started Aug 15 05:22:13 PM PDT 24
Finished Aug 15 05:22:24 PM PDT 24
Peak memory 209664 kb
Host smart-f0d89e6a-088d-4d99-b486-1a514bd4ee18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071714740 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.2071714740
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3141597741
Short name T241
Test name
Test status
Simulation time 195033947290 ps
CPU time 63.76 seconds
Started Aug 15 05:23:10 PM PDT 24
Finished Aug 15 05:24:14 PM PDT 24
Peak memory 201348 kb
Host smart-5ac3d18d-b29f-402b-97da-a325d33a0a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141597741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.3141597741
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.43638100
Short name T29
Test name
Test status
Simulation time 3494252832 ps
CPU time 5.4 seconds
Started Aug 15 05:23:52 PM PDT 24
Finished Aug 15 05:23:58 PM PDT 24
Peak memory 201156 kb
Host smart-4586a094-e4f9-4912-8d69-4f5fee1d4413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43638100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.43638100
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.2382399707
Short name T16
Test name
Test status
Simulation time 52341347145 ps
CPU time 136.45 seconds
Started Aug 15 05:22:38 PM PDT 24
Finished Aug 15 05:24:55 PM PDT 24
Peak memory 201348 kb
Host smart-a48caa9c-e6bb-454a-bac4-7b991eb0ec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382399707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.2382399707
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.2409344370
Short name T88
Test name
Test status
Simulation time 2511017481 ps
CPU time 6.92 seconds
Started Aug 15 05:22:14 PM PDT 24
Finished Aug 15 05:22:21 PM PDT 24
Peak memory 201060 kb
Host smart-54ad12cb-2ca3-4b3a-a647-65d4d3dc7fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409344370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.2409344370
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2185770727
Short name T67
Test name
Test status
Simulation time 41242863855 ps
CPU time 54.83 seconds
Started Aug 15 05:21:59 PM PDT 24
Finished Aug 15 05:22:54 PM PDT 24
Peak memory 201072 kb
Host smart-a8f5836d-cbf7-46d7-b7eb-14d884d0c7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185770727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.2185770727
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.4021742258
Short name T384
Test name
Test status
Simulation time 99136522793 ps
CPU time 112.12 seconds
Started Aug 15 05:22:02 PM PDT 24
Finished Aug 15 05:23:55 PM PDT 24
Peak memory 201348 kb
Host smart-b23aed56-bc56-437e-a571-6a06fccfdd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021742258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.4021742258
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.3983426169
Short name T15
Test name
Test status
Simulation time 2025279615 ps
CPU time 3.33 seconds
Started Aug 15 05:22:23 PM PDT 24
Finished Aug 15 05:22:26 PM PDT 24
Peak memory 201104 kb
Host smart-67d0fb3d-356b-4f47-9d1a-296eadc1e49a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983426169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.3983426169
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.382652934
Short name T367
Test name
Test status
Simulation time 4552234869 ps
CPU time 20.09 seconds
Started Aug 15 04:34:43 PM PDT 24
Finished Aug 15 04:35:03 PM PDT 24
Peak memory 200984 kb
Host smart-685f0d6e-16c7-4f7e-8f01-4e2fb94c3e1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382652934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
sysrst_ctrl_same_csr_outstanding.382652934
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1599012787
Short name T308
Test name
Test status
Simulation time 22197879637 ps
CPU time 41.51 seconds
Started Aug 15 04:34:39 PM PDT 24
Finished Aug 15 04:35:21 PM PDT 24
Peak memory 201072 kb
Host smart-62b5451e-6731-4891-92d7-ba73c5981531
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599012787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.1599012787
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.1481392258
Short name T130
Test name
Test status
Simulation time 79456023585 ps
CPU time 213.82 seconds
Started Aug 15 05:23:13 PM PDT 24
Finished Aug 15 05:26:47 PM PDT 24
Peak memory 201200 kb
Host smart-7cac620e-8ff3-4f54-8f0c-a4bc4117a313
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481392258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.1481392258
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1020770487
Short name T379
Test name
Test status
Simulation time 29027125561 ps
CPU time 80.35 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:25:14 PM PDT 24
Peak memory 201284 kb
Host smart-a6e07f59-f09c-4e49-b673-19a8cae53b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020770487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.1020770487
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1848061371
Short name T96
Test name
Test status
Simulation time 49280653042 ps
CPU time 16.98 seconds
Started Aug 15 05:23:52 PM PDT 24
Finished Aug 15 05:24:09 PM PDT 24
Peak memory 201360 kb
Host smart-fcd50b54-604a-42be-8760-a1ce03b0da56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848061371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.1848061371
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.3948336035
Short name T413
Test name
Test status
Simulation time 116428501306 ps
CPU time 39.34 seconds
Started Aug 15 05:23:11 PM PDT 24
Finished Aug 15 05:23:50 PM PDT 24
Peak memory 201184 kb
Host smart-647490b8-7536-4b7c-bbcf-b6535f0126cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948336035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.3948336035
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.750034031
Short name T389
Test name
Test status
Simulation time 113232837962 ps
CPU time 291.53 seconds
Started Aug 15 05:23:53 PM PDT 24
Finished Aug 15 05:28:45 PM PDT 24
Peak memory 201272 kb
Host smart-d5abfd53-dad0-4f36-88b6-cedd938328ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750034031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_wi
th_pre_cond.750034031
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1469594669
Short name T276
Test name
Test status
Simulation time 55254382340 ps
CPU time 35.11 seconds
Started Aug 15 05:22:26 PM PDT 24
Finished Aug 15 05:23:01 PM PDT 24
Peak memory 201296 kb
Host smart-939a67b2-9c69-476a-bcad-182aaab89296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469594669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.1469594669
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2678548110
Short name T157
Test name
Test status
Simulation time 121492436414 ps
CPU time 16.54 seconds
Started Aug 15 05:22:50 PM PDT 24
Finished Aug 15 05:23:07 PM PDT 24
Peak memory 201132 kb
Host smart-fb19e26c-22a7-48ad-a8da-8ce940fb82aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678548110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.2678548110
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2352232227
Short name T7
Test name
Test status
Simulation time 89954364835 ps
CPU time 236.9 seconds
Started Aug 15 05:23:00 PM PDT 24
Finished Aug 15 05:26:58 PM PDT 24
Peak memory 201256 kb
Host smart-eea79ee6-22f0-42d6-9261-48207c5b5097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352232227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.2352232227
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.1536553206
Short name T12
Test name
Test status
Simulation time 107281193183 ps
CPU time 142.14 seconds
Started Aug 15 05:22:08 PM PDT 24
Finished Aug 15 05:24:30 PM PDT 24
Peak memory 201240 kb
Host smart-6d1d2b52-7d2e-4f8a-9411-1a8501f6c26b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536553206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.1536553206
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.342359310
Short name T419
Test name
Test status
Simulation time 610779118480 ps
CPU time 82.67 seconds
Started Aug 15 05:22:02 PM PDT 24
Finished Aug 15 05:23:25 PM PDT 24
Peak memory 201176 kb
Host smart-0d0e4477-0d5f-4282-91e5-17c0901c17d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342359310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_ultra_low_pwr.342359310
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.997647730
Short name T70
Test name
Test status
Simulation time 4543829889 ps
CPU time 3.34 seconds
Started Aug 15 05:22:10 PM PDT 24
Finished Aug 15 05:22:14 PM PDT 24
Peak memory 201124 kb
Host smart-af8eed7d-3fc9-452d-9eff-db87201cb4fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997647730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_ec_pwr_on_rst.997647730
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3860894625
Short name T409
Test name
Test status
Simulation time 109180909920 ps
CPU time 279.75 seconds
Started Aug 15 05:23:57 PM PDT 24
Finished Aug 15 05:28:37 PM PDT 24
Peak memory 201308 kb
Host smart-ebce8916-d067-45fd-ac4c-1ddeb13af3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860894625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.3860894625
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.1261087661
Short name T177
Test name
Test status
Simulation time 74079609446 ps
CPU time 179.93 seconds
Started Aug 15 05:22:32 PM PDT 24
Finished Aug 15 05:25:33 PM PDT 24
Peak memory 201240 kb
Host smart-84d5505b-d982-462d-81e5-8b13283c0bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261087661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.1261087661
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.2318417571
Short name T171
Test name
Test status
Simulation time 4138303588 ps
CPU time 2.72 seconds
Started Aug 15 05:22:26 PM PDT 24
Finished Aug 15 05:22:29 PM PDT 24
Peak memory 201108 kb
Host smart-69b4b063-98cb-40c1-9cf3-f16ba3879f94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318417571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.2318417571
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3617786408
Short name T872
Test name
Test status
Simulation time 2242152579 ps
CPU time 5.48 seconds
Started Aug 15 04:34:41 PM PDT 24
Finished Aug 15 04:34:47 PM PDT 24
Peak memory 209332 kb
Host smart-685a063c-3ab9-4939-84ae-10c471352f44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617786408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.3617786408
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.640722936
Short name T27
Test name
Test status
Simulation time 2897222004 ps
CPU time 2.5 seconds
Started Aug 15 05:21:56 PM PDT 24
Finished Aug 15 05:21:58 PM PDT 24
Peak memory 201164 kb
Host smart-84de2759-2733-4767-bd35-9abbfc8accfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640722936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.640722936
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.561489090
Short name T386
Test name
Test status
Simulation time 42698429457 ps
CPU time 17.24 seconds
Started Aug 15 04:35:02 PM PDT 24
Finished Aug 15 04:35:19 PM PDT 24
Peak memory 201224 kb
Host smart-1e075fd1-b988-456e-9202-839e40a799b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561489090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_tl_intg_err.561489090
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1894952441
Short name T377
Test name
Test status
Simulation time 73859893659 ps
CPU time 88.93 seconds
Started Aug 15 05:21:59 PM PDT 24
Finished Aug 15 05:23:28 PM PDT 24
Peak memory 201332 kb
Host smart-382764cd-dbc1-4d5c-b7b7-fd764e353f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894952441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.1894952441
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.83758961
Short name T456
Test name
Test status
Simulation time 9199035707 ps
CPU time 6.42 seconds
Started Aug 15 05:22:15 PM PDT 24
Finished Aug 15 05:22:21 PM PDT 24
Peak memory 201068 kb
Host smart-e674fcaf-9ab8-44b7-88b3-0eba1effa1ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83758961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stre
ss_all.83758961
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1357752038
Short name T393
Test name
Test status
Simulation time 106166627262 ps
CPU time 139.86 seconds
Started Aug 15 05:22:31 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 201260 kb
Host smart-f51daa11-f376-4fa9-a7fc-a9dbae0aa104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357752038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.1357752038
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1918910393
Short name T395
Test name
Test status
Simulation time 144642511532 ps
CPU time 390.9 seconds
Started Aug 15 05:22:10 PM PDT 24
Finished Aug 15 05:28:41 PM PDT 24
Peak memory 201300 kb
Host smart-50e06cfa-2e2d-46e2-95b1-ef4e74730990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918910393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.1918910393
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.2656830316
Short name T278
Test name
Test status
Simulation time 36545177219 ps
CPU time 25.67 seconds
Started Aug 15 05:22:48 PM PDT 24
Finished Aug 15 05:23:14 PM PDT 24
Peak memory 201280 kb
Host smart-dea5f1be-e1cb-4f91-a5da-24ff400eddce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656830316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.2656830316
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2766583008
Short name T272
Test name
Test status
Simulation time 52031415466 ps
CPU time 126.38 seconds
Started Aug 15 05:22:47 PM PDT 24
Finished Aug 15 05:24:54 PM PDT 24
Peak memory 201368 kb
Host smart-51934bf7-e9e4-4644-b8af-c66b37f55e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766583008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.2766583008
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.3595867848
Short name T129
Test name
Test status
Simulation time 152272225102 ps
CPU time 368.98 seconds
Started Aug 15 05:23:01 PM PDT 24
Finished Aug 15 05:29:10 PM PDT 24
Peak memory 201188 kb
Host smart-01919c10-a4d7-4311-a226-55f79fad3c76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595867848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.3595867848
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1139749780
Short name T399
Test name
Test status
Simulation time 116613339900 ps
CPU time 159.87 seconds
Started Aug 15 05:25:15 PM PDT 24
Finished Aug 15 05:27:55 PM PDT 24
Peak memory 201348 kb
Host smart-f3c18791-4042-40b7-b61c-80dedd222342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139749780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.1139749780
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2769365016
Short name T402
Test name
Test status
Simulation time 85937761446 ps
CPU time 38.18 seconds
Started Aug 15 05:23:55 PM PDT 24
Finished Aug 15 05:24:33 PM PDT 24
Peak memory 201316 kb
Host smart-b9c2e85f-95e4-409b-a4c9-68db977fe47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769365016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.2769365016
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1229560346
Short name T339
Test name
Test status
Simulation time 166016616229 ps
CPU time 34.78 seconds
Started Aug 15 05:23:47 PM PDT 24
Finished Aug 15 05:24:22 PM PDT 24
Peak memory 201244 kb
Host smart-8e7a6e96-c746-4f9b-8224-ff83129c9ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229560346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.1229560346
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.2574563937
Short name T184
Test name
Test status
Simulation time 4575414797 ps
CPU time 5.19 seconds
Started Aug 15 05:21:58 PM PDT 24
Finished Aug 15 05:22:03 PM PDT 24
Peak memory 201108 kb
Host smart-b2a3cd53-a3bd-4930-a6e1-537c41c9c11d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574563937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.2574563937
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.3330546047
Short name T214
Test name
Test status
Simulation time 4321001927 ps
CPU time 6.14 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:13 PM PDT 24
Peak memory 201132 kb
Host smart-3971e79a-6fc9-460d-9056-fda1a832c56b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330546047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.3330546047
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.1126325077
Short name T185
Test name
Test status
Simulation time 17371649915 ps
CPU time 37.19 seconds
Started Aug 15 05:22:55 PM PDT 24
Finished Aug 15 05:23:32 PM PDT 24
Peak memory 201020 kb
Host smart-554b5f11-a19b-4beb-a9c5-74ac215cb87d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126325077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.1126325077
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.2337760122
Short name T213
Test name
Test status
Simulation time 2815662854 ps
CPU time 2.15 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:21 PM PDT 24
Peak memory 201116 kb
Host smart-8d574148-e894-4249-a70a-d472ecb42a47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337760122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.2337760122
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.274929686
Short name T168
Test name
Test status
Simulation time 3226000617 ps
CPU time 8.38 seconds
Started Aug 15 05:22:05 PM PDT 24
Finished Aug 15 05:22:14 PM PDT 24
Peak memory 201052 kb
Host smart-75dc0528-a841-4f8a-835c-e644f1db0490
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274929686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl
_edge_detect.274929686
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1701433761
Short name T111
Test name
Test status
Simulation time 80484556812 ps
CPU time 100.05 seconds
Started Aug 15 05:22:54 PM PDT 24
Finished Aug 15 05:24:35 PM PDT 24
Peak memory 201268 kb
Host smart-9a9033ff-aa0a-49ff-b0d1-1acd4ec52ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701433761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_w
ith_pre_cond.1701433761
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.4121418183
Short name T109
Test name
Test status
Simulation time 77686364476 ps
CPU time 80.44 seconds
Started Aug 15 05:22:57 PM PDT 24
Finished Aug 15 05:24:23 PM PDT 24
Peak memory 201224 kb
Host smart-7acc8a46-e5fc-4033-9f7e-76b57d5d980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121418183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.4121418183
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1585918270
Short name T110
Test name
Test status
Simulation time 153146937369 ps
CPU time 98.88 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:25:33 PM PDT 24
Peak memory 201364 kb
Host smart-de799ec8-75b2-426a-acac-af2f3c131e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585918270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.1585918270
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3749905422
Short name T31
Test name
Test status
Simulation time 2820732873 ps
CPU time 5.18 seconds
Started Aug 15 04:34:45 PM PDT 24
Finished Aug 15 04:34:50 PM PDT 24
Peak memory 201048 kb
Host smart-1a6b7a67-76d8-4f5d-afc0-23102c4a41fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749905422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.3749905422
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3568290126
Short name T365
Test name
Test status
Simulation time 40477963389 ps
CPU time 220.7 seconds
Started Aug 15 04:34:49 PM PDT 24
Finished Aug 15 04:38:30 PM PDT 24
Peak memory 201028 kb
Host smart-b5d6e19f-b1e6-4690-a4b8-bb275cd985c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568290126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.3568290126
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3953769337
Short name T896
Test name
Test status
Simulation time 4015041855 ps
CPU time 10.89 seconds
Started Aug 15 04:34:40 PM PDT 24
Finished Aug 15 04:34:51 PM PDT 24
Peak memory 200752 kb
Host smart-02f547b8-2ce2-424c-9492-9e8a71495f4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953769337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.3953769337
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.447113542
Short name T884
Test name
Test status
Simulation time 2089505598 ps
CPU time 2.72 seconds
Started Aug 15 04:34:50 PM PDT 24
Finished Aug 15 04:34:53 PM PDT 24
Peak memory 200940 kb
Host smart-2423bae2-5cab-4890-81c8-b67673163112
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447113542 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.447113542
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1530290052
Short name T853
Test name
Test status
Simulation time 2055243755 ps
CPU time 6.28 seconds
Started Aug 15 04:34:45 PM PDT 24
Finished Aug 15 04:34:51 PM PDT 24
Peak memory 200836 kb
Host smart-b8cba71a-dbed-415a-914d-147602dbea2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530290052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.1530290052
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2788709221
Short name T833
Test name
Test status
Simulation time 2014100639 ps
CPU time 5.57 seconds
Started Aug 15 04:34:38 PM PDT 24
Finished Aug 15 04:34:44 PM PDT 24
Peak memory 200528 kb
Host smart-3fa8ae2e-78dc-4073-98af-a73f050a52e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788709221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.2788709221
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.211029102
Short name T311
Test name
Test status
Simulation time 42366681123 ps
CPU time 107.64 seconds
Started Aug 15 04:34:45 PM PDT 24
Finished Aug 15 04:36:33 PM PDT 24
Peak memory 201140 kb
Host smart-63b3e540-ab3e-4788-a08e-aeb96c78df0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211029102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_tl_intg_err.211029102
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1608419522
Short name T865
Test name
Test status
Simulation time 2716046091 ps
CPU time 5.48 seconds
Started Aug 15 04:34:49 PM PDT 24
Finished Aug 15 04:34:54 PM PDT 24
Peak memory 201020 kb
Host smart-d04ce9d5-6c82-456b-b49f-04b980ea9421
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608419522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.1608419522
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3617915099
Short name T893
Test name
Test status
Simulation time 38836230471 ps
CPU time 93.95 seconds
Started Aug 15 04:34:46 PM PDT 24
Finished Aug 15 04:36:21 PM PDT 24
Peak memory 201028 kb
Host smart-a888548f-aeef-4fa0-977d-6e1653153503
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617915099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.3617915099
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2815092896
Short name T364
Test name
Test status
Simulation time 6126465061 ps
CPU time 1.74 seconds
Started Aug 15 04:34:47 PM PDT 24
Finished Aug 15 04:34:49 PM PDT 24
Peak memory 200908 kb
Host smart-e5a767db-2b49-41fd-977f-49523ec72f94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815092896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.2815092896
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4111578924
Short name T877
Test name
Test status
Simulation time 2056746413 ps
CPU time 6.78 seconds
Started Aug 15 04:34:51 PM PDT 24
Finished Aug 15 04:34:58 PM PDT 24
Peak memory 200940 kb
Host smart-49a399c3-b01c-46e3-b802-2d590547dda3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111578924 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4111578924
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1135026180
Short name T816
Test name
Test status
Simulation time 2023911859 ps
CPU time 3.14 seconds
Started Aug 15 04:34:49 PM PDT 24
Finished Aug 15 04:34:52 PM PDT 24
Peak memory 200488 kb
Host smart-6312dea2-63b4-4342-907f-2bf1059b5b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135026180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.1135026180
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2361643977
Short name T864
Test name
Test status
Simulation time 4342878647 ps
CPU time 2.36 seconds
Started Aug 15 04:34:49 PM PDT 24
Finished Aug 15 04:34:52 PM PDT 24
Peak memory 200936 kb
Host smart-2a476c53-f3db-4bbf-a7ef-35e521af1cc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361643977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.2361643977
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.862888524
Short name T830
Test name
Test status
Simulation time 2073999832 ps
CPU time 2.18 seconds
Started Aug 15 04:34:59 PM PDT 24
Finished Aug 15 04:35:01 PM PDT 24
Peak memory 200860 kb
Host smart-5240ddc5-1ff9-49ad-9a58-2cc3186702eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862888524 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.862888524
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2696427581
Short name T360
Test name
Test status
Simulation time 2026318099 ps
CPU time 3.35 seconds
Started Aug 15 04:34:58 PM PDT 24
Finished Aug 15 04:35:02 PM PDT 24
Peak memory 200832 kb
Host smart-0e5af882-7c73-4342-9d8e-668bb82dc61b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696427581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.2696427581
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2656213260
Short name T804
Test name
Test status
Simulation time 2012373045 ps
CPU time 5.23 seconds
Started Aug 15 04:35:01 PM PDT 24
Finished Aug 15 04:35:06 PM PDT 24
Peak memory 200636 kb
Host smart-16fac4f8-56aa-4d7a-8cdd-f1881e791092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656213260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.2656213260
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2648906747
Short name T18
Test name
Test status
Simulation time 7738929178 ps
CPU time 29.2 seconds
Started Aug 15 04:35:02 PM PDT 24
Finished Aug 15 04:35:31 PM PDT 24
Peak memory 201220 kb
Host smart-32f757c1-9408-4f8a-b962-a8ad6cdc0846
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648906747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.2648906747
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.790888920
Short name T879
Test name
Test status
Simulation time 2081508960 ps
CPU time 2.97 seconds
Started Aug 15 04:34:58 PM PDT 24
Finished Aug 15 04:35:01 PM PDT 24
Peak memory 201192 kb
Host smart-d0f9f7cb-8638-492a-945c-70ff2ab46391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790888920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_error
s.790888920
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2998118811
Short name T860
Test name
Test status
Simulation time 42612834777 ps
CPU time 58.68 seconds
Started Aug 15 04:35:00 PM PDT 24
Finished Aug 15 04:35:59 PM PDT 24
Peak memory 201572 kb
Host smart-b1bca165-2438-4d7b-977a-45f3ca76a442
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998118811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.2998118811
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3383280829
Short name T806
Test name
Test status
Simulation time 2086842293 ps
CPU time 2.28 seconds
Started Aug 15 04:35:04 PM PDT 24
Finished Aug 15 04:35:06 PM PDT 24
Peak memory 200948 kb
Host smart-f41ba65a-b4f2-4127-af16-4975ead26c90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383280829 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3383280829
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3786679221
Short name T356
Test name
Test status
Simulation time 2041163090 ps
CPU time 3.46 seconds
Started Aug 15 04:35:01 PM PDT 24
Finished Aug 15 04:35:05 PM PDT 24
Peak memory 200744 kb
Host smart-a347d88d-767c-4c4d-be70-e6f229e3c57d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786679221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.3786679221
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1880639802
Short name T794
Test name
Test status
Simulation time 2034344614 ps
CPU time 1.86 seconds
Started Aug 15 04:35:01 PM PDT 24
Finished Aug 15 04:35:03 PM PDT 24
Peak memory 200840 kb
Host smart-f4701ed2-135d-41f7-bcac-6928c07fe1ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880639802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.1880639802
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1136409814
Short name T819
Test name
Test status
Simulation time 5287559935 ps
CPU time 10.21 seconds
Started Aug 15 04:35:08 PM PDT 24
Finished Aug 15 04:35:18 PM PDT 24
Peak memory 201560 kb
Host smart-7a2f550f-6784-4e37-92d7-37d19eead5fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136409814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.1136409814
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1612356993
Short name T849
Test name
Test status
Simulation time 3013149907 ps
CPU time 2.24 seconds
Started Aug 15 04:35:14 PM PDT 24
Finished Aug 15 04:35:17 PM PDT 24
Peak memory 201128 kb
Host smart-057bb886-20e3-44cd-b596-5fe88acc570b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612356993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.1612356993
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.804500103
Short name T300
Test name
Test status
Simulation time 42364188063 ps
CPU time 110.94 seconds
Started Aug 15 04:34:58 PM PDT 24
Finished Aug 15 04:36:49 PM PDT 24
Peak memory 201212 kb
Host smart-4d62624e-33be-4cd4-bcaa-970d9c911c7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804500103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_tl_intg_err.804500103
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.437595188
Short name T814
Test name
Test status
Simulation time 2060602258 ps
CPU time 2.21 seconds
Started Aug 15 04:35:10 PM PDT 24
Finished Aug 15 04:35:12 PM PDT 24
Peak memory 200960 kb
Host smart-f1cfc7c4-8e98-4d1b-9cb7-f645704a0629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437595188 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.437595188
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2659743518
Short name T918
Test name
Test status
Simulation time 2119800466 ps
CPU time 2.3 seconds
Started Aug 15 04:34:59 PM PDT 24
Finished Aug 15 04:35:02 PM PDT 24
Peak memory 200932 kb
Host smart-d1cb12f3-45cf-44e2-9fbe-421821fe91d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659743518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.2659743518
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1791321951
Short name T822
Test name
Test status
Simulation time 2021336840 ps
CPU time 3.04 seconds
Started Aug 15 04:34:58 PM PDT 24
Finished Aug 15 04:35:02 PM PDT 24
Peak memory 200592 kb
Host smart-02d99194-33f7-45d5-843f-c460e4606433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791321951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.1791321951
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.78218175
Short name T842
Test name
Test status
Simulation time 4765344586 ps
CPU time 4.05 seconds
Started Aug 15 04:35:00 PM PDT 24
Finished Aug 15 04:35:04 PM PDT 24
Peak memory 200856 kb
Host smart-496aac36-7fcb-4e83-9993-577cf04185a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78218175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=
sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
sysrst_ctrl_same_csr_outstanding.78218175
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1205957823
Short name T902
Test name
Test status
Simulation time 2397669055 ps
CPU time 3.44 seconds
Started Aug 15 04:34:58 PM PDT 24
Finished Aug 15 04:35:02 PM PDT 24
Peak memory 201192 kb
Host smart-6bbf543e-da6d-449b-acef-2ffea31eb5aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205957823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.1205957823
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3859150939
Short name T312
Test name
Test status
Simulation time 2113758663 ps
CPU time 2.43 seconds
Started Aug 15 04:35:08 PM PDT 24
Finished Aug 15 04:35:11 PM PDT 24
Peak memory 209416 kb
Host smart-16c48ec8-71e3-4c5b-8ba1-83e4b6946581
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859150939 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3859150939
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2062260487
Short name T891
Test name
Test status
Simulation time 2049535005 ps
CPU time 1.98 seconds
Started Aug 15 04:35:17 PM PDT 24
Finished Aug 15 04:35:19 PM PDT 24
Peak memory 200764 kb
Host smart-0603b6d6-b839-464a-84a5-cce97a095bad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062260487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.2062260487
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.785476001
Short name T844
Test name
Test status
Simulation time 2011323054 ps
CPU time 5.71 seconds
Started Aug 15 04:34:59 PM PDT 24
Finished Aug 15 04:35:05 PM PDT 24
Peak memory 200484 kb
Host smart-069bdae9-a843-4d7c-8fac-b8bcbbcc7380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785476001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_tes
t.785476001
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1387555680
Short name T20
Test name
Test status
Simulation time 8829118583 ps
CPU time 6.62 seconds
Started Aug 15 04:35:17 PM PDT 24
Finished Aug 15 04:35:24 PM PDT 24
Peak memory 201256 kb
Host smart-5f4eb879-2f13-47de-a7b9-1d606ab0ed5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387555680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.1387555680
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3536142038
Short name T874
Test name
Test status
Simulation time 2490034985 ps
CPU time 3.7 seconds
Started Aug 15 04:35:01 PM PDT 24
Finished Aug 15 04:35:05 PM PDT 24
Peak memory 201212 kb
Host smart-cc0c008d-099c-4b7f-a922-8c9cac3cb66c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536142038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.3536142038
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2256623548
Short name T807
Test name
Test status
Simulation time 22525458013 ps
CPU time 14.34 seconds
Started Aug 15 04:35:02 PM PDT 24
Finished Aug 15 04:35:16 PM PDT 24
Peak memory 201184 kb
Host smart-176654cb-69f3-4ab1-b540-c1d0577c6f36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256623548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.2256623548
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2263389844
Short name T30
Test name
Test status
Simulation time 2048591868 ps
CPU time 6.32 seconds
Started Aug 15 04:35:06 PM PDT 24
Finished Aug 15 04:35:13 PM PDT 24
Peak memory 200900 kb
Host smart-aaa13709-781e-46a0-ba74-e665213505ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263389844 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2263389844
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.64222993
Short name T908
Test name
Test status
Simulation time 2029552773 ps
CPU time 6.25 seconds
Started Aug 15 04:35:05 PM PDT 24
Finished Aug 15 04:35:11 PM PDT 24
Peak memory 200820 kb
Host smart-67bc00af-076f-4812-af9d-6c0a0eedb634
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64222993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw
.64222993
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1819225177
Short name T861
Test name
Test status
Simulation time 2080619923 ps
CPU time 1.27 seconds
Started Aug 15 04:35:13 PM PDT 24
Finished Aug 15 04:35:15 PM PDT 24
Peak memory 200628 kb
Host smart-12b2083f-802b-49d4-b085-646e64e96d51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819225177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.1819225177
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3368879694
Short name T19
Test name
Test status
Simulation time 10177341115 ps
CPU time 11.27 seconds
Started Aug 15 04:35:05 PM PDT 24
Finished Aug 15 04:35:17 PM PDT 24
Peak memory 201128 kb
Host smart-60feaff7-3e0c-43d5-a229-1d5127c0b732
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368879694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.3368879694
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1329173702
Short name T868
Test name
Test status
Simulation time 2456496203 ps
CPU time 3.53 seconds
Started Aug 15 04:35:03 PM PDT 24
Finished Aug 15 04:35:07 PM PDT 24
Peak memory 209400 kb
Host smart-1e4ea71c-c1c5-430a-ae68-851351e1ca9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329173702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.1329173702
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.328693273
Short name T862
Test name
Test status
Simulation time 22322635689 ps
CPU time 28.67 seconds
Started Aug 15 04:35:15 PM PDT 24
Finished Aug 15 04:35:44 PM PDT 24
Peak memory 201208 kb
Host smart-cbd4ccca-9bef-4ce4-aaf8-984b83442339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328693273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_tl_intg_err.328693273
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2544520709
Short name T843
Test name
Test status
Simulation time 2177510319 ps
CPU time 2.41 seconds
Started Aug 15 04:35:07 PM PDT 24
Finished Aug 15 04:35:10 PM PDT 24
Peak memory 201004 kb
Host smart-3cb6a2a4-7c82-4184-92b4-857e65f20946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544520709 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2544520709
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3572284295
Short name T361
Test name
Test status
Simulation time 2089814055 ps
CPU time 2.31 seconds
Started Aug 15 04:35:06 PM PDT 24
Finished Aug 15 04:35:08 PM PDT 24
Peak memory 200768 kb
Host smart-0cf5f40e-6079-4daa-8d26-f679546a8c68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572284295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.3572284295
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1260307722
Short name T797
Test name
Test status
Simulation time 2126548323 ps
CPU time 1.06 seconds
Started Aug 15 04:35:03 PM PDT 24
Finished Aug 15 04:35:04 PM PDT 24
Peak memory 200624 kb
Host smart-c7236d1b-6fc0-4128-8d10-4dd39f8d3647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260307722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.1260307722
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.477905087
Short name T876
Test name
Test status
Simulation time 10305480632 ps
CPU time 28.06 seconds
Started Aug 15 04:35:09 PM PDT 24
Finished Aug 15 04:35:38 PM PDT 24
Peak memory 201168 kb
Host smart-7eb76efb-2d84-47a1-bd36-672f28ee6d8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477905087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.sysrst_ctrl_same_csr_outstanding.477905087
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1848330638
Short name T827
Test name
Test status
Simulation time 2086916173 ps
CPU time 3.99 seconds
Started Aug 15 04:35:13 PM PDT 24
Finished Aug 15 04:35:17 PM PDT 24
Peak memory 201100 kb
Host smart-f786e643-d2a9-409f-8ee4-e2279e01109d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848330638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.1848330638
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3406245624
Short name T906
Test name
Test status
Simulation time 42795629822 ps
CPU time 31.05 seconds
Started Aug 15 04:35:09 PM PDT 24
Finished Aug 15 04:35:40 PM PDT 24
Peak memory 201228 kb
Host smart-a23fef00-d003-428e-9805-a277c447d184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406245624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.3406245624
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.456002857
Short name T408
Test name
Test status
Simulation time 2066946759 ps
CPU time 3.51 seconds
Started Aug 15 04:35:03 PM PDT 24
Finished Aug 15 04:35:07 PM PDT 24
Peak memory 200960 kb
Host smart-4d00cc1b-1fbd-4dd2-90df-4a05e1446118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456002857 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.456002857
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2313532942
Short name T366
Test name
Test status
Simulation time 2029123251 ps
CPU time 5.51 seconds
Started Aug 15 04:35:06 PM PDT 24
Finished Aug 15 04:35:11 PM PDT 24
Peak memory 200668 kb
Host smart-04513a23-bcd3-4356-829f-00371245caed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313532942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.2313532942
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1617647893
Short name T808
Test name
Test status
Simulation time 2052592880 ps
CPU time 1.97 seconds
Started Aug 15 04:35:10 PM PDT 24
Finished Aug 15 04:35:12 PM PDT 24
Peak memory 200540 kb
Host smart-eed79993-c878-4098-b993-2d834aff41bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617647893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.1617647893
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3084611527
Short name T829
Test name
Test status
Simulation time 5114897666 ps
CPU time 6.78 seconds
Started Aug 15 04:35:01 PM PDT 24
Finished Aug 15 04:35:08 PM PDT 24
Peak memory 201280 kb
Host smart-d8d94c11-ef73-4af5-b67c-7429a083073d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084611527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.3084611527
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.601514998
Short name T838
Test name
Test status
Simulation time 2265595559 ps
CPU time 5.33 seconds
Started Aug 15 04:35:06 PM PDT 24
Finished Aug 15 04:35:12 PM PDT 24
Peak memory 201184 kb
Host smart-4263bdd2-f863-4d54-9ce1-5ad478dda8f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601514998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_error
s.601514998
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.4037114783
Short name T911
Test name
Test status
Simulation time 43420866655 ps
CPU time 15.71 seconds
Started Aug 15 04:35:16 PM PDT 24
Finished Aug 15 04:35:32 PM PDT 24
Peak memory 201144 kb
Host smart-e854efce-48d7-4fae-abcc-b6331c7267ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037114783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.4037114783
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3000403632
Short name T824
Test name
Test status
Simulation time 2155562371 ps
CPU time 1.6 seconds
Started Aug 15 04:35:08 PM PDT 24
Finished Aug 15 04:35:09 PM PDT 24
Peak memory 201004 kb
Host smart-b39726d7-bcf9-44a5-b11c-4d46b70bedd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000403632 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3000403632
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3058853810
Short name T369
Test name
Test status
Simulation time 2114522259 ps
CPU time 2.26 seconds
Started Aug 15 04:35:17 PM PDT 24
Finished Aug 15 04:35:19 PM PDT 24
Peak memory 200884 kb
Host smart-784d2fee-5976-454d-b57b-234c9eb1f5c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058853810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.3058853810
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3154505937
Short name T863
Test name
Test status
Simulation time 2037164500 ps
CPU time 2.01 seconds
Started Aug 15 04:35:05 PM PDT 24
Finished Aug 15 04:35:07 PM PDT 24
Peak memory 200692 kb
Host smart-312ab8ad-1beb-447f-bb8c-0edb097a0f8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154505937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.3154505937
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1515033804
Short name T895
Test name
Test status
Simulation time 7203739502 ps
CPU time 26.71 seconds
Started Aug 15 04:35:08 PM PDT 24
Finished Aug 15 04:35:35 PM PDT 24
Peak memory 201192 kb
Host smart-131f503f-1188-47c0-ac7b-c2369b98b577
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515033804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.1515033804
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1508168030
Short name T301
Test name
Test status
Simulation time 2028292274 ps
CPU time 6.51 seconds
Started Aug 15 04:35:06 PM PDT 24
Finished Aug 15 04:35:13 PM PDT 24
Peak memory 201112 kb
Host smart-52082367-abcd-44d5-af3b-3fa41f1602aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508168030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.1508168030
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.981985820
Short name T293
Test name
Test status
Simulation time 42437178601 ps
CPU time 107.97 seconds
Started Aug 15 04:35:09 PM PDT 24
Finished Aug 15 04:36:57 PM PDT 24
Peak memory 201088 kb
Host smart-7d6c08a3-ba28-4d11-9e15-7e26a4281838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981985820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_tl_intg_err.981985820
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1019655252
Short name T856
Test name
Test status
Simulation time 2082737797 ps
CPU time 2.08 seconds
Started Aug 15 04:35:04 PM PDT 24
Finished Aug 15 04:35:06 PM PDT 24
Peak memory 200836 kb
Host smart-3b0c204e-01a1-4230-893d-1a1a5d409a45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019655252 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1019655252
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1009804593
Short name T905
Test name
Test status
Simulation time 2080985343 ps
CPU time 3.78 seconds
Started Aug 15 04:35:14 PM PDT 24
Finished Aug 15 04:35:18 PM PDT 24
Peak memory 200856 kb
Host smart-9020aa64-402e-4626-901c-624b021cbf99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009804593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.1009804593
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.58177866
Short name T845
Test name
Test status
Simulation time 2042510719 ps
CPU time 2.21 seconds
Started Aug 15 04:35:01 PM PDT 24
Finished Aug 15 04:35:03 PM PDT 24
Peak memory 200548 kb
Host smart-510af6d4-77e5-45fd-b50e-1f37a5c89595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58177866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test
.58177866
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1351152372
Short name T898
Test name
Test status
Simulation time 5335085148 ps
CPU time 6.7 seconds
Started Aug 15 04:35:04 PM PDT 24
Finished Aug 15 04:35:11 PM PDT 24
Peak memory 201200 kb
Host smart-43ba47ea-d25b-4af9-86ac-fdc41c7c1090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351152372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.1351152372
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1693886540
Short name T837
Test name
Test status
Simulation time 2175555271 ps
CPU time 4.86 seconds
Started Aug 15 04:35:14 PM PDT 24
Finished Aug 15 04:35:19 PM PDT 24
Peak memory 201184 kb
Host smart-318fd9c9-bbfa-4de6-862d-4a1d488971f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693886540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.1693886540
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1509052035
Short name T811
Test name
Test status
Simulation time 22217973616 ps
CPU time 30.45 seconds
Started Aug 15 04:35:05 PM PDT 24
Finished Aug 15 04:35:35 PM PDT 24
Peak memory 201200 kb
Host smart-2309d9d6-cb04-46ee-adf7-26f566f9e40b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509052035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.1509052035
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3159223714
Short name T825
Test name
Test status
Simulation time 2061683784 ps
CPU time 6.25 seconds
Started Aug 15 04:35:14 PM PDT 24
Finished Aug 15 04:35:20 PM PDT 24
Peak memory 200972 kb
Host smart-12d02b1e-30ac-44ed-a930-05c5bf4ce199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159223714 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3159223714
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2232270997
Short name T823
Test name
Test status
Simulation time 2069637059 ps
CPU time 2 seconds
Started Aug 15 04:35:13 PM PDT 24
Finished Aug 15 04:35:15 PM PDT 24
Peak memory 200872 kb
Host smart-d12aaf90-c6e6-4923-a0a0-7aefc5a53952
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232270997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.2232270997
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3862385882
Short name T857
Test name
Test status
Simulation time 2047892903 ps
CPU time 1.81 seconds
Started Aug 15 04:35:05 PM PDT 24
Finished Aug 15 04:35:07 PM PDT 24
Peak memory 200752 kb
Host smart-0e8dab0b-b0c6-4414-ae68-22edcd97724a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862385882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.3862385882
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1658421913
Short name T836
Test name
Test status
Simulation time 4704811407 ps
CPU time 9.25 seconds
Started Aug 15 04:35:09 PM PDT 24
Finished Aug 15 04:35:18 PM PDT 24
Peak memory 201208 kb
Host smart-e30482ac-71a8-4e02-be32-d2d02b974643
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658421913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.1658421913
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.684068380
Short name T313
Test name
Test status
Simulation time 2062409864 ps
CPU time 5.73 seconds
Started Aug 15 04:35:18 PM PDT 24
Finished Aug 15 04:35:24 PM PDT 24
Peak memory 209240 kb
Host smart-73d17a0d-26cd-464a-a608-0d4b2d172f94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684068380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_error
s.684068380
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1493767855
Short name T802
Test name
Test status
Simulation time 42951578888 ps
CPU time 31.37 seconds
Started Aug 15 04:35:13 PM PDT 24
Finished Aug 15 04:35:44 PM PDT 24
Peak memory 201204 kb
Host smart-a8285bd3-b14c-4d8a-a935-f2c726de374f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493767855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.1493767855
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3132165260
Short name T363
Test name
Test status
Simulation time 2395689604 ps
CPU time 8.52 seconds
Started Aug 15 04:34:49 PM PDT 24
Finished Aug 15 04:34:58 PM PDT 24
Peak memory 201056 kb
Host smart-adccb63d-95a1-466b-a509-5751c20805fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132165260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.3132165260
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.706470260
Short name T357
Test name
Test status
Simulation time 33186298612 ps
CPU time 86.99 seconds
Started Aug 15 04:34:47 PM PDT 24
Finished Aug 15 04:36:14 PM PDT 24
Peak memory 201504 kb
Host smart-c337e15e-9e0b-416c-9cc0-f42ca7ecc340
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706470260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_bit_bash.706470260
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.470538821
Short name T907
Test name
Test status
Simulation time 6029338124 ps
CPU time 15.64 seconds
Started Aug 15 04:34:46 PM PDT 24
Finished Aug 15 04:35:02 PM PDT 24
Peak memory 200956 kb
Host smart-3c0236f0-f7b9-4240-99dc-8c7db11a005e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470538821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_hw_reset.470538821
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1026753852
Short name T913
Test name
Test status
Simulation time 2038052444 ps
CPU time 5.99 seconds
Started Aug 15 04:34:47 PM PDT 24
Finished Aug 15 04:34:53 PM PDT 24
Peak memory 200940 kb
Host smart-6b781fb4-6dd6-4a34-b019-1e73981471a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026753852 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1026753852
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2580304626
Short name T866
Test name
Test status
Simulation time 2057328633 ps
CPU time 6.35 seconds
Started Aug 15 04:34:46 PM PDT 24
Finished Aug 15 04:34:53 PM PDT 24
Peak memory 200884 kb
Host smart-cac8f6d5-6d37-4e00-9f4f-bd6f70ce5aed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580304626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.2580304626
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.4067938372
Short name T809
Test name
Test status
Simulation time 2191714752 ps
CPU time 0.9 seconds
Started Aug 15 04:34:54 PM PDT 24
Finished Aug 15 04:34:55 PM PDT 24
Peak memory 200708 kb
Host smart-1dfbd3dc-6237-4d98-baaa-b860e1982bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067938372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.4067938372
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2291687340
Short name T850
Test name
Test status
Simulation time 5307482145 ps
CPU time 5.5 seconds
Started Aug 15 04:35:03 PM PDT 24
Finished Aug 15 04:35:09 PM PDT 24
Peak memory 201132 kb
Host smart-f6a595af-05f4-4d7f-90f0-abee3076d0da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291687340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.2291687340
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.900322048
Short name T917
Test name
Test status
Simulation time 2101124983 ps
CPU time 6.96 seconds
Started Aug 15 04:34:53 PM PDT 24
Finished Aug 15 04:35:00 PM PDT 24
Peak memory 201072 kb
Host smart-8887fc11-e1f1-4dc5-9b32-f62780b00fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900322048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors
.900322048
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.925665222
Short name T32
Test name
Test status
Simulation time 22202532876 ps
CPU time 59.78 seconds
Started Aug 15 04:34:54 PM PDT 24
Finished Aug 15 04:35:54 PM PDT 24
Peak memory 201152 kb
Host smart-e5b9a83c-20dc-435e-9427-31cad458d2c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925665222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_tl_intg_err.925665222
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2443143694
Short name T852
Test name
Test status
Simulation time 2026330849 ps
CPU time 2.57 seconds
Started Aug 15 04:35:06 PM PDT 24
Finished Aug 15 04:35:09 PM PDT 24
Peak memory 200608 kb
Host smart-220afce6-6fd4-4361-9314-326f56f05669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443143694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.2443143694
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.19875256
Short name T894
Test name
Test status
Simulation time 2013984441 ps
CPU time 5.56 seconds
Started Aug 15 04:35:07 PM PDT 24
Finished Aug 15 04:35:13 PM PDT 24
Peak memory 200592 kb
Host smart-a84470e0-91c4-40ab-b920-af1b9db54e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19875256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test
.19875256
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2092400447
Short name T803
Test name
Test status
Simulation time 2042207858 ps
CPU time 1.55 seconds
Started Aug 15 04:35:13 PM PDT 24
Finished Aug 15 04:35:15 PM PDT 24
Peak memory 200740 kb
Host smart-b60d2b10-477b-4aaa-82de-d6af61fd6232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092400447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.2092400447
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3891353045
Short name T799
Test name
Test status
Simulation time 2015053361 ps
CPU time 5.67 seconds
Started Aug 15 04:35:16 PM PDT 24
Finished Aug 15 04:35:22 PM PDT 24
Peak memory 200568 kb
Host smart-f6066aee-65b6-456a-bdef-1cb76af191a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891353045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.3891353045
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1592137617
Short name T854
Test name
Test status
Simulation time 2025367238 ps
CPU time 2.69 seconds
Started Aug 15 04:35:16 PM PDT 24
Finished Aug 15 04:35:19 PM PDT 24
Peak memory 200640 kb
Host smart-44c0bf91-9605-4ce1-8d34-12cd97394537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592137617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.1592137617
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.4193838908
Short name T805
Test name
Test status
Simulation time 2014717825 ps
CPU time 4.71 seconds
Started Aug 15 04:35:03 PM PDT 24
Finished Aug 15 04:35:08 PM PDT 24
Peak memory 200752 kb
Host smart-15bff252-86ae-49d4-8b68-99a438db1a1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193838908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.4193838908
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3416263271
Short name T912
Test name
Test status
Simulation time 2010799458 ps
CPU time 5.7 seconds
Started Aug 15 04:35:05 PM PDT 24
Finished Aug 15 04:35:11 PM PDT 24
Peak memory 200624 kb
Host smart-84be102f-9ed8-4cbe-b8f9-7083d45f1ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416263271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.3416263271
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2062277460
Short name T813
Test name
Test status
Simulation time 2043079294 ps
CPU time 1.83 seconds
Started Aug 15 04:35:06 PM PDT 24
Finished Aug 15 04:35:08 PM PDT 24
Peak memory 200568 kb
Host smart-be097da7-4e16-4c3d-a785-4f16ba8402f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062277460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.2062277460
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2060907140
Short name T881
Test name
Test status
Simulation time 2025513623 ps
CPU time 2.17 seconds
Started Aug 15 04:35:02 PM PDT 24
Finished Aug 15 04:35:04 PM PDT 24
Peak memory 200716 kb
Host smart-c53da888-4dd5-4ea1-9875-7c07b547ff30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060907140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.2060907140
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2294048354
Short name T801
Test name
Test status
Simulation time 2024578059 ps
CPU time 1.94 seconds
Started Aug 15 04:35:17 PM PDT 24
Finished Aug 15 04:35:19 PM PDT 24
Peak memory 200740 kb
Host smart-6eba929b-b92b-430e-b318-4c182c160abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294048354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.2294048354
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1978377810
Short name T826
Test name
Test status
Simulation time 2726929913 ps
CPU time 4.24 seconds
Started Aug 15 04:34:54 PM PDT 24
Finished Aug 15 04:34:59 PM PDT 24
Peak memory 201072 kb
Host smart-84587b08-9a90-4614-b8e4-2a4a7a84c87a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978377810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.1978377810
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3308479808
Short name T358
Test name
Test status
Simulation time 74314346978 ps
CPU time 101.98 seconds
Started Aug 15 04:34:47 PM PDT 24
Finished Aug 15 04:36:29 PM PDT 24
Peak memory 201076 kb
Host smart-39456159-ccfa-40d9-97ae-06746bcf643b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308479808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.3308479808
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1996127758
Short name T841
Test name
Test status
Simulation time 4088029811 ps
CPU time 2.26 seconds
Started Aug 15 04:34:46 PM PDT 24
Finished Aug 15 04:34:49 PM PDT 24
Peak memory 200840 kb
Host smart-b015108f-9ab8-4e11-8bb7-9f8196d4db1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996127758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.1996127758
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.994691024
Short name T855
Test name
Test status
Simulation time 2088522735 ps
CPU time 3 seconds
Started Aug 15 04:35:01 PM PDT 24
Finished Aug 15 04:35:05 PM PDT 24
Peak memory 200928 kb
Host smart-769fa99c-526a-4957-ac90-3e6e6514aeaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994691024 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.994691024
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2883012531
Short name T828
Test name
Test status
Simulation time 2044128344 ps
CPU time 3.23 seconds
Started Aug 15 04:34:59 PM PDT 24
Finished Aug 15 04:35:02 PM PDT 24
Peak memory 200788 kb
Host smart-3736701c-7cad-4103-a9f7-903927415260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883012531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.2883012531
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1981687306
Short name T897
Test name
Test status
Simulation time 2042411940 ps
CPU time 2.02 seconds
Started Aug 15 04:35:03 PM PDT 24
Finished Aug 15 04:35:05 PM PDT 24
Peak memory 200724 kb
Host smart-0c94cf38-4059-4fab-ae2c-aa453c92138a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981687306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.1981687306
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2507315621
Short name T903
Test name
Test status
Simulation time 7898587064 ps
CPU time 6.21 seconds
Started Aug 15 04:34:50 PM PDT 24
Finished Aug 15 04:34:56 PM PDT 24
Peak memory 201148 kb
Host smart-0c02f1ce-36cd-48e1-a374-547883335758
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507315621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.2507315621
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.900992901
Short name T878
Test name
Test status
Simulation time 2159546427 ps
CPU time 2.57 seconds
Started Aug 15 04:35:08 PM PDT 24
Finished Aug 15 04:35:11 PM PDT 24
Peak memory 209364 kb
Host smart-09669ff7-537f-41a1-8ae7-99c384d91b69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900992901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors
.900992901
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2311226332
Short name T812
Test name
Test status
Simulation time 22234708893 ps
CPU time 54.55 seconds
Started Aug 15 04:34:56 PM PDT 24
Finished Aug 15 04:35:51 PM PDT 24
Peak memory 201240 kb
Host smart-2bef95fb-9498-4dc2-931f-c79d180a8638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311226332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.2311226332
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.1772646336
Short name T815
Test name
Test status
Simulation time 2025040337 ps
CPU time 3.67 seconds
Started Aug 15 04:35:06 PM PDT 24
Finished Aug 15 04:35:10 PM PDT 24
Peak memory 200584 kb
Host smart-1336736c-9397-4df5-a4e0-b08718e36855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772646336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.1772646336
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.924607840
Short name T880
Test name
Test status
Simulation time 2017747636 ps
CPU time 5.8 seconds
Started Aug 15 04:35:04 PM PDT 24
Finished Aug 15 04:35:10 PM PDT 24
Peak memory 200588 kb
Host smart-59f03c92-1c16-4653-b7e5-d69d9a8db280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924607840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_tes
t.924607840
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.220992055
Short name T904
Test name
Test status
Simulation time 2023978117 ps
CPU time 2.55 seconds
Started Aug 15 04:35:10 PM PDT 24
Finished Aug 15 04:35:13 PM PDT 24
Peak memory 200540 kb
Host smart-dbcf29c0-8965-4635-b894-b786366275db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220992055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_tes
t.220992055
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3057620461
Short name T900
Test name
Test status
Simulation time 2017853911 ps
CPU time 5.38 seconds
Started Aug 15 04:35:11 PM PDT 24
Finished Aug 15 04:35:17 PM PDT 24
Peak memory 200564 kb
Host smart-b0e69114-f196-4912-b83b-ebff4faac161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057620461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.3057620461
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1901000566
Short name T890
Test name
Test status
Simulation time 2019079074 ps
CPU time 3.03 seconds
Started Aug 15 04:35:15 PM PDT 24
Finished Aug 15 04:35:18 PM PDT 24
Peak memory 200784 kb
Host smart-33b3a72e-2f2b-4f90-a16e-605c839eae94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901000566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.1901000566
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3329709097
Short name T916
Test name
Test status
Simulation time 2016987004 ps
CPU time 3.33 seconds
Started Aug 15 04:35:12 PM PDT 24
Finished Aug 15 04:35:15 PM PDT 24
Peak memory 200560 kb
Host smart-59367ce0-40ee-429f-ba9f-51c3acaffe73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329709097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.3329709097
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1533177132
Short name T831
Test name
Test status
Simulation time 2029556971 ps
CPU time 3.08 seconds
Started Aug 15 04:35:09 PM PDT 24
Finished Aug 15 04:35:12 PM PDT 24
Peak memory 200572 kb
Host smart-14110964-4a9e-4d00-b8ff-231b438ec8ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533177132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.1533177132
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2898007302
Short name T859
Test name
Test status
Simulation time 2028224523 ps
CPU time 1.89 seconds
Started Aug 15 04:35:27 PM PDT 24
Finished Aug 15 04:35:29 PM PDT 24
Peak memory 200644 kb
Host smart-7510c22a-02a8-4e76-9003-4036a0a68d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898007302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.2898007302
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2556574790
Short name T915
Test name
Test status
Simulation time 2040129023 ps
CPU time 1.99 seconds
Started Aug 15 04:35:21 PM PDT 24
Finished Aug 15 04:35:23 PM PDT 24
Peak memory 200676 kb
Host smart-b5b5fcde-779a-4219-931e-710fbb8cc1de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556574790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.2556574790
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.4027110756
Short name T885
Test name
Test status
Simulation time 2014827155 ps
CPU time 6 seconds
Started Aug 15 04:35:14 PM PDT 24
Finished Aug 15 04:35:21 PM PDT 24
Peak memory 200764 kb
Host smart-6c33a0d3-227e-443e-a81d-2dfc1f391a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027110756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.4027110756
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3919497439
Short name T892
Test name
Test status
Simulation time 2816878713 ps
CPU time 3.58 seconds
Started Aug 15 04:34:46 PM PDT 24
Finished Aug 15 04:34:50 PM PDT 24
Peak memory 201060 kb
Host smart-7bf276e4-9909-4423-81c9-1dc525e47c6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919497439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.3919497439
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3929834784
Short name T359
Test name
Test status
Simulation time 33001254519 ps
CPU time 69.5 seconds
Started Aug 15 04:34:51 PM PDT 24
Finished Aug 15 04:36:01 PM PDT 24
Peak memory 201076 kb
Host smart-b4f75f63-6fa7-4a98-9100-377c943440b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929834784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.3929834784
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.135253801
Short name T834
Test name
Test status
Simulation time 6078835580 ps
CPU time 4.69 seconds
Started Aug 15 04:34:47 PM PDT 24
Finished Aug 15 04:34:52 PM PDT 24
Peak memory 200968 kb
Host smart-a7a9337a-664a-47d6-a0c9-17d63d64c0f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135253801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_hw_reset.135253801
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2284753307
Short name T851
Test name
Test status
Simulation time 2077401202 ps
CPU time 3.76 seconds
Started Aug 15 04:34:47 PM PDT 24
Finished Aug 15 04:34:51 PM PDT 24
Peak memory 200936 kb
Host smart-2c730fa3-7fe1-4bb9-89d4-8195fae8a840
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284753307 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2284753307
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.593947047
Short name T362
Test name
Test status
Simulation time 2057320090 ps
CPU time 6.28 seconds
Started Aug 15 04:35:01 PM PDT 24
Finished Aug 15 04:35:07 PM PDT 24
Peak memory 200776 kb
Host smart-e677fae6-8c34-42bd-9571-73c29146ea31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593947047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw
.593947047
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.20389425
Short name T867
Test name
Test status
Simulation time 2080718334 ps
CPU time 1.11 seconds
Started Aug 15 04:34:54 PM PDT 24
Finished Aug 15 04:34:56 PM PDT 24
Peak memory 200716 kb
Host smart-1246e9dd-1acc-4378-ade5-10ca89929a99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20389425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.20389425
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.1926112293
Short name T869
Test name
Test status
Simulation time 4916592380 ps
CPU time 2.08 seconds
Started Aug 15 04:34:48 PM PDT 24
Finished Aug 15 04:34:51 PM PDT 24
Peak memory 200956 kb
Host smart-315fbbf9-ecd3-4cc8-8cdb-d9973bd92f60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926112293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.1926112293
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1694181836
Short name T901
Test name
Test status
Simulation time 2119437328 ps
CPU time 3.28 seconds
Started Aug 15 04:34:57 PM PDT 24
Finished Aug 15 04:35:00 PM PDT 24
Peak memory 201144 kb
Host smart-d508fecb-5fb7-4784-8b62-83c97b00c787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694181836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.1694181836
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3382114472
Short name T847
Test name
Test status
Simulation time 22261355909 ps
CPU time 55.95 seconds
Started Aug 15 04:34:47 PM PDT 24
Finished Aug 15 04:35:43 PM PDT 24
Peak memory 201140 kb
Host smart-c812e9ab-5efe-4bee-bf3d-b1c27a1bedf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382114472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.3382114472
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.554436250
Short name T818
Test name
Test status
Simulation time 2022755835 ps
CPU time 3.17 seconds
Started Aug 15 04:35:15 PM PDT 24
Finished Aug 15 04:35:19 PM PDT 24
Peak memory 200792 kb
Host smart-a6a9550c-3318-4b7d-964a-7ac99cbcc02e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554436250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_tes
t.554436250
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2871048877
Short name T820
Test name
Test status
Simulation time 2038052903 ps
CPU time 1.85 seconds
Started Aug 15 04:35:14 PM PDT 24
Finished Aug 15 04:35:16 PM PDT 24
Peak memory 200512 kb
Host smart-5dcf94b1-a8b7-4713-a81e-d19c3af7cfcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871048877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.2871048877
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.678691627
Short name T798
Test name
Test status
Simulation time 2039336707 ps
CPU time 1.95 seconds
Started Aug 15 04:35:12 PM PDT 24
Finished Aug 15 04:35:15 PM PDT 24
Peak memory 200552 kb
Host smart-fc6ad924-eef4-4fdb-9701-288ba4536880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678691627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_tes
t.678691627
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.1569720996
Short name T848
Test name
Test status
Simulation time 2012305480 ps
CPU time 5.8 seconds
Started Aug 15 04:35:12 PM PDT 24
Finished Aug 15 04:35:18 PM PDT 24
Peak memory 200752 kb
Host smart-6fd9ba79-7f3a-46e1-bdff-9a22e28af9b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569720996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.1569720996
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3659305868
Short name T882
Test name
Test status
Simulation time 2029094537 ps
CPU time 1.99 seconds
Started Aug 15 04:35:20 PM PDT 24
Finished Aug 15 04:35:22 PM PDT 24
Peak memory 200756 kb
Host smart-9583a097-a734-41db-82b7-82dcba111028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659305868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.3659305868
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3635238854
Short name T810
Test name
Test status
Simulation time 2034135976 ps
CPU time 1.45 seconds
Started Aug 15 04:35:13 PM PDT 24
Finished Aug 15 04:35:15 PM PDT 24
Peak memory 200568 kb
Host smart-83d438f8-2eda-429c-ac4f-b7cb29d6ca4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635238854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.3635238854
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.3026344232
Short name T796
Test name
Test status
Simulation time 2028312896 ps
CPU time 1.65 seconds
Started Aug 15 04:35:15 PM PDT 24
Finished Aug 15 04:35:17 PM PDT 24
Peak memory 200632 kb
Host smart-a43daa32-75b7-4071-9729-cbc34ba964a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026344232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.3026344232
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.102749149
Short name T795
Test name
Test status
Simulation time 2011524691 ps
CPU time 5.67 seconds
Started Aug 15 04:35:12 PM PDT 24
Finished Aug 15 04:35:18 PM PDT 24
Peak memory 200740 kb
Host smart-005b03ca-2b6a-44d0-8436-5a51cdbf6b86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102749149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_tes
t.102749149
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3034919415
Short name T875
Test name
Test status
Simulation time 2015624084 ps
CPU time 5.58 seconds
Started Aug 15 04:35:16 PM PDT 24
Finished Aug 15 04:35:22 PM PDT 24
Peak memory 200680 kb
Host smart-342227e0-1a72-4a17-9ec1-f96cd936d6e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034919415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.3034919415
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2879920662
Short name T821
Test name
Test status
Simulation time 2012460834 ps
CPU time 5.8 seconds
Started Aug 15 04:35:35 PM PDT 24
Finished Aug 15 04:35:41 PM PDT 24
Peak memory 200520 kb
Host smart-65785691-991a-40ae-b757-7cb941dc9d08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879920662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.2879920662
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3030127858
Short name T846
Test name
Test status
Simulation time 2069277639 ps
CPU time 4.41 seconds
Started Aug 15 04:35:09 PM PDT 24
Finished Aug 15 04:35:14 PM PDT 24
Peak memory 200876 kb
Host smart-70e325b4-7de2-47b9-8935-ae4451547da2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030127858 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3030127858
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3288459165
Short name T355
Test name
Test status
Simulation time 2050672293 ps
CPU time 5.73 seconds
Started Aug 15 04:34:49 PM PDT 24
Finished Aug 15 04:34:55 PM PDT 24
Peak memory 200856 kb
Host smart-824c072d-f016-44e1-ad1a-bef2172d7d08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288459165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.3288459165
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1035791026
Short name T887
Test name
Test status
Simulation time 2023146991 ps
CPU time 2.99 seconds
Started Aug 15 04:34:46 PM PDT 24
Finished Aug 15 04:34:49 PM PDT 24
Peak memory 200680 kb
Host smart-653b30fe-80c6-4917-944a-98c881ea88fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035791026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.1035791026
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.204696075
Short name T883
Test name
Test status
Simulation time 10544048041 ps
CPU time 19.32 seconds
Started Aug 15 04:34:49 PM PDT 24
Finished Aug 15 04:35:08 PM PDT 24
Peak memory 201080 kb
Host smart-1da12933-3830-46e5-8bb8-719623884330
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204696075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
sysrst_ctrl_same_csr_outstanding.204696075
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2940564362
Short name T871
Test name
Test status
Simulation time 2112794850 ps
CPU time 7.44 seconds
Started Aug 15 04:34:51 PM PDT 24
Finished Aug 15 04:34:59 PM PDT 24
Peak memory 209300 kb
Host smart-f8cea6a0-dd08-4531-a340-b9cd89d1d087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940564362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.2940564362
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.243434227
Short name T870
Test name
Test status
Simulation time 2154470889 ps
CPU time 2.43 seconds
Started Aug 15 04:34:49 PM PDT 24
Finished Aug 15 04:34:52 PM PDT 24
Peak memory 201052 kb
Host smart-e5d86b83-c686-48c7-bd16-86353f469a8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243434227 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.243434227
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.2842303604
Short name T889
Test name
Test status
Simulation time 2060938430 ps
CPU time 6.39 seconds
Started Aug 15 04:35:03 PM PDT 24
Finished Aug 15 04:35:10 PM PDT 24
Peak memory 200780 kb
Host smart-649ece30-cc50-497e-a65d-d50b6476a70f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842303604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.2842303604
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.517628557
Short name T909
Test name
Test status
Simulation time 2011377585 ps
CPU time 6.03 seconds
Started Aug 15 04:34:49 PM PDT 24
Finished Aug 15 04:34:56 PM PDT 24
Peak memory 200620 kb
Host smart-0875a244-c3f3-4a33-88d3-c70ae409de05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517628557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test
.517628557
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2241430772
Short name T858
Test name
Test status
Simulation time 10199535582 ps
CPU time 9.54 seconds
Started Aug 15 04:34:50 PM PDT 24
Finished Aug 15 04:35:00 PM PDT 24
Peak memory 201172 kb
Host smart-20991bc2-ea76-4d8a-a126-d8506cae425e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241430772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.2241430772
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3760006824
Short name T873
Test name
Test status
Simulation time 2173976357 ps
CPU time 3.95 seconds
Started Aug 15 04:34:48 PM PDT 24
Finished Aug 15 04:34:52 PM PDT 24
Peak memory 209400 kb
Host smart-e2ba6682-10f3-41b2-9f1d-5bbcbc6fabc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760006824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.3760006824
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3948046602
Short name T817
Test name
Test status
Simulation time 22541508584 ps
CPU time 15.25 seconds
Started Aug 15 04:34:48 PM PDT 24
Finished Aug 15 04:35:03 PM PDT 24
Peak memory 201200 kb
Host smart-a1cf45b3-269e-4a13-b89a-31ccc1e6c588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948046602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3948046602
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.995498892
Short name T888
Test name
Test status
Simulation time 2052606662 ps
CPU time 4.4 seconds
Started Aug 15 04:35:06 PM PDT 24
Finished Aug 15 04:35:10 PM PDT 24
Peak memory 200896 kb
Host smart-2e998e89-ab9c-4c8c-a68e-0f46af04c5eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995498892 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.995498892
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3192489095
Short name T33
Test name
Test status
Simulation time 2075802166 ps
CPU time 3.64 seconds
Started Aug 15 04:35:03 PM PDT 24
Finished Aug 15 04:35:07 PM PDT 24
Peak memory 200852 kb
Host smart-fdce16d2-e06a-4134-b20d-5bb518e84c78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192489095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.3192489095
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.4288331342
Short name T914
Test name
Test status
Simulation time 2031604679 ps
CPU time 1.82 seconds
Started Aug 15 04:34:59 PM PDT 24
Finished Aug 15 04:35:01 PM PDT 24
Peak memory 200496 kb
Host smart-f9edfc3b-62f2-4d0e-b227-5d6ca32afe11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288331342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.4288331342
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3151924924
Short name T368
Test name
Test status
Simulation time 9488706130 ps
CPU time 25.4 seconds
Started Aug 15 04:35:01 PM PDT 24
Finished Aug 15 04:35:26 PM PDT 24
Peak memory 201180 kb
Host smart-8dd1e1a7-de37-4eff-a34e-973fb9f35e6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151924924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.3151924924
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2518949777
Short name T303
Test name
Test status
Simulation time 2375273524 ps
CPU time 3.18 seconds
Started Aug 15 04:34:46 PM PDT 24
Finished Aug 15 04:34:50 PM PDT 24
Peak memory 201208 kb
Host smart-435e6fd2-c1c0-4061-bbef-314ba1c17853
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518949777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.2518949777
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1207637513
Short name T385
Test name
Test status
Simulation time 42415416348 ps
CPU time 52.82 seconds
Started Aug 15 04:35:04 PM PDT 24
Finished Aug 15 04:35:57 PM PDT 24
Peak memory 201268 kb
Host smart-3a648e63-1fee-4a98-9380-ce5e0c3b5ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207637513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.1207637513
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1372707788
Short name T800
Test name
Test status
Simulation time 2173942137 ps
CPU time 2.38 seconds
Started Aug 15 04:35:15 PM PDT 24
Finished Aug 15 04:35:17 PM PDT 24
Peak memory 201088 kb
Host smart-ef482b7e-bee7-40cb-ad16-6dc8f8953118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372707788 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1372707788
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3429348382
Short name T910
Test name
Test status
Simulation time 2063811510 ps
CPU time 5.58 seconds
Started Aug 15 04:35:00 PM PDT 24
Finished Aug 15 04:35:06 PM PDT 24
Peak memory 200776 kb
Host smart-8225512c-c1fc-4fc8-845b-e5cee56d0276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429348382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.3429348382
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2291777177
Short name T899
Test name
Test status
Simulation time 2039784959 ps
CPU time 1.84 seconds
Started Aug 15 04:35:00 PM PDT 24
Finished Aug 15 04:35:02 PM PDT 24
Peak memory 200604 kb
Host smart-6564dd5a-4716-47cc-a217-bd3c01fbfd24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291777177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.2291777177
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.4053533464
Short name T835
Test name
Test status
Simulation time 6518855952 ps
CPU time 26.01 seconds
Started Aug 15 04:35:13 PM PDT 24
Finished Aug 15 04:35:39 PM PDT 24
Peak memory 201128 kb
Host smart-0c03bd7c-b41e-4130-bd87-811e2fd4ca97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053533464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.4053533464
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.4185804067
Short name T299
Test name
Test status
Simulation time 2723189468 ps
CPU time 2.06 seconds
Started Aug 15 04:35:01 PM PDT 24
Finished Aug 15 04:35:03 PM PDT 24
Peak memory 201084 kb
Host smart-82f3b75d-a91d-43b1-82a5-b131dcbf742d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185804067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.4185804067
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1367860724
Short name T407
Test name
Test status
Simulation time 42355184212 ps
CPU time 115.51 seconds
Started Aug 15 04:35:07 PM PDT 24
Finished Aug 15 04:37:02 PM PDT 24
Peak memory 201184 kb
Host smart-91dba0e6-28f6-4afd-8be3-7a24aa5742b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367860724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.1367860724
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.212061734
Short name T840
Test name
Test status
Simulation time 2083122778 ps
CPU time 6.39 seconds
Started Aug 15 04:35:04 PM PDT 24
Finished Aug 15 04:35:10 PM PDT 24
Peak memory 200892 kb
Host smart-87f22445-6b15-4b2a-bbc8-e95a0414d3c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212061734 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.212061734
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3244787269
Short name T354
Test name
Test status
Simulation time 2034588386 ps
CPU time 5.79 seconds
Started Aug 15 04:35:00 PM PDT 24
Finished Aug 15 04:35:06 PM PDT 24
Peak memory 200788 kb
Host smart-15001fa8-9ff9-4a04-b03a-907cf687decb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244787269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.3244787269
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.855942626
Short name T832
Test name
Test status
Simulation time 2015154375 ps
CPU time 5.98 seconds
Started Aug 15 04:35:11 PM PDT 24
Finished Aug 15 04:35:18 PM PDT 24
Peak memory 200720 kb
Host smart-e38c71b2-6ab4-4254-a1da-7e05481cd0dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855942626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test
.855942626
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1471619113
Short name T839
Test name
Test status
Simulation time 4437248451 ps
CPU time 4.64 seconds
Started Aug 15 04:34:58 PM PDT 24
Finished Aug 15 04:35:03 PM PDT 24
Peak memory 201032 kb
Host smart-f985e29b-ff5d-4c51-acf7-7fb72d7c0544
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471619113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.1471619113
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1106396211
Short name T306
Test name
Test status
Simulation time 2117951706 ps
CPU time 3.1 seconds
Started Aug 15 04:35:01 PM PDT 24
Finished Aug 15 04:35:05 PM PDT 24
Peak memory 201112 kb
Host smart-337b8745-0c0d-4351-8e38-0712cc5a2b05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106396211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.1106396211
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1516766667
Short name T886
Test name
Test status
Simulation time 22218053756 ps
CPU time 54.78 seconds
Started Aug 15 04:35:14 PM PDT 24
Finished Aug 15 04:36:09 PM PDT 24
Peak memory 201168 kb
Host smart-ea961dd4-860a-4e7d-85f6-d18a3aefdab7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516766667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.1516766667
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.3764136654
Short name T435
Test name
Test status
Simulation time 2014983233 ps
CPU time 5.5 seconds
Started Aug 15 05:22:05 PM PDT 24
Finished Aug 15 05:22:11 PM PDT 24
Peak memory 201072 kb
Host smart-e6eb3e33-fd1f-4edc-a8c0-1bdcc108108c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764136654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.3764136654
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.197291410
Short name T291
Test name
Test status
Simulation time 132901620931 ps
CPU time 174.69 seconds
Started Aug 15 05:21:55 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 201232 kb
Host smart-0bd6d6cf-dde0-451a-9bb0-7b3e8396b1b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197291410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_combo_detect.197291410
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2134020306
Short name T438
Test name
Test status
Simulation time 2426451634 ps
CPU time 6.77 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:14 PM PDT 24
Peak memory 201092 kb
Host smart-e792dc32-5869-4826-a248-d2d5e8fba67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134020306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2134020306
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.820218638
Short name T702
Test name
Test status
Simulation time 2555416019 ps
CPU time 1.56 seconds
Started Aug 15 05:21:54 PM PDT 24
Finished Aug 15 05:21:56 PM PDT 24
Peak memory 201096 kb
Host smart-cc09e39c-54ba-410c-86b2-b58b990d81ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820218638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.820218638
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.981298027
Short name T582
Test name
Test status
Simulation time 2595897120 ps
CPU time 3.14 seconds
Started Aug 15 05:21:58 PM PDT 24
Finished Aug 15 05:22:01 PM PDT 24
Peak memory 201096 kb
Host smart-01b01251-bfb3-4c27-8ecd-4f9daf91b865
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981298027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_ec_pwr_on_rst.981298027
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1034596810
Short name T235
Test name
Test status
Simulation time 2615343476 ps
CPU time 4.21 seconds
Started Aug 15 05:22:00 PM PDT 24
Finished Aug 15 05:22:04 PM PDT 24
Peak memory 201100 kb
Host smart-fc9e7507-5055-4455-a556-7392ff23f13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034596810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.1034596810
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.2007207269
Short name T83
Test name
Test status
Simulation time 2461724152 ps
CPU time 6.57 seconds
Started Aug 15 05:22:08 PM PDT 24
Finished Aug 15 05:22:15 PM PDT 24
Peak memory 201112 kb
Host smart-a19ea820-7c11-45ba-8cef-6027084e7074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007207269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.2007207269
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1164773910
Short name T743
Test name
Test status
Simulation time 2261734729 ps
CPU time 0.97 seconds
Started Aug 15 05:21:59 PM PDT 24
Finished Aug 15 05:22:00 PM PDT 24
Peak memory 201108 kb
Host smart-e079d213-fbdd-4895-b2a4-eb0aef06807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164773910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1164773910
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.790991985
Short name T523
Test name
Test status
Simulation time 2531458029 ps
CPU time 2.32 seconds
Started Aug 15 05:22:03 PM PDT 24
Finished Aug 15 05:22:06 PM PDT 24
Peak memory 201100 kb
Host smart-8dc24f67-ad9f-4a43-a665-39cd7af51928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790991985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.790991985
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3144786298
Short name T315
Test name
Test status
Simulation time 42010312128 ps
CPU time 109.63 seconds
Started Aug 15 05:21:54 PM PDT 24
Finished Aug 15 05:23:44 PM PDT 24
Peak memory 220876 kb
Host smart-2f820fd1-05de-44aa-8a95-0f8a1afcd4c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144786298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3144786298
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.3836030704
Short name T467
Test name
Test status
Simulation time 2134984950 ps
CPU time 2.1 seconds
Started Aug 15 05:22:05 PM PDT 24
Finished Aug 15 05:22:08 PM PDT 24
Peak memory 201064 kb
Host smart-cc7b120f-46e4-484a-af72-0aaf0cd5cf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836030704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.3836030704
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1318620152
Short name T669
Test name
Test status
Simulation time 7189736403 ps
CPU time 10.01 seconds
Started Aug 15 05:22:02 PM PDT 24
Finished Aug 15 05:22:12 PM PDT 24
Peak memory 209548 kb
Host smart-6cfd7347-6469-4415-9e51-8effb0b0c51f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318620152 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.1318620152
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.1116328800
Short name T463
Test name
Test status
Simulation time 2036479199 ps
CPU time 1.86 seconds
Started Aug 15 05:21:57 PM PDT 24
Finished Aug 15 05:21:59 PM PDT 24
Peak memory 201108 kb
Host smart-59e191bc-3321-42c7-b638-a7b4f3ef7834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116328800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.1116328800
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3452676285
Short name T118
Test name
Test status
Simulation time 3762798949 ps
CPU time 10.48 seconds
Started Aug 15 05:21:58 PM PDT 24
Finished Aug 15 05:22:09 PM PDT 24
Peak memory 201196 kb
Host smart-1f2285e8-e9e4-4230-8585-3763ee21a611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452676285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.3452676285
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.3052718532
Short name T127
Test name
Test status
Simulation time 108475503131 ps
CPU time 145.03 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:24:32 PM PDT 24
Peak memory 201208 kb
Host smart-e4eafaeb-2094-4253-9184-5ca2739253a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052718532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.3052718532
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3738233570
Short name T665
Test name
Test status
Simulation time 2397387265 ps
CPU time 6.28 seconds
Started Aug 15 05:21:53 PM PDT 24
Finished Aug 15 05:21:59 PM PDT 24
Peak memory 201108 kb
Host smart-9f95a0ec-5b2f-440c-a844-5c05ecab0bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738233570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.3738233570
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1736328692
Short name T620
Test name
Test status
Simulation time 2339214165 ps
CPU time 6.4 seconds
Started Aug 15 05:22:02 PM PDT 24
Finished Aug 15 05:22:08 PM PDT 24
Peak memory 201064 kb
Host smart-4d8d9478-7d52-4a7a-aeed-b76fab502195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736328692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1736328692
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2692531903
Short name T567
Test name
Test status
Simulation time 25081387772 ps
CPU time 61.18 seconds
Started Aug 15 05:22:04 PM PDT 24
Finished Aug 15 05:23:05 PM PDT 24
Peak memory 201300 kb
Host smart-42064cd3-41c1-4c95-aea7-54e9fea87a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692531903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.2692531903
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1511241548
Short name T496
Test name
Test status
Simulation time 3530775993 ps
CPU time 5.55 seconds
Started Aug 15 05:22:03 PM PDT 24
Finished Aug 15 05:22:09 PM PDT 24
Peak memory 201088 kb
Host smart-d5c88952-f3d1-42d8-b9b2-562cf3056dee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511241548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.1511241548
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.2847604871
Short name T49
Test name
Test status
Simulation time 2720944207 ps
CPU time 2.28 seconds
Started Aug 15 05:22:01 PM PDT 24
Finished Aug 15 05:22:03 PM PDT 24
Peak memory 201048 kb
Host smart-872a2e61-87a0-4f8c-ba1b-2bb35800c7a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847604871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.2847604871
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1427452921
Short name T726
Test name
Test status
Simulation time 2658555524 ps
CPU time 1.75 seconds
Started Aug 15 05:21:59 PM PDT 24
Finished Aug 15 05:22:01 PM PDT 24
Peak memory 201072 kb
Host smart-891ef967-a8b2-4398-bb57-839ea9b0a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427452921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.1427452921
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.1103867560
Short name T640
Test name
Test status
Simulation time 2479504118 ps
CPU time 3.94 seconds
Started Aug 15 05:22:09 PM PDT 24
Finished Aug 15 05:22:13 PM PDT 24
Peak memory 201072 kb
Host smart-14777f7f-5db7-4105-a491-d84afd21e15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103867560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.1103867560
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.1270254408
Short name T749
Test name
Test status
Simulation time 2042583168 ps
CPU time 2.94 seconds
Started Aug 15 05:22:02 PM PDT 24
Finished Aug 15 05:22:05 PM PDT 24
Peak memory 201004 kb
Host smart-4bdb14a2-4fd7-4e14-8619-e86cc4710c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270254408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.1270254408
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.1510442812
Short name T422
Test name
Test status
Simulation time 2508257665 ps
CPU time 6.99 seconds
Started Aug 15 05:22:00 PM PDT 24
Finished Aug 15 05:22:07 PM PDT 24
Peak memory 201084 kb
Host smart-5eaae94c-b7f9-4d63-9e28-0618462cd5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510442812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.1510442812
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.137235874
Short name T294
Test name
Test status
Simulation time 22105806733 ps
CPU time 10.06 seconds
Started Aug 15 05:21:55 PM PDT 24
Finished Aug 15 05:22:06 PM PDT 24
Peak memory 220968 kb
Host smart-c16fcd33-b829-423c-98fd-343a0a5dfc27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137235874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.137235874
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.784202506
Short name T623
Test name
Test status
Simulation time 2108092398 ps
CPU time 5.43 seconds
Started Aug 15 05:22:01 PM PDT 24
Finished Aug 15 05:22:06 PM PDT 24
Peak memory 201040 kb
Host smart-2275a873-656d-4244-8b14-0878fab9e99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784202506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.784202506
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.1016221893
Short name T575
Test name
Test status
Simulation time 11238458961 ps
CPU time 2.64 seconds
Started Aug 15 05:22:06 PM PDT 24
Finished Aug 15 05:22:08 PM PDT 24
Peak memory 201120 kb
Host smart-81943be0-34a0-4d88-9656-3e95d26ca98c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016221893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.1016221893
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.489497876
Short name T615
Test name
Test status
Simulation time 6696537499 ps
CPU time 5.4 seconds
Started Aug 15 05:21:55 PM PDT 24
Finished Aug 15 05:22:00 PM PDT 24
Peak memory 209592 kb
Host smart-3486d8cf-ee36-41e9-b365-5d89655b995b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489497876 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.489497876
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1556619546
Short name T728
Test name
Test status
Simulation time 699380704770 ps
CPU time 27.85 seconds
Started Aug 15 05:22:00 PM PDT 24
Finished Aug 15 05:22:28 PM PDT 24
Peak memory 201092 kb
Host smart-bc581f55-ba63-4adf-9c54-e61a89779ee4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556619546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.1556619546
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.3876463649
Short name T777
Test name
Test status
Simulation time 2012349489 ps
CPU time 5.45 seconds
Started Aug 15 05:22:27 PM PDT 24
Finished Aug 15 05:22:33 PM PDT 24
Peak memory 201052 kb
Host smart-5958eed1-71ef-4257-95e5-c5744035a4f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876463649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.3876463649
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2061133083
Short name T711
Test name
Test status
Simulation time 3377884751 ps
CPU time 3.85 seconds
Started Aug 15 05:22:29 PM PDT 24
Finished Aug 15 05:22:33 PM PDT 24
Peak memory 201168 kb
Host smart-c5cbc953-0a32-407e-8e50-30335ce5b631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061133083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.2
061133083
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.602635502
Short name T603
Test name
Test status
Simulation time 84031774582 ps
CPU time 102.18 seconds
Started Aug 15 05:22:32 PM PDT 24
Finished Aug 15 05:24:14 PM PDT 24
Peak memory 201180 kb
Host smart-b4fd5c7a-91bc-40c9-b44b-a1c52d9de2b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602635502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_combo_detect.602635502
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1907102402
Short name T268
Test name
Test status
Simulation time 20338455748 ps
CPU time 27.4 seconds
Started Aug 15 05:22:30 PM PDT 24
Finished Aug 15 05:23:01 PM PDT 24
Peak memory 201312 kb
Host smart-48bf606b-0106-4314-a09d-34cc2b71042b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907102402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.1907102402
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2960273153
Short name T518
Test name
Test status
Simulation time 3015615922 ps
CPU time 8.27 seconds
Started Aug 15 05:22:31 PM PDT 24
Finished Aug 15 05:22:39 PM PDT 24
Peak memory 201084 kb
Host smart-2525ae7b-c727-48f2-9648-3c2e68c0c2c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960273153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.2960273153
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.2964818550
Short name T11
Test name
Test status
Simulation time 2529202734 ps
CPU time 6.44 seconds
Started Aug 15 05:22:34 PM PDT 24
Finished Aug 15 05:22:40 PM PDT 24
Peak memory 201032 kb
Host smart-da8b7015-d86a-4eee-9def-caf5c4fe26a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964818550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.2964818550
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2783379649
Short name T89
Test name
Test status
Simulation time 2612717437 ps
CPU time 6.49 seconds
Started Aug 15 05:22:28 PM PDT 24
Finished Aug 15 05:22:35 PM PDT 24
Peak memory 201128 kb
Host smart-20571346-4289-442b-8b1b-bd77699a2d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783379649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.2783379649
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.2981013049
Short name T85
Test name
Test status
Simulation time 2478252819 ps
CPU time 6.78 seconds
Started Aug 15 05:22:31 PM PDT 24
Finished Aug 15 05:22:38 PM PDT 24
Peak memory 201124 kb
Host smart-a77a6541-e586-4d5d-b35e-c8652cd75bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981013049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.2981013049
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.914707416
Short name T571
Test name
Test status
Simulation time 2035246604 ps
CPU time 6.03 seconds
Started Aug 15 05:22:26 PM PDT 24
Finished Aug 15 05:22:32 PM PDT 24
Peak memory 201040 kb
Host smart-1284ae7e-4cb8-490e-bdbd-bd46d9715b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914707416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.914707416
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.2087194449
Short name T508
Test name
Test status
Simulation time 2513403486 ps
CPU time 6.88 seconds
Started Aug 15 05:22:29 PM PDT 24
Finished Aug 15 05:22:36 PM PDT 24
Peak memory 201092 kb
Host smart-24fd0a4a-9aa2-4e16-ad3c-f100c10b2ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087194449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.2087194449
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.4283599626
Short name T578
Test name
Test status
Simulation time 2108565954 ps
CPU time 6.18 seconds
Started Aug 15 05:22:31 PM PDT 24
Finished Aug 15 05:22:37 PM PDT 24
Peak memory 201016 kb
Host smart-732b4115-8840-4a04-bb37-d9bfe3a5a8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283599626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.4283599626
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.358713002
Short name T724
Test name
Test status
Simulation time 107629416757 ps
CPU time 27.69 seconds
Started Aug 15 05:22:30 PM PDT 24
Finished Aug 15 05:22:58 PM PDT 24
Peak memory 201236 kb
Host smart-6db0e306-7c62-49db-bfaf-fac1aff0f151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358713002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_st
ress_all.358713002
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.2111312660
Short name T533
Test name
Test status
Simulation time 2024408708 ps
CPU time 2.76 seconds
Started Aug 15 05:22:34 PM PDT 24
Finished Aug 15 05:22:37 PM PDT 24
Peak memory 201140 kb
Host smart-9cbbdbd2-c89c-4a42-b324-5990f72ee9b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111312660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.2111312660
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2632564853
Short name T55
Test name
Test status
Simulation time 3723295434 ps
CPU time 5.06 seconds
Started Aug 15 05:22:33 PM PDT 24
Finished Aug 15 05:22:38 PM PDT 24
Peak memory 201148 kb
Host smart-4a7a45be-1fe1-4707-ac28-412570656a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632564853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2
632564853
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.2479808638
Short name T279
Test name
Test status
Simulation time 37993087422 ps
CPU time 96.02 seconds
Started Aug 15 05:22:26 PM PDT 24
Finished Aug 15 05:24:02 PM PDT 24
Peak memory 201276 kb
Host smart-b8e8747a-574b-4e55-90d2-a2c034da6faf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479808638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.2479808638
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3042544347
Short name T506
Test name
Test status
Simulation time 43913844684 ps
CPU time 29.55 seconds
Started Aug 15 05:22:30 PM PDT 24
Finished Aug 15 05:23:00 PM PDT 24
Peak memory 201292 kb
Host smart-4827d1ca-9bac-4bf7-9f88-48890364a084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042544347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.3042544347
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.1116741378
Short name T69
Test name
Test status
Simulation time 3062489255 ps
CPU time 2.69 seconds
Started Aug 15 05:22:28 PM PDT 24
Finished Aug 15 05:22:31 PM PDT 24
Peak memory 201092 kb
Host smart-7795dadd-9fff-4a99-bdcb-83ddeef251cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116741378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.1116741378
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.752983301
Short name T460
Test name
Test status
Simulation time 2634740587 ps
CPU time 2.3 seconds
Started Aug 15 05:22:30 PM PDT 24
Finished Aug 15 05:22:33 PM PDT 24
Peak memory 201108 kb
Host smart-de27d8d7-5073-472c-9525-55c2a343f2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752983301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.752983301
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.2580857720
Short name T627
Test name
Test status
Simulation time 2581455911 ps
CPU time 0.99 seconds
Started Aug 15 05:22:30 PM PDT 24
Finished Aug 15 05:22:31 PM PDT 24
Peak memory 201092 kb
Host smart-944d94d5-8d8f-4f73-83f1-c9e10f3a9940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580857720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.2580857720
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.40520911
Short name T449
Test name
Test status
Simulation time 2219142689 ps
CPU time 2.05 seconds
Started Aug 15 05:22:49 PM PDT 24
Finished Aug 15 05:22:51 PM PDT 24
Peak memory 201028 kb
Host smart-3b75c0e7-f065-4841-8854-1d20de93bc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40520911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.40520911
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.938960207
Short name T434
Test name
Test status
Simulation time 2529932284 ps
CPU time 2.58 seconds
Started Aug 15 05:22:28 PM PDT 24
Finished Aug 15 05:22:31 PM PDT 24
Peak memory 201040 kb
Host smart-d46de787-3954-4749-bf4f-c1f5bca31d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938960207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.938960207
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.3983232438
Short name T261
Test name
Test status
Simulation time 2172654481 ps
CPU time 1.25 seconds
Started Aug 15 05:22:28 PM PDT 24
Finished Aug 15 05:22:29 PM PDT 24
Peak memory 201076 kb
Host smart-a2d661a7-8777-4a53-8f53-37e8903d33d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983232438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.3983232438
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.371652700
Short name T624
Test name
Test status
Simulation time 12312389888 ps
CPU time 8.77 seconds
Started Aug 15 05:22:31 PM PDT 24
Finished Aug 15 05:22:41 PM PDT 24
Peak memory 201104 kb
Host smart-6d6c8097-6044-4ace-9c5b-c33eb5ab8fcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371652700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_st
ress_all.371652700
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.359342222
Short name T320
Test name
Test status
Simulation time 4378884802 ps
CPU time 8.97 seconds
Started Aug 15 05:22:28 PM PDT 24
Finished Aug 15 05:22:37 PM PDT 24
Peak memory 216816 kb
Host smart-21418145-eb9b-4de4-af96-31dc957e1a2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359342222 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.359342222
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.4281628020
Short name T706
Test name
Test status
Simulation time 3313399335 ps
CPU time 5.52 seconds
Started Aug 15 05:22:31 PM PDT 24
Finished Aug 15 05:22:37 PM PDT 24
Peak memory 201068 kb
Host smart-ef985333-22c2-42f6-9d84-852b628b6a63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281628020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.4281628020
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.131725214
Short name T790
Test name
Test status
Simulation time 2043848645 ps
CPU time 1.54 seconds
Started Aug 15 05:22:26 PM PDT 24
Finished Aug 15 05:22:28 PM PDT 24
Peak memory 201072 kb
Host smart-3ae86526-b215-4299-91ca-628175126a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131725214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_tes
t.131725214
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.334374240
Short name T521
Test name
Test status
Simulation time 3608410369 ps
CPU time 9.29 seconds
Started Aug 15 05:22:30 PM PDT 24
Finished Aug 15 05:22:39 PM PDT 24
Peak memory 201216 kb
Host smart-cf2ebc8a-c52d-4e6c-80d3-11054fe3f291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334374240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.334374240
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.2356000181
Short name T747
Test name
Test status
Simulation time 132956168570 ps
CPU time 162.46 seconds
Started Aug 15 05:22:30 PM PDT 24
Finished Aug 15 05:25:13 PM PDT 24
Peak memory 201160 kb
Host smart-9d6df7c1-10d1-42dd-b7c0-15bd2efb1f69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356000181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.2356000181
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.4061021578
Short name T243
Test name
Test status
Simulation time 3029698984 ps
CPU time 7.91 seconds
Started Aug 15 05:22:39 PM PDT 24
Finished Aug 15 05:22:47 PM PDT 24
Peak memory 201080 kb
Host smart-059c9882-e2d8-425d-87e1-647275a0f476
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061021578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.4061021578
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2524210842
Short name T612
Test name
Test status
Simulation time 2637053989 ps
CPU time 2.45 seconds
Started Aug 15 05:22:49 PM PDT 24
Finished Aug 15 05:22:52 PM PDT 24
Peak memory 201028 kb
Host smart-26a10f91-625f-4c1f-af74-189dcb894f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524210842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.2524210842
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2339350294
Short name T745
Test name
Test status
Simulation time 2495326497 ps
CPU time 2.15 seconds
Started Aug 15 05:22:33 PM PDT 24
Finished Aug 15 05:22:36 PM PDT 24
Peak memory 201108 kb
Host smart-ff2bc5df-b3c2-4845-98b3-afb394212147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339350294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2339350294
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.1757719740
Short name T520
Test name
Test status
Simulation time 2231705624 ps
CPU time 1.96 seconds
Started Aug 15 05:22:28 PM PDT 24
Finished Aug 15 05:22:30 PM PDT 24
Peak memory 201072 kb
Host smart-b236b40d-b28a-46e9-ae09-69c8aa6e5bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757719740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.1757719740
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.244505716
Short name T514
Test name
Test status
Simulation time 2617026381 ps
CPU time 1.2 seconds
Started Aug 15 05:22:31 PM PDT 24
Finished Aug 15 05:22:32 PM PDT 24
Peak memory 201064 kb
Host smart-e18cf141-d87b-4225-9857-bd1619194f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244505716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.244505716
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.142552096
Short name T644
Test name
Test status
Simulation time 2111592419 ps
CPU time 4.69 seconds
Started Aug 15 05:22:33 PM PDT 24
Finished Aug 15 05:22:38 PM PDT 24
Peak memory 200996 kb
Host smart-a647e1a7-ccc4-465b-9aa0-492b91476010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142552096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.142552096
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1843719857
Short name T746
Test name
Test status
Simulation time 4189434881 ps
CPU time 6.46 seconds
Started Aug 15 05:22:30 PM PDT 24
Finished Aug 15 05:22:37 PM PDT 24
Peak memory 201268 kb
Host smart-a65f3937-ccee-47b8-afe8-855a9885562a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843719857 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.1843719857
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3706868303
Short name T150
Test name
Test status
Simulation time 3389565948647 ps
CPU time 18.4 seconds
Started Aug 15 05:22:29 PM PDT 24
Finished Aug 15 05:22:47 PM PDT 24
Peak memory 201040 kb
Host smart-eda305b4-2082-4d7f-9770-c64e391b05f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706868303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.3706868303
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.4029526385
Short name T471
Test name
Test status
Simulation time 2020627595 ps
CPU time 3.16 seconds
Started Aug 15 05:22:39 PM PDT 24
Finished Aug 15 05:22:43 PM PDT 24
Peak memory 200980 kb
Host smart-caedd694-7e59-456c-82f0-d75ab6d7a3c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029526385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.4029526385
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2684317252
Short name T606
Test name
Test status
Simulation time 121510204930 ps
CPU time 318.82 seconds
Started Aug 15 05:22:30 PM PDT 24
Finished Aug 15 05:27:49 PM PDT 24
Peak memory 201200 kb
Host smart-7945d612-070a-4e03-adf6-ee98aa268c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684317252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.2
684317252
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1185570485
Short name T54
Test name
Test status
Simulation time 77699293823 ps
CPU time 97.62 seconds
Started Aug 15 05:22:37 PM PDT 24
Finished Aug 15 05:24:14 PM PDT 24
Peak memory 201288 kb
Host smart-e5f38b82-0d71-4c41-85d2-c68916f2cadc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185570485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.1185570485
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1912629247
Short name T253
Test name
Test status
Simulation time 160223756901 ps
CPU time 85.35 seconds
Started Aug 15 05:22:28 PM PDT 24
Finished Aug 15 05:23:53 PM PDT 24
Peak memory 201292 kb
Host smart-a9a83d96-07af-4b05-b6e4-abf818e520d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912629247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.1912629247
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1232918093
Short name T768
Test name
Test status
Simulation time 3870311006 ps
CPU time 4.45 seconds
Started Aug 15 05:22:29 PM PDT 24
Finished Aug 15 05:22:34 PM PDT 24
Peak memory 201104 kb
Host smart-93957d33-b491-4e73-9932-a36c793113c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232918093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1232918093
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.3949292724
Short name T50
Test name
Test status
Simulation time 3250981196 ps
CPU time 1.61 seconds
Started Aug 15 05:22:31 PM PDT 24
Finished Aug 15 05:22:33 PM PDT 24
Peak memory 200980 kb
Host smart-a4faa6be-38f7-4b6e-88a5-231a58891cee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949292724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.3949292724
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2033060651
Short name T249
Test name
Test status
Simulation time 2615870897 ps
CPU time 4.18 seconds
Started Aug 15 05:22:28 PM PDT 24
Finished Aug 15 05:22:33 PM PDT 24
Peak memory 201128 kb
Host smart-abfaa91a-1f17-4be4-abb6-304daf6c4656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033060651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.2033060651
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.2950621515
Short name T719
Test name
Test status
Simulation time 2468075591 ps
CPU time 2.94 seconds
Started Aug 15 05:22:29 PM PDT 24
Finished Aug 15 05:22:32 PM PDT 24
Peak memory 201112 kb
Host smart-6021b7e6-780e-4cd5-af2c-64ad26fdee7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950621515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.2950621515
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.3986843491
Short name T572
Test name
Test status
Simulation time 2228075290 ps
CPU time 6.91 seconds
Started Aug 15 05:22:39 PM PDT 24
Finished Aug 15 05:22:46 PM PDT 24
Peak memory 201024 kb
Host smart-e4425252-45f4-4031-a9a0-5a454fcdda30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986843491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.3986843491
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1106818911
Short name T595
Test name
Test status
Simulation time 2513731095 ps
CPU time 6.78 seconds
Started Aug 15 05:22:43 PM PDT 24
Finished Aug 15 05:22:50 PM PDT 24
Peak memory 201096 kb
Host smart-f1eee850-9712-4b16-97e3-c69c2244129b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106818911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.1106818911
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.2937239729
Short name T485
Test name
Test status
Simulation time 2136330876 ps
CPU time 1.86 seconds
Started Aug 15 05:22:29 PM PDT 24
Finished Aug 15 05:22:31 PM PDT 24
Peak memory 201064 kb
Host smart-274dfa9b-f097-4c6e-82d1-8cb6edb39baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937239729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.2937239729
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.794526956
Short name T782
Test name
Test status
Simulation time 7406214035 ps
CPU time 5.82 seconds
Started Aug 15 05:22:29 PM PDT 24
Finished Aug 15 05:22:40 PM PDT 24
Peak memory 201152 kb
Host smart-d91b35fa-5fc2-434e-acd8-f67156dee268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794526956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_st
ress_all.794526956
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.3829613694
Short name T273
Test name
Test status
Simulation time 2028094170 ps
CPU time 1.91 seconds
Started Aug 15 05:22:33 PM PDT 24
Finished Aug 15 05:22:35 PM PDT 24
Peak memory 201100 kb
Host smart-bbb1c5de-d46a-4077-8cc0-9ebed776963f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829613694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.3829613694
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2274798724
Short name T548
Test name
Test status
Simulation time 33541045946 ps
CPU time 21.1 seconds
Started Aug 15 05:22:36 PM PDT 24
Finished Aug 15 05:22:57 PM PDT 24
Peak memory 201048 kb
Host smart-dd1d58b3-461b-4986-8edd-d598566af583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274798724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.2
274798724
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1060333764
Short name T277
Test name
Test status
Simulation time 83190795640 ps
CPU time 81.95 seconds
Started Aug 15 05:22:28 PM PDT 24
Finished Aug 15 05:23:50 PM PDT 24
Peak memory 201208 kb
Host smart-7ce9292d-f01b-4141-99fa-e0f44d8c0021
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060333764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.1060333764
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3358712439
Short name T752
Test name
Test status
Simulation time 129972195460 ps
CPU time 309.56 seconds
Started Aug 15 05:22:59 PM PDT 24
Finished Aug 15 05:28:09 PM PDT 24
Peak memory 201288 kb
Host smart-88555e2a-ec19-4541-977d-e8b3df699393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358712439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.3358712439
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.179860210
Short name T48
Test name
Test status
Simulation time 3598959052 ps
CPU time 3 seconds
Started Aug 15 05:22:29 PM PDT 24
Finished Aug 15 05:22:32 PM PDT 24
Peak memory 201040 kb
Host smart-b64c9921-f6e2-4eae-b68a-586c1407f96a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179860210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctr
l_edge_detect.179860210
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2077001995
Short name T671
Test name
Test status
Simulation time 2628316396 ps
CPU time 2.47 seconds
Started Aug 15 05:22:44 PM PDT 24
Finished Aug 15 05:22:47 PM PDT 24
Peak memory 201120 kb
Host smart-96ab02c4-b45c-4673-af19-b8999ee45f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077001995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.2077001995
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3944831322
Short name T164
Test name
Test status
Simulation time 2456699528 ps
CPU time 8.06 seconds
Started Aug 15 05:22:31 PM PDT 24
Finished Aug 15 05:22:44 PM PDT 24
Peak memory 201136 kb
Host smart-714a0575-85e2-409b-abd5-8fb461b5691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944831322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.3944831322
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.1627769693
Short name T472
Test name
Test status
Simulation time 2231725153 ps
CPU time 1.59 seconds
Started Aug 15 05:22:28 PM PDT 24
Finished Aug 15 05:22:30 PM PDT 24
Peak memory 201100 kb
Host smart-7c7ac482-5a29-4334-8767-a09d83081e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627769693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.1627769693
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.1018596205
Short name T159
Test name
Test status
Simulation time 2571577743 ps
CPU time 1.57 seconds
Started Aug 15 05:22:30 PM PDT 24
Finished Aug 15 05:22:32 PM PDT 24
Peak memory 201136 kb
Host smart-5623e834-db85-4a90-b1ab-82bd5b333d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018596205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.1018596205
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.2642848451
Short name T577
Test name
Test status
Simulation time 2113416596 ps
CPU time 3.33 seconds
Started Aug 15 05:22:38 PM PDT 24
Finished Aug 15 05:22:41 PM PDT 24
Peak memory 201020 kb
Host smart-a1e035c3-69c0-4e69-abd6-390fd7f397e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642848451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.2642848451
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.2300283239
Short name T263
Test name
Test status
Simulation time 99924838815 ps
CPU time 163.89 seconds
Started Aug 15 05:22:57 PM PDT 24
Finished Aug 15 05:25:41 PM PDT 24
Peak memory 201152 kb
Host smart-672126d9-c12a-49c5-b9d3-52a9fbf0b29a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300283239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.2300283239
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3917239155
Short name T326
Test name
Test status
Simulation time 4815760145 ps
CPU time 10.4 seconds
Started Aug 15 05:22:29 PM PDT 24
Finished Aug 15 05:22:40 PM PDT 24
Peak memory 201296 kb
Host smart-aa2eef46-9b8f-44e2-932d-68208c6b7941
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917239155 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.3917239155
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3799624770
Short name T21
Test name
Test status
Simulation time 4117796791 ps
CPU time 2.44 seconds
Started Aug 15 05:22:31 PM PDT 24
Finished Aug 15 05:22:34 PM PDT 24
Peak memory 201088 kb
Host smart-2be9a81d-e614-480d-be0d-ec264311c642
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799624770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.3799624770
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.3638030524
Short name T441
Test name
Test status
Simulation time 2015239286 ps
CPU time 3.2 seconds
Started Aug 15 05:22:36 PM PDT 24
Finished Aug 15 05:22:40 PM PDT 24
Peak memory 201076 kb
Host smart-c15b624b-5156-4b3f-b1ef-3caef0dc7c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638030524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.3638030524
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2817352605
Short name T617
Test name
Test status
Simulation time 3365948765 ps
CPU time 2.93 seconds
Started Aug 15 05:22:35 PM PDT 24
Finished Aug 15 05:22:38 PM PDT 24
Peak memory 201140 kb
Host smart-0c3f862d-ddce-4a06-b87e-de4bc766ae8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817352605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
817352605
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.3556216534
Short name T259
Test name
Test status
Simulation time 192763357282 ps
CPU time 27.67 seconds
Started Aug 15 05:22:37 PM PDT 24
Finished Aug 15 05:23:05 PM PDT 24
Peak memory 201224 kb
Host smart-90508901-ddc6-4477-af04-920a92b94f2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556216534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.3556216534
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3494671106
Short name T633
Test name
Test status
Simulation time 3658443643 ps
CPU time 5.47 seconds
Started Aug 15 05:22:53 PM PDT 24
Finished Aug 15 05:22:59 PM PDT 24
Peak memory 201056 kb
Host smart-81aee459-3cfd-43d4-9e91-705bdf2f17f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494671106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.3494671106
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.2468117524
Short name T107
Test name
Test status
Simulation time 3077429507 ps
CPU time 4.23 seconds
Started Aug 15 05:22:40 PM PDT 24
Finished Aug 15 05:22:44 PM PDT 24
Peak memory 201080 kb
Host smart-8f05787c-59b8-4eaa-b7a7-5a495a5a9a7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468117524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.2468117524
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1128105239
Short name T534
Test name
Test status
Simulation time 2639113921 ps
CPU time 2.23 seconds
Started Aug 15 05:22:32 PM PDT 24
Finished Aug 15 05:22:34 PM PDT 24
Peak memory 201080 kb
Host smart-a51f8ce7-7cea-4f76-a3dd-947a8c57c91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128105239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.1128105239
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2422777847
Short name T24
Test name
Test status
Simulation time 2462378024 ps
CPU time 3.74 seconds
Started Aug 15 05:22:33 PM PDT 24
Finished Aug 15 05:22:37 PM PDT 24
Peak memory 201100 kb
Host smart-ba7a351a-7afe-42ad-9486-37a9128ea899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422777847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.2422777847
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.128370202
Short name T546
Test name
Test status
Simulation time 2102608912 ps
CPU time 6.13 seconds
Started Aug 15 05:22:35 PM PDT 24
Finished Aug 15 05:22:41 PM PDT 24
Peak memory 201032 kb
Host smart-934b8e1b-c671-4c19-befa-d55b9fabf7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128370202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.128370202
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.3453426607
Short name T492
Test name
Test status
Simulation time 2511920390 ps
CPU time 6.86 seconds
Started Aug 15 05:22:38 PM PDT 24
Finished Aug 15 05:22:45 PM PDT 24
Peak memory 201096 kb
Host smart-1468d42b-99be-47e7-af01-9b47757cabf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453426607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.3453426607
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.2374062487
Short name T474
Test name
Test status
Simulation time 2111024512 ps
CPU time 6.28 seconds
Started Aug 15 05:22:51 PM PDT 24
Finished Aug 15 05:22:58 PM PDT 24
Peak memory 201024 kb
Host smart-b0a07a6a-e291-4303-824c-46bcb24fd743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374062487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.2374062487
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.3507157047
Short name T43
Test name
Test status
Simulation time 13174706095 ps
CPU time 16.97 seconds
Started Aug 15 05:22:52 PM PDT 24
Finished Aug 15 05:23:09 PM PDT 24
Peak memory 201096 kb
Host smart-2fdc8879-0d38-44b8-9763-a7337e3c5985
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507157047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.3507157047
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.310188734
Short name T335
Test name
Test status
Simulation time 18675488403 ps
CPU time 11.53 seconds
Started Aug 15 05:22:41 PM PDT 24
Finished Aug 15 05:22:53 PM PDT 24
Peak memory 209636 kb
Host smart-ad4f133c-99fd-466b-aa72-73b717c8b044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310188734 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.310188734
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3323373456
Short name T72
Test name
Test status
Simulation time 3129698391 ps
CPU time 5.01 seconds
Started Aug 15 05:22:47 PM PDT 24
Finished Aug 15 05:22:52 PM PDT 24
Peak memory 201164 kb
Host smart-170cc241-a72d-4a00-bb7a-45edb3033ea6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323373456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.3323373456
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.894771877
Short name T536
Test name
Test status
Simulation time 2012852766 ps
CPU time 5.88 seconds
Started Aug 15 05:22:40 PM PDT 24
Finished Aug 15 05:22:46 PM PDT 24
Peak memory 200928 kb
Host smart-cdb306cf-44b0-470d-8002-a9725e396180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894771877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_tes
t.894771877
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.740154640
Short name T61
Test name
Test status
Simulation time 307690763381 ps
CPU time 829.76 seconds
Started Aug 15 05:22:43 PM PDT 24
Finished Aug 15 05:36:33 PM PDT 24
Peak memory 201140 kb
Host smart-67f3a615-e3d6-40d4-a2d1-c73dc008d445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740154640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.740154640
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.365257678
Short name T285
Test name
Test status
Simulation time 89012852202 ps
CPU time 209.93 seconds
Started Aug 15 05:22:56 PM PDT 24
Finished Aug 15 05:26:27 PM PDT 24
Peak memory 201216 kb
Host smart-e4ba6f07-b296-43b4-9013-4cc6d4a8a9e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365257678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_combo_detect.365257678
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2466510814
Short name T344
Test name
Test status
Simulation time 62879300739 ps
CPU time 140.1 seconds
Started Aug 15 05:22:46 PM PDT 24
Finished Aug 15 05:25:07 PM PDT 24
Peak memory 201260 kb
Host smart-66f50b27-fe7d-4d75-b78b-4e4edf5b1cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466510814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.2466510814
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1287686091
Short name T597
Test name
Test status
Simulation time 2727102920 ps
CPU time 7.07 seconds
Started Aug 15 05:22:53 PM PDT 24
Finished Aug 15 05:23:00 PM PDT 24
Peak memory 201128 kb
Host smart-11600181-d700-47bf-90d1-bc74a474250e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287686091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.1287686091
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.204348072
Short name T186
Test name
Test status
Simulation time 2403482819 ps
CPU time 6.31 seconds
Started Aug 15 05:22:36 PM PDT 24
Finished Aug 15 05:22:43 PM PDT 24
Peak memory 201092 kb
Host smart-578fa1fb-cfb9-44a5-a87f-20d214387211
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204348072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctr
l_edge_detect.204348072
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.381240568
Short name T596
Test name
Test status
Simulation time 2611707859 ps
CPU time 7.41 seconds
Started Aug 15 05:22:52 PM PDT 24
Finished Aug 15 05:22:59 PM PDT 24
Peak memory 201100 kb
Host smart-9f0bcc0e-4854-474d-95d2-6a2d1a6d8c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381240568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.381240568
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.1003389405
Short name T14
Test name
Test status
Simulation time 2448687340 ps
CPU time 6.78 seconds
Started Aug 15 05:22:42 PM PDT 24
Finished Aug 15 05:22:49 PM PDT 24
Peak memory 201060 kb
Host smart-5d37f4f3-d439-43fb-a55e-2273f37b6641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003389405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.1003389405
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.4275856939
Short name T565
Test name
Test status
Simulation time 2190214835 ps
CPU time 6.03 seconds
Started Aug 15 05:22:37 PM PDT 24
Finished Aug 15 05:22:43 PM PDT 24
Peak memory 201124 kb
Host smart-bdfcb7ba-789f-4f39-9b6d-ba5cc6f4657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275856939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.4275856939
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.792980309
Short name T421
Test name
Test status
Simulation time 2513880869 ps
CPU time 3.87 seconds
Started Aug 15 05:22:37 PM PDT 24
Finished Aug 15 05:22:41 PM PDT 24
Peak memory 201100 kb
Host smart-b4de201d-9611-40b2-b80c-42e6640a72a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792980309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.792980309
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.925859686
Short name T274
Test name
Test status
Simulation time 2135664289 ps
CPU time 1.41 seconds
Started Aug 15 05:22:36 PM PDT 24
Finished Aug 15 05:22:38 PM PDT 24
Peak memory 200908 kb
Host smart-c703e923-64c2-45c5-ab99-bd5b9ed7a875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925859686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.925859686
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.2250586770
Short name T165
Test name
Test status
Simulation time 84873569686 ps
CPU time 43.24 seconds
Started Aug 15 05:22:57 PM PDT 24
Finished Aug 15 05:23:40 PM PDT 24
Peak memory 201108 kb
Host smart-3f452bf9-bf5b-435f-b81c-9d0a89eaf7d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250586770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.2250586770
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.3823080387
Short name T318
Test name
Test status
Simulation time 7752916591 ps
CPU time 11.7 seconds
Started Aug 15 05:22:52 PM PDT 24
Finished Aug 15 05:23:04 PM PDT 24
Peak memory 212596 kb
Host smart-b9da2a48-e9c3-4b43-8ef9-87dfe9d5e350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823080387 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.3823080387
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2508970738
Short name T99
Test name
Test status
Simulation time 4503149507 ps
CPU time 6.08 seconds
Started Aug 15 05:22:37 PM PDT 24
Finished Aug 15 05:22:43 PM PDT 24
Peak memory 201136 kb
Host smart-c84d3080-fc0d-493a-8f91-c343bb17c20f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508970738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.2508970738
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.3136761019
Short name T574
Test name
Test status
Simulation time 2135313517 ps
CPU time 0.91 seconds
Started Aug 15 05:22:49 PM PDT 24
Finished Aug 15 05:22:50 PM PDT 24
Peak memory 201136 kb
Host smart-bc417f94-6233-4580-9827-57711b9c2b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136761019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.3136761019
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2492186022
Short name T542
Test name
Test status
Simulation time 3116543425 ps
CPU time 9.28 seconds
Started Aug 15 05:22:56 PM PDT 24
Finished Aug 15 05:23:06 PM PDT 24
Peak memory 201132 kb
Host smart-9a1588a4-4e5d-4394-9eb6-2ee354dd21a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492186022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.2
492186022
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.360778488
Short name T381
Test name
Test status
Simulation time 94214144286 ps
CPU time 111.76 seconds
Started Aug 15 05:22:51 PM PDT 24
Finished Aug 15 05:24:43 PM PDT 24
Peak memory 201176 kb
Host smart-bfc9f13d-8200-458c-ad1c-1cf858ad152c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360778488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_combo_detect.360778488
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.4155459622
Short name T269
Test name
Test status
Simulation time 185564628444 ps
CPU time 130.02 seconds
Started Aug 15 05:23:05 PM PDT 24
Finished Aug 15 05:25:15 PM PDT 24
Peak memory 201360 kb
Host smart-aa6e4645-93c6-4c82-837f-3fc05719010d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155459622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.4155459622
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1855621406
Short name T65
Test name
Test status
Simulation time 4903008001 ps
CPU time 13.46 seconds
Started Aug 15 05:22:38 PM PDT 24
Finished Aug 15 05:22:52 PM PDT 24
Peak memory 201104 kb
Host smart-70c50b56-84ad-481c-9c57-5a7c82886291
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855621406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.1855621406
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.1302705447
Short name T188
Test name
Test status
Simulation time 3165168537 ps
CPU time 2.44 seconds
Started Aug 15 05:22:48 PM PDT 24
Finished Aug 15 05:22:50 PM PDT 24
Peak memory 201076 kb
Host smart-965bb16a-30c0-4723-9849-f1ea154a7dd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302705447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.1302705447
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2701316132
Short name T450
Test name
Test status
Simulation time 2619041724 ps
CPU time 4.16 seconds
Started Aug 15 05:22:41 PM PDT 24
Finished Aug 15 05:22:46 PM PDT 24
Peak memory 201072 kb
Host smart-3ba4f9b9-2c91-47b5-a3ed-4bdb5c52eb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701316132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.2701316132
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.1007453291
Short name T591
Test name
Test status
Simulation time 2347724401 ps
CPU time 0.98 seconds
Started Aug 15 05:22:38 PM PDT 24
Finished Aug 15 05:22:39 PM PDT 24
Peak memory 201120 kb
Host smart-d9555a6b-381d-48d5-8d88-db12b40f6adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007453291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.1007453291
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.2288899350
Short name T515
Test name
Test status
Simulation time 2507809036 ps
CPU time 7.12 seconds
Started Aug 15 05:22:40 PM PDT 24
Finished Aug 15 05:22:47 PM PDT 24
Peak memory 200920 kb
Host smart-3f828212-8500-4966-910a-8ec608c5e81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288899350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.2288899350
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.3551651128
Short name T786
Test name
Test status
Simulation time 2110997380 ps
CPU time 5.75 seconds
Started Aug 15 05:22:44 PM PDT 24
Finished Aug 15 05:22:50 PM PDT 24
Peak memory 200952 kb
Host smart-0faab884-86cb-4f70-a481-10ce683775b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551651128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.3551651128
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1018832185
Short name T420
Test name
Test status
Simulation time 15405902710 ps
CPU time 5.4 seconds
Started Aug 15 05:22:55 PM PDT 24
Finished Aug 15 05:23:01 PM PDT 24
Peak memory 201320 kb
Host smart-fbd61b0b-a065-4781-8ad1-59615d7ac27b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018832185 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.1018832185
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.24884386
Short name T519
Test name
Test status
Simulation time 2030931085 ps
CPU time 1.95 seconds
Started Aug 15 05:22:52 PM PDT 24
Finished Aug 15 05:22:54 PM PDT 24
Peak memory 201072 kb
Host smart-62836ea0-c70c-4d66-8f35-de290ec8eb74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24884386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test
.24884386
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1751819352
Short name T117
Test name
Test status
Simulation time 3543841733 ps
CPU time 2.92 seconds
Started Aug 15 05:22:48 PM PDT 24
Finished Aug 15 05:22:51 PM PDT 24
Peak memory 201236 kb
Host smart-23879f09-df6d-4584-9b09-8cf551c7ada9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751819352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1
751819352
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.634569365
Short name T374
Test name
Test status
Simulation time 98108744624 ps
CPU time 16.91 seconds
Started Aug 15 05:22:52 PM PDT 24
Finished Aug 15 05:23:09 PM PDT 24
Peak memory 201304 kb
Host smart-6f051186-fb63-4023-9bfb-cfea732fe5e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634569365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_combo_detect.634569365
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.514639900
Short name T621
Test name
Test status
Simulation time 3958697031 ps
CPU time 5.58 seconds
Started Aug 15 05:22:44 PM PDT 24
Finished Aug 15 05:22:50 PM PDT 24
Peak memory 201092 kb
Host smart-109c5891-d331-4e7f-b7ab-71bd314af65a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514639900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_ec_pwr_on_rst.514639900
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.4135517500
Short name T236
Test name
Test status
Simulation time 3213365766 ps
CPU time 2.94 seconds
Started Aug 15 05:22:49 PM PDT 24
Finished Aug 15 05:22:52 PM PDT 24
Peak memory 201080 kb
Host smart-180e838b-2160-4d00-a19d-2403c8551e1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135517500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.4135517500
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1269976815
Short name T642
Test name
Test status
Simulation time 2721521973 ps
CPU time 1.09 seconds
Started Aug 15 05:22:59 PM PDT 24
Finished Aug 15 05:23:00 PM PDT 24
Peak memory 201136 kb
Host smart-1f94bba8-de99-4bca-a3a7-655838604bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269976815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.1269976815
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3944919030
Short name T328
Test name
Test status
Simulation time 2473623702 ps
CPU time 2.42 seconds
Started Aug 15 05:22:47 PM PDT 24
Finished Aug 15 05:22:50 PM PDT 24
Peak memory 201136 kb
Host smart-ee8b5921-b883-4301-8486-749aa89191bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944919030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.3944919030
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.2846634610
Short name T678
Test name
Test status
Simulation time 2131831765 ps
CPU time 3.5 seconds
Started Aug 15 05:22:57 PM PDT 24
Finished Aug 15 05:23:01 PM PDT 24
Peak memory 201076 kb
Host smart-900399a2-9efd-478a-b9ff-ddf1be5b52b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846634610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.2846634610
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.3064388581
Short name T447
Test name
Test status
Simulation time 2514371525 ps
CPU time 7.36 seconds
Started Aug 15 05:22:45 PM PDT 24
Finished Aug 15 05:22:53 PM PDT 24
Peak memory 201104 kb
Host smart-f03e88ec-43f6-435e-a113-3b4e8f4b1b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064388581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.3064388581
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.1798195138
Short name T700
Test name
Test status
Simulation time 2119691262 ps
CPU time 3.33 seconds
Started Aug 15 05:22:56 PM PDT 24
Finished Aug 15 05:23:00 PM PDT 24
Peak memory 201032 kb
Host smart-7b002431-8bf6-4ac8-9670-d5fc8d73e84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798195138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.1798195138
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.414375792
Short name T321
Test name
Test status
Simulation time 312159757402 ps
CPU time 13.3 seconds
Started Aug 15 05:22:40 PM PDT 24
Finished Aug 15 05:22:53 PM PDT 24
Peak memory 201168 kb
Host smart-11580859-e1e3-4986-9dfe-2fd26410921a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414375792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_st
ress_all.414375792
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2321256128
Short name T457
Test name
Test status
Simulation time 9244570954 ps
CPU time 12.44 seconds
Started Aug 15 05:22:39 PM PDT 24
Finished Aug 15 05:22:51 PM PDT 24
Peak memory 217796 kb
Host smart-0f925010-3050-4b8b-814a-65d14c56e47c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321256128 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.2321256128
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.107073360
Short name T346
Test name
Test status
Simulation time 3076871179 ps
CPU time 5.52 seconds
Started Aug 15 05:22:34 PM PDT 24
Finished Aug 15 05:22:40 PM PDT 24
Peak memory 201148 kb
Host smart-7495222d-562b-4687-bb72-33e5ddcde63a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107073360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_ultra_low_pwr.107073360
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.754765143
Short name T710
Test name
Test status
Simulation time 2061008376 ps
CPU time 1.22 seconds
Started Aug 15 05:22:39 PM PDT 24
Finished Aug 15 05:22:40 PM PDT 24
Peak memory 201076 kb
Host smart-1607726a-0873-449e-b80b-40ee8909840d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754765143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_tes
t.754765143
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.2314608771
Short name T651
Test name
Test status
Simulation time 3181199569 ps
CPU time 8.98 seconds
Started Aug 15 05:22:42 PM PDT 24
Finished Aug 15 05:22:51 PM PDT 24
Peak memory 201164 kb
Host smart-3cf049ff-f111-4205-92a0-15519c251f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314608771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.2
314608771
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.3476969471
Short name T132
Test name
Test status
Simulation time 63460211154 ps
CPU time 11.78 seconds
Started Aug 15 05:22:52 PM PDT 24
Finished Aug 15 05:23:04 PM PDT 24
Peak memory 201244 kb
Host smart-32ebcee9-414a-4e7b-975d-d9d73081b24b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476969471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.3476969471
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2579542847
Short name T388
Test name
Test status
Simulation time 56954952068 ps
CPU time 37 seconds
Started Aug 15 05:22:40 PM PDT 24
Finished Aug 15 05:23:17 PM PDT 24
Peak memory 201316 kb
Host smart-1add5c26-9491-4beb-adc7-1230e66e573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579542847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.2579542847
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.4284291771
Short name T415
Test name
Test status
Simulation time 1266153439137 ps
CPU time 3213.67 seconds
Started Aug 15 05:22:47 PM PDT 24
Finished Aug 15 06:16:21 PM PDT 24
Peak memory 201056 kb
Host smart-98465780-d0f4-4e4f-8440-e0f820ee7d54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284291771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ec_pwr_on_rst.4284291771
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.219021974
Short name T680
Test name
Test status
Simulation time 2610077535 ps
CPU time 6.98 seconds
Started Aug 15 05:22:40 PM PDT 24
Finished Aug 15 05:22:47 PM PDT 24
Peak memory 201060 kb
Host smart-6fbce209-765d-4323-ba66-298d2ceff620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219021974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.219021974
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.424990193
Short name T444
Test name
Test status
Simulation time 2483331297 ps
CPU time 2.16 seconds
Started Aug 15 05:22:47 PM PDT 24
Finished Aug 15 05:22:49 PM PDT 24
Peak memory 201100 kb
Host smart-26a3fea0-596c-4145-abc9-3d1ece28bd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424990193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.424990193
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.36767043
Short name T260
Test name
Test status
Simulation time 2106518663 ps
CPU time 3.35 seconds
Started Aug 15 05:22:40 PM PDT 24
Finished Aug 15 05:22:43 PM PDT 24
Peak memory 200996 kb
Host smart-8de32159-a624-48ba-98d1-83d5f27a3d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36767043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.36767043
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.1529163152
Short name T524
Test name
Test status
Simulation time 2535585297 ps
CPU time 2.37 seconds
Started Aug 15 05:22:57 PM PDT 24
Finished Aug 15 05:23:00 PM PDT 24
Peak memory 201104 kb
Host smart-5637d830-c054-4883-949d-d98365f36c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529163152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.1529163152
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.3768553136
Short name T446
Test name
Test status
Simulation time 2113346797 ps
CPU time 6.01 seconds
Started Aug 15 05:22:41 PM PDT 24
Finished Aug 15 05:22:48 PM PDT 24
Peak memory 201016 kb
Host smart-7cf052d3-3e96-446d-8643-0a5f1f130875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768553136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.3768553136
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.1922022417
Short name T781
Test name
Test status
Simulation time 12668018284 ps
CPU time 28.63 seconds
Started Aug 15 05:22:51 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 201040 kb
Host smart-5cee0f5c-d08f-47f2-a08f-ad1c70427624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922022417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.1922022417
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1163979439
Short name T552
Test name
Test status
Simulation time 6805137350 ps
CPU time 2.31 seconds
Started Aug 15 05:22:50 PM PDT 24
Finished Aug 15 05:22:53 PM PDT 24
Peak memory 201096 kb
Host smart-bd012b84-39b7-4802-95fd-ba77246e3307
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163979439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.1163979439
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.2601219801
Short name T451
Test name
Test status
Simulation time 2014942593 ps
CPU time 5.23 seconds
Started Aug 15 05:21:56 PM PDT 24
Finished Aug 15 05:22:01 PM PDT 24
Peak memory 201068 kb
Host smart-6723b1e7-d35c-4298-a403-0e9e4b68002b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601219801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.2601219801
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3662253302
Short name T793
Test name
Test status
Simulation time 3572087922 ps
CPU time 1.6 seconds
Started Aug 15 05:22:04 PM PDT 24
Finished Aug 15 05:22:06 PM PDT 24
Peak memory 201436 kb
Host smart-6ff8364e-dda5-4f8a-963c-a709a14bb88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662253302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.3662253302
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.686725446
Short name T201
Test name
Test status
Simulation time 2389425753 ps
CPU time 6.38 seconds
Started Aug 15 05:22:04 PM PDT 24
Finished Aug 15 05:22:11 PM PDT 24
Peak memory 201088 kb
Host smart-8e86f67b-9585-4060-810c-465e8be5f997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686725446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.686725446
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1097085629
Short name T95
Test name
Test status
Simulation time 2545680860 ps
CPU time 6.67 seconds
Started Aug 15 05:22:05 PM PDT 24
Finished Aug 15 05:22:12 PM PDT 24
Peak memory 201092 kb
Host smart-08dedbed-da09-4e70-be1c-9cabb946c1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097085629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1097085629
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.498566128
Short name T649
Test name
Test status
Simulation time 3684800226 ps
CPU time 5.37 seconds
Started Aug 15 05:22:03 PM PDT 24
Finished Aug 15 05:22:08 PM PDT 24
Peak memory 201116 kb
Host smart-50d48a12-f66c-48df-a27a-2dd8ae2ff098
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498566128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_ec_pwr_on_rst.498566128
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.154529227
Short name T430
Test name
Test status
Simulation time 2646111876 ps
CPU time 1.85 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:10 PM PDT 24
Peak memory 201064 kb
Host smart-d133879e-8cb2-4877-8c57-c79486cd204e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154529227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.154529227
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.761136799
Short name T86
Test name
Test status
Simulation time 2503495742 ps
CPU time 1.74 seconds
Started Aug 15 05:22:02 PM PDT 24
Finished Aug 15 05:22:03 PM PDT 24
Peak memory 201088 kb
Host smart-1d2ce017-e3ca-492b-9090-fcbd03760557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761136799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.761136799
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2021738753
Short name T762
Test name
Test status
Simulation time 2265728312 ps
CPU time 3.5 seconds
Started Aug 15 05:22:04 PM PDT 24
Finished Aug 15 05:22:07 PM PDT 24
Peak memory 201056 kb
Host smart-469a48ca-b863-4d28-a223-8eb8381b6a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021738753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.2021738753
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.2029685218
Short name T314
Test name
Test status
Simulation time 22011705487 ps
CPU time 58.06 seconds
Started Aug 15 05:22:04 PM PDT 24
Finished Aug 15 05:23:03 PM PDT 24
Peak memory 220656 kb
Host smart-1a6529f3-97d1-4a3a-87d7-226982cafd3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029685218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.2029685218
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.2072555391
Short name T316
Test name
Test status
Simulation time 2219478018 ps
CPU time 0.98 seconds
Started Aug 15 05:21:58 PM PDT 24
Finished Aug 15 05:21:59 PM PDT 24
Peak memory 201096 kb
Host smart-571b4a07-ba40-4202-91e7-e78d80557d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072555391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.2072555391
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.522057151
Short name T262
Test name
Test status
Simulation time 4361856275 ps
CPU time 13.09 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:20 PM PDT 24
Peak memory 209576 kb
Host smart-3b0431be-3b44-43d1-a8db-82cb170a3557
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522057151 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.522057151
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3221678998
Short name T584
Test name
Test status
Simulation time 6271996120 ps
CPU time 7.88 seconds
Started Aug 15 05:22:06 PM PDT 24
Finished Aug 15 05:22:14 PM PDT 24
Peak memory 201144 kb
Host smart-387a9079-62c5-40cc-87f0-98f55d350040
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221678998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.3221678998
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.802669080
Short name T148
Test name
Test status
Simulation time 2013547665 ps
CPU time 5.64 seconds
Started Aug 15 05:22:59 PM PDT 24
Finished Aug 15 05:23:05 PM PDT 24
Peak memory 201028 kb
Host smart-0dd51190-d146-4904-bab0-40535c4b74d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802669080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_tes
t.802669080
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.4280202249
Short name T324
Test name
Test status
Simulation time 3661729355 ps
CPU time 1.68 seconds
Started Aug 15 05:22:41 PM PDT 24
Finished Aug 15 05:22:43 PM PDT 24
Peak memory 201176 kb
Host smart-a25a55bb-e518-4acc-8682-78db392a8c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280202249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.4
280202249
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.3422312651
Short name T264
Test name
Test status
Simulation time 117888933692 ps
CPU time 63.51 seconds
Started Aug 15 05:22:41 PM PDT 24
Finished Aug 15 05:23:44 PM PDT 24
Peak memory 201216 kb
Host smart-b6d60329-4d41-4a6e-8bed-aba259da8801
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422312651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.3422312651
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2022292929
Short name T396
Test name
Test status
Simulation time 59805200613 ps
CPU time 34.02 seconds
Started Aug 15 05:22:59 PM PDT 24
Finished Aug 15 05:23:33 PM PDT 24
Peak memory 201268 kb
Host smart-e8a31d1d-9aa5-465e-9770-d749d73f69fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022292929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.2022292929
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3301623594
Short name T255
Test name
Test status
Simulation time 3182546898 ps
CPU time 2.52 seconds
Started Aug 15 05:23:01 PM PDT 24
Finished Aug 15 05:23:04 PM PDT 24
Peak memory 201100 kb
Host smart-0691503a-d48f-490c-baa0-5cce1dcd9872
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301623594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.3301623594
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.905470120
Short name T741
Test name
Test status
Simulation time 2612358870 ps
CPU time 7.71 seconds
Started Aug 15 05:22:42 PM PDT 24
Finished Aug 15 05:22:50 PM PDT 24
Peak memory 201128 kb
Host smart-0b3e8063-f44e-43b9-95de-da7159622d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905470120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.905470120
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.925177259
Short name T767
Test name
Test status
Simulation time 2489331051 ps
CPU time 2.09 seconds
Started Aug 15 05:22:58 PM PDT 24
Finished Aug 15 05:23:00 PM PDT 24
Peak memory 201108 kb
Host smart-82546193-6eb3-4775-bf95-504d818ba797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925177259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.925177259
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.1323688072
Short name T425
Test name
Test status
Simulation time 2084043634 ps
CPU time 3.67 seconds
Started Aug 15 05:22:42 PM PDT 24
Finished Aug 15 05:22:46 PM PDT 24
Peak memory 201000 kb
Host smart-b1091235-b576-409b-a754-9aa7a282a88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323688072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.1323688072
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.1123678196
Short name T66
Test name
Test status
Simulation time 2510537135 ps
CPU time 6.82 seconds
Started Aug 15 05:22:41 PM PDT 24
Finished Aug 15 05:22:48 PM PDT 24
Peak memory 201092 kb
Host smart-4743f04c-7828-4596-82ba-6b241b9085cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123678196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.1123678196
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.3106125997
Short name T687
Test name
Test status
Simulation time 2132709185 ps
CPU time 2.01 seconds
Started Aug 15 05:22:41 PM PDT 24
Finished Aug 15 05:22:43 PM PDT 24
Peak memory 201032 kb
Host smart-b5596b33-fe95-4439-99ac-348143280848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106125997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.3106125997
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1318945321
Short name T194
Test name
Test status
Simulation time 5199234785 ps
CPU time 11.26 seconds
Started Aug 15 05:22:44 PM PDT 24
Finished Aug 15 05:22:56 PM PDT 24
Peak memory 211180 kb
Host smart-5328cc74-f08a-4b14-8edb-fab349d1c219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318945321 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.1318945321
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2354110908
Short name T75
Test name
Test status
Simulation time 3817522103 ps
CPU time 6.46 seconds
Started Aug 15 05:22:40 PM PDT 24
Finished Aug 15 05:22:47 PM PDT 24
Peak memory 201092 kb
Host smart-afed64b6-7d3c-4bec-b998-d09f144d7edd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354110908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.2354110908
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.677417197
Short name T619
Test name
Test status
Simulation time 2014924135 ps
CPU time 5.77 seconds
Started Aug 15 05:22:51 PM PDT 24
Finished Aug 15 05:22:57 PM PDT 24
Peak memory 201092 kb
Host smart-50792034-3d61-43a9-bef8-8acc24c1b69c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677417197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_tes
t.677417197
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3034230059
Short name T625
Test name
Test status
Simulation time 3942105033 ps
CPU time 5.99 seconds
Started Aug 15 05:22:58 PM PDT 24
Finished Aug 15 05:23:04 PM PDT 24
Peak memory 201136 kb
Host smart-db96b665-ea80-4a02-bff3-9e171a369723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034230059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.3
034230059
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.737837406
Short name T760
Test name
Test status
Simulation time 116152947593 ps
CPU time 128.37 seconds
Started Aug 15 05:22:58 PM PDT 24
Finished Aug 15 05:25:06 PM PDT 24
Peak memory 201220 kb
Host smart-611f3d4d-b959-4e06-90f3-c52d5928a41e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737837406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_combo_detect.737837406
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3158799041
Short name T643
Test name
Test status
Simulation time 26151308475 ps
CPU time 13.51 seconds
Started Aug 15 05:23:10 PM PDT 24
Finished Aug 15 05:23:24 PM PDT 24
Peak memory 201212 kb
Host smart-6269ad0e-568c-44cc-8361-92515ae05e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158799041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.3158799041
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1722002168
Short name T155
Test name
Test status
Simulation time 2765963226 ps
CPU time 7.82 seconds
Started Aug 15 05:22:51 PM PDT 24
Finished Aug 15 05:22:59 PM PDT 24
Peak memory 201088 kb
Host smart-e7107c2a-bd13-4c19-83c4-801db775e6b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722002168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.1722002168
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.863483020
Short name T46
Test name
Test status
Simulation time 5123525566 ps
CPU time 4.26 seconds
Started Aug 15 05:22:40 PM PDT 24
Finished Aug 15 05:22:45 PM PDT 24
Peak memory 201080 kb
Host smart-f27e38ad-66cc-4fc1-9a79-7d1626ec3193
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863483020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctr
l_edge_detect.863483020
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.357707279
Short name T525
Test name
Test status
Simulation time 2610719749 ps
CPU time 7.21 seconds
Started Aug 15 05:22:55 PM PDT 24
Finished Aug 15 05:23:02 PM PDT 24
Peak memory 201112 kb
Host smart-b7001491-090e-463f-8bfe-5a23b54bfd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357707279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.357707279
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.4069504078
Short name T682
Test name
Test status
Simulation time 2469650084 ps
CPU time 8.1 seconds
Started Aug 15 05:22:57 PM PDT 24
Finished Aug 15 05:23:05 PM PDT 24
Peak memory 201108 kb
Host smart-d38827cb-7324-4e73-8e31-b7f3af300642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069504078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.4069504078
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.3068303287
Short name T594
Test name
Test status
Simulation time 2183759902 ps
CPU time 6.15 seconds
Started Aug 15 05:22:49 PM PDT 24
Finished Aug 15 05:22:55 PM PDT 24
Peak memory 201116 kb
Host smart-3b7c64b5-ff7a-437c-ac53-ec0e3dfcf700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068303287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.3068303287
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.3633189157
Short name T566
Test name
Test status
Simulation time 2517394775 ps
CPU time 3.87 seconds
Started Aug 15 05:22:48 PM PDT 24
Finished Aug 15 05:22:52 PM PDT 24
Peak memory 201092 kb
Host smart-fccad89d-faf0-4d8a-8d82-3d3788da036e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633189157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.3633189157
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.1387922740
Short name T544
Test name
Test status
Simulation time 2129784597 ps
CPU time 1.85 seconds
Started Aug 15 05:22:48 PM PDT 24
Finished Aug 15 05:22:50 PM PDT 24
Peak memory 201028 kb
Host smart-ccb28970-6e58-4d0d-9869-aa223fe27703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387922740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.1387922740
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.701638396
Short name T482
Test name
Test status
Simulation time 12262738271 ps
CPU time 6.91 seconds
Started Aug 15 05:22:44 PM PDT 24
Finished Aug 15 05:22:51 PM PDT 24
Peak memory 201088 kb
Host smart-1d48bd41-988a-4086-bb9b-2571d1ea1384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701638396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_st
ress_all.701638396
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3620311324
Short name T332
Test name
Test status
Simulation time 8762942701 ps
CPU time 7.46 seconds
Started Aug 15 05:22:40 PM PDT 24
Finished Aug 15 05:22:48 PM PDT 24
Peak memory 201068 kb
Host smart-9c71bca3-2dc3-491f-a350-70bf2e64be5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620311324 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.3620311324
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3590309640
Short name T102
Test name
Test status
Simulation time 6041862460 ps
CPU time 2.14 seconds
Started Aug 15 05:22:46 PM PDT 24
Finished Aug 15 05:22:48 PM PDT 24
Peak memory 201124 kb
Host smart-572755e6-b960-46b4-b936-714bd4f3276f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590309640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ultra_low_pwr.3590309640
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.1235741725
Short name T750
Test name
Test status
Simulation time 2012216772 ps
CPU time 5.76 seconds
Started Aug 15 05:22:42 PM PDT 24
Finished Aug 15 05:22:48 PM PDT 24
Peak memory 201068 kb
Host smart-2e560df8-f72f-4b2b-9444-d1dc4f38512c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235741725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.1235741725
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3428528591
Short name T554
Test name
Test status
Simulation time 3742777575 ps
CPU time 10.19 seconds
Started Aug 15 05:22:55 PM PDT 24
Finished Aug 15 05:23:05 PM PDT 24
Peak memory 201160 kb
Host smart-f41bd96e-7064-4b8c-af94-f15cf4bd7fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428528591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.3
428528591
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.3993681108
Short name T283
Test name
Test status
Simulation time 82896235933 ps
CPU time 203.84 seconds
Started Aug 15 05:23:07 PM PDT 24
Finished Aug 15 05:26:31 PM PDT 24
Peak memory 201212 kb
Host smart-c2feb4ca-d74e-48da-a4ca-341d3c39583c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993681108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.3993681108
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2368630884
Short name T390
Test name
Test status
Simulation time 88921643744 ps
CPU time 57.78 seconds
Started Aug 15 05:22:54 PM PDT 24
Finished Aug 15 05:23:52 PM PDT 24
Peak memory 201272 kb
Host smart-f984207d-c17b-4236-86a6-840d2aed5650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368630884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.2368630884
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1519291817
Short name T191
Test name
Test status
Simulation time 3693275857 ps
CPU time 10.31 seconds
Started Aug 15 05:22:40 PM PDT 24
Finished Aug 15 05:22:51 PM PDT 24
Peak memory 201072 kb
Host smart-132cb976-5cea-49c7-8304-00d6292d9ae6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519291817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.1519291817
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.3683530615
Short name T203
Test name
Test status
Simulation time 3693524466 ps
CPU time 1.73 seconds
Started Aug 15 05:22:48 PM PDT 24
Finished Aug 15 05:22:50 PM PDT 24
Peak memory 201088 kb
Host smart-3c9772e5-bb82-436c-aaca-bf5b950ea198
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683530615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.3683530615
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.24152984
Short name T517
Test name
Test status
Simulation time 2639190520 ps
CPU time 1.78 seconds
Started Aug 15 05:22:43 PM PDT 24
Finished Aug 15 05:22:45 PM PDT 24
Peak memory 201100 kb
Host smart-eed1a59e-0430-44b8-a69f-1610fd89427a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24152984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.24152984
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2482188287
Short name T668
Test name
Test status
Simulation time 2488812986 ps
CPU time 2.51 seconds
Started Aug 15 05:22:55 PM PDT 24
Finished Aug 15 05:22:58 PM PDT 24
Peak memory 201032 kb
Host smart-34089ffb-ed21-46d1-8881-6247b1cc3e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482188287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.2482188287
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.2027099922
Short name T543
Test name
Test status
Simulation time 2039508909 ps
CPU time 1.95 seconds
Started Aug 15 05:22:39 PM PDT 24
Finished Aug 15 05:22:41 PM PDT 24
Peak memory 201024 kb
Host smart-96e3c657-dea1-4168-bce0-3ff0221dae5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027099922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.2027099922
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2580030077
Short name T713
Test name
Test status
Simulation time 2514093176 ps
CPU time 7.52 seconds
Started Aug 15 05:22:50 PM PDT 24
Finished Aug 15 05:22:58 PM PDT 24
Peak memory 201040 kb
Host smart-185c7c87-aeba-4457-ad40-f4f014ca8f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580030077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2580030077
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.419711647
Short name T432
Test name
Test status
Simulation time 2117310776 ps
CPU time 3.14 seconds
Started Aug 15 05:23:08 PM PDT 24
Finished Aug 15 05:23:11 PM PDT 24
Peak memory 201032 kb
Host smart-fad66411-ebce-4ede-8907-191e5c171f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419711647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.419711647
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.944017790
Short name T530
Test name
Test status
Simulation time 7570033053 ps
CPU time 1.69 seconds
Started Aug 15 05:23:07 PM PDT 24
Finished Aug 15 05:23:09 PM PDT 24
Peak memory 201040 kb
Host smart-299519ad-b201-498d-bf80-f3de86c6586b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944017790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_st
ress_all.944017790
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3904851230
Short name T57
Test name
Test status
Simulation time 17786570412 ps
CPU time 10.13 seconds
Started Aug 15 05:22:52 PM PDT 24
Finished Aug 15 05:23:02 PM PDT 24
Peak memory 209604 kb
Host smart-739a4bd7-ec65-48ac-9f89-172fc9976afa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904851230 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.3904851230
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.681353378
Short name T418
Test name
Test status
Simulation time 244436394800 ps
CPU time 3.95 seconds
Started Aug 15 05:22:49 PM PDT 24
Finished Aug 15 05:22:53 PM PDT 24
Peak memory 201108 kb
Host smart-061281f1-71de-42cb-88aa-877de92dc696
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681353378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_ultra_low_pwr.681353378
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.2003945646
Short name T721
Test name
Test status
Simulation time 2049842311 ps
CPU time 1.42 seconds
Started Aug 15 05:22:44 PM PDT 24
Finished Aug 15 05:22:50 PM PDT 24
Peak memory 201136 kb
Host smart-abb58dea-ac27-4d3a-835d-ea04440adc72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003945646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.2003945646
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3503250967
Short name T154
Test name
Test status
Simulation time 127446681899 ps
CPU time 230.63 seconds
Started Aug 15 05:22:45 PM PDT 24
Finished Aug 15 05:26:36 PM PDT 24
Peak memory 201252 kb
Host smart-3824820c-d62b-4026-97ca-b5bb14526dd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503250967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.3503250967
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1173318302
Short name T404
Test name
Test status
Simulation time 106027305650 ps
CPU time 261.66 seconds
Started Aug 15 05:22:48 PM PDT 24
Finished Aug 15 05:27:10 PM PDT 24
Peak memory 201368 kb
Host smart-f0a8c9d7-9ef9-4be7-b858-4467d430e470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173318302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.1173318302
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1832108376
Short name T763
Test name
Test status
Simulation time 4522994289 ps
CPU time 3.16 seconds
Started Aug 15 05:22:55 PM PDT 24
Finished Aug 15 05:22:58 PM PDT 24
Peak memory 201084 kb
Host smart-d2de0159-23de-4a38-b0f0-ff6efba52b86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832108376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.1832108376
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.207555095
Short name T733
Test name
Test status
Simulation time 2627290277 ps
CPU time 2.16 seconds
Started Aug 15 05:23:11 PM PDT 24
Finished Aug 15 05:23:13 PM PDT 24
Peak memory 201028 kb
Host smart-103af0f6-1472-4115-9047-d9bb527e894d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207555095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.207555095
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.4126023131
Short name T140
Test name
Test status
Simulation time 2460813497 ps
CPU time 7.76 seconds
Started Aug 15 05:22:59 PM PDT 24
Finished Aug 15 05:23:07 PM PDT 24
Peak memory 201100 kb
Host smart-5ccc4501-4e96-4357-90f2-981f20f75ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126023131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.4126023131
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.3722824635
Short name T718
Test name
Test status
Simulation time 2021587648 ps
CPU time 2.71 seconds
Started Aug 15 05:22:48 PM PDT 24
Finished Aug 15 05:22:50 PM PDT 24
Peak memory 201048 kb
Host smart-78242d83-da8e-4563-9f11-dfd907ccd2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722824635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.3722824635
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2629314747
Short name T221
Test name
Test status
Simulation time 2508935951 ps
CPU time 7.36 seconds
Started Aug 15 05:22:59 PM PDT 24
Finished Aug 15 05:23:07 PM PDT 24
Peak memory 201132 kb
Host smart-9a88ac43-a87e-41bc-b157-3439c4b6abf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629314747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.2629314747
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.3929929178
Short name T6
Test name
Test status
Simulation time 2110097907 ps
CPU time 6.1 seconds
Started Aug 15 05:23:00 PM PDT 24
Finished Aug 15 05:23:06 PM PDT 24
Peak memory 200976 kb
Host smart-606756f7-cf8d-4f88-a899-ff3296d05f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929929178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.3929929178
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.2912433924
Short name T370
Test name
Test status
Simulation time 62686936220 ps
CPU time 155.65 seconds
Started Aug 15 05:22:52 PM PDT 24
Finished Aug 15 05:25:28 PM PDT 24
Peak memory 201144 kb
Host smart-ec51465d-cc14-4aef-b439-03e2a2c9615e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912433924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.2912433924
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.26849932
Short name T296
Test name
Test status
Simulation time 3974241776 ps
CPU time 10.67 seconds
Started Aug 15 05:22:57 PM PDT 24
Finished Aug 15 05:23:08 PM PDT 24
Peak memory 201212 kb
Host smart-0eb1c277-8629-48a3-b702-2f9479078e53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26849932 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.26849932
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1315947426
Short name T761
Test name
Test status
Simulation time 575607327435 ps
CPU time 142.21 seconds
Started Aug 15 05:22:54 PM PDT 24
Finished Aug 15 05:25:16 PM PDT 24
Peak memory 201128 kb
Host smart-2cdb03f4-3f4b-4b7f-a034-d8c7ede42e3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315947426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.1315947426
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.2821046132
Short name T211
Test name
Test status
Simulation time 2011460563 ps
CPU time 5.85 seconds
Started Aug 15 05:23:00 PM PDT 24
Finished Aug 15 05:23:06 PM PDT 24
Peak memory 201040 kb
Host smart-00b3637b-44b4-408e-8ba7-ea2b9cc0e734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821046132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.2821046132
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3488047810
Short name T133
Test name
Test status
Simulation time 3583003283 ps
CPU time 9.78 seconds
Started Aug 15 05:22:46 PM PDT 24
Finished Aug 15 05:22:56 PM PDT 24
Peak memory 201216 kb
Host smart-10bd8231-09c1-4ef5-874b-1cde0e9e75a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488047810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.3
488047810
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.4194280224
Short name T497
Test name
Test status
Simulation time 2996420268 ps
CPU time 4.25 seconds
Started Aug 15 05:22:53 PM PDT 24
Finished Aug 15 05:22:57 PM PDT 24
Peak memory 201128 kb
Host smart-cde805d2-7909-46a1-945a-93dee4a71611
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194280224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.4194280224
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.1196943773
Short name T199
Test name
Test status
Simulation time 2852145359 ps
CPU time 5.88 seconds
Started Aug 15 05:22:50 PM PDT 24
Finished Aug 15 05:22:56 PM PDT 24
Peak memory 201100 kb
Host smart-0c333175-a93c-48fa-97ae-8495621c65ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196943773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.1196943773
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.228722733
Short name T590
Test name
Test status
Simulation time 2607755262 ps
CPU time 7.05 seconds
Started Aug 15 05:22:43 PM PDT 24
Finished Aug 15 05:22:50 PM PDT 24
Peak memory 201124 kb
Host smart-6dbc30fd-7eb5-4686-9776-000da482d20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228722733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.228722733
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.2396176758
Short name T772
Test name
Test status
Simulation time 2504703251 ps
CPU time 1.42 seconds
Started Aug 15 05:22:56 PM PDT 24
Finished Aug 15 05:22:58 PM PDT 24
Peak memory 201128 kb
Host smart-ab484b41-af12-47ea-b080-a4ac9c7d2247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396176758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.2396176758
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.1183992535
Short name T502
Test name
Test status
Simulation time 2065173569 ps
CPU time 5.41 seconds
Started Aug 15 05:22:37 PM PDT 24
Finished Aug 15 05:22:43 PM PDT 24
Peak memory 201056 kb
Host smart-65455eca-2d59-43c7-9174-366a16897d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183992535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.1183992535
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.3525846209
Short name T688
Test name
Test status
Simulation time 2510848993 ps
CPU time 7.13 seconds
Started Aug 15 05:22:56 PM PDT 24
Finished Aug 15 05:23:04 PM PDT 24
Peak memory 201108 kb
Host smart-0e2ad5f5-3c2b-4c38-b8fc-4e6f247e2f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525846209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.3525846209
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.4142662766
Short name T5
Test name
Test status
Simulation time 2118171759 ps
CPU time 3.28 seconds
Started Aug 15 05:22:57 PM PDT 24
Finished Aug 15 05:23:00 PM PDT 24
Peak memory 201032 kb
Host smart-f9dd2905-9f6a-42a4-81da-35f9d409db44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142662766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.4142662766
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.1505861564
Short name T406
Test name
Test status
Simulation time 13293128838 ps
CPU time 6.05 seconds
Started Aug 15 05:22:49 PM PDT 24
Finished Aug 15 05:22:55 PM PDT 24
Peak memory 201140 kb
Host smart-7bfecc8d-5aea-4657-8669-9390f5b653f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505861564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.1505861564
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.4161251814
Short name T220
Test name
Test status
Simulation time 3005607986 ps
CPU time 8.7 seconds
Started Aug 15 05:22:57 PM PDT 24
Finished Aug 15 05:23:11 PM PDT 24
Peak memory 201256 kb
Host smart-4636335a-cb8d-4500-8163-6e686ce430bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161251814 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.4161251814
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2228010798
Short name T116
Test name
Test status
Simulation time 9556872067 ps
CPU time 1.29 seconds
Started Aug 15 05:22:51 PM PDT 24
Finished Aug 15 05:22:53 PM PDT 24
Peak memory 201024 kb
Host smart-e5feb98e-91b8-43f1-8692-6d2b796515ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228010798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.2228010798
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.1528174548
Short name T233
Test name
Test status
Simulation time 2014383697 ps
CPU time 5.47 seconds
Started Aug 15 05:23:09 PM PDT 24
Finished Aug 15 05:23:15 PM PDT 24
Peak memory 201120 kb
Host smart-6d05d6fa-60f5-4604-b448-b6da20e39363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528174548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.1528174548
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.4267991448
Short name T180
Test name
Test status
Simulation time 3295743055 ps
CPU time 7.62 seconds
Started Aug 15 05:23:06 PM PDT 24
Finished Aug 15 05:23:14 PM PDT 24
Peak memory 201124 kb
Host smart-2ebd6cab-fbda-4188-844b-da9da79c8631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267991448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.4
267991448
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3509486589
Short name T602
Test name
Test status
Simulation time 4132712125 ps
CPU time 3.38 seconds
Started Aug 15 05:22:54 PM PDT 24
Finished Aug 15 05:22:58 PM PDT 24
Peak memory 201128 kb
Host smart-76fba517-7ca9-44a8-a163-28e43cb4bb91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509486589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.3509486589
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.2600720658
Short name T42
Test name
Test status
Simulation time 4840773808 ps
CPU time 1.26 seconds
Started Aug 15 05:22:47 PM PDT 24
Finished Aug 15 05:22:49 PM PDT 24
Peak memory 201104 kb
Host smart-d4f0c6f0-ad9e-4310-9e05-1f89ab8c1540
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600720658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.2600720658
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1918544069
Short name T459
Test name
Test status
Simulation time 2619117935 ps
CPU time 4.14 seconds
Started Aug 15 05:22:42 PM PDT 24
Finished Aug 15 05:22:47 PM PDT 24
Peak memory 201080 kb
Host smart-0f4263f7-dbfc-47f6-a45d-2979b50c20aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918544069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.1918544069
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1970284628
Short name T465
Test name
Test status
Simulation time 2475053632 ps
CPU time 3.86 seconds
Started Aug 15 05:22:49 PM PDT 24
Finished Aug 15 05:22:53 PM PDT 24
Peak memory 201104 kb
Host smart-9b8f11a0-29cc-46a7-a9f0-2e3f9bdb7f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970284628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1970284628
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.3448007065
Short name T412
Test name
Test status
Simulation time 2098129343 ps
CPU time 2.08 seconds
Started Aug 15 05:22:46 PM PDT 24
Finished Aug 15 05:22:48 PM PDT 24
Peak memory 200972 kb
Host smart-3bd1cdba-1ba5-45e6-8927-921feb7dd1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448007065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.3448007065
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.3064517581
Short name T628
Test name
Test status
Simulation time 2512692798 ps
CPU time 7.26 seconds
Started Aug 15 05:23:00 PM PDT 24
Finished Aug 15 05:23:07 PM PDT 24
Peak memory 201112 kb
Host smart-5dcd9e14-1fdc-4bf5-ba05-b670d387e5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064517581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.3064517581
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.898682176
Short name T225
Test name
Test status
Simulation time 2128043993 ps
CPU time 1.91 seconds
Started Aug 15 05:22:56 PM PDT 24
Finished Aug 15 05:22:58 PM PDT 24
Peak memory 201024 kb
Host smart-3b944915-9c44-4838-9402-9f25f1ddeadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898682176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.898682176
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.3369417266
Short name T598
Test name
Test status
Simulation time 12225797114 ps
CPU time 15.28 seconds
Started Aug 15 05:23:12 PM PDT 24
Finished Aug 15 05:23:27 PM PDT 24
Peak memory 201108 kb
Host smart-345698eb-40bb-411e-98cd-92c7f1bca2a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369417266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.3369417266
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.249674339
Short name T336
Test name
Test status
Simulation time 5520714056 ps
CPU time 15.88 seconds
Started Aug 15 05:22:52 PM PDT 24
Finished Aug 15 05:23:08 PM PDT 24
Peak memory 209580 kb
Host smart-b44640db-fca5-4f77-8ec0-cb61ca07b962
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249674339 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.249674339
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2913318716
Short name T113
Test name
Test status
Simulation time 6046803395 ps
CPU time 2.44 seconds
Started Aug 15 05:23:03 PM PDT 24
Finished Aug 15 05:23:06 PM PDT 24
Peak memory 201132 kb
Host smart-a4b5c6ab-02d9-446f-ad24-9ce62ed71dc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913318716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.2913318716
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.1404256140
Short name T179
Test name
Test status
Simulation time 2010504505 ps
CPU time 5.47 seconds
Started Aug 15 05:22:42 PM PDT 24
Finished Aug 15 05:22:47 PM PDT 24
Peak memory 201048 kb
Host smart-2d94ab44-0cfe-41e3-9192-371a4b75430c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404256140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.1404256140
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.4211041076
Short name T522
Test name
Test status
Simulation time 3810102810 ps
CPU time 1.99 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:23:18 PM PDT 24
Peak memory 201124 kb
Host smart-e2a1ee33-b5b4-4ef6-9773-449bb4c832c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211041076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.4
211041076
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1947869706
Short name T398
Test name
Test status
Simulation time 67027297720 ps
CPU time 11.78 seconds
Started Aug 15 05:22:48 PM PDT 24
Finished Aug 15 05:23:00 PM PDT 24
Peak memory 201360 kb
Host smart-1b6c5f24-0a3d-48b9-9e06-5ca21e43ab81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947869706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.1947869706
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2409337709
Short name T580
Test name
Test status
Simulation time 4281709167 ps
CPU time 3.05 seconds
Started Aug 15 05:22:49 PM PDT 24
Finished Aug 15 05:22:52 PM PDT 24
Peak memory 199736 kb
Host smart-bb78a468-0310-4065-8f92-48118bc988d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409337709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.2409337709
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.711293700
Short name T223
Test name
Test status
Simulation time 3160165929 ps
CPU time 1.74 seconds
Started Aug 15 05:22:59 PM PDT 24
Finished Aug 15 05:23:01 PM PDT 24
Peak memory 201068 kb
Host smart-623ed969-f87d-4aa9-9311-5ccb69b8bf89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711293700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctr
l_edge_detect.711293700
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1397620475
Short name T664
Test name
Test status
Simulation time 2611925073 ps
CPU time 7.34 seconds
Started Aug 15 05:23:00 PM PDT 24
Finished Aug 15 05:23:08 PM PDT 24
Peak memory 201104 kb
Host smart-544de7f4-6a98-4b44-bb03-dc70d705b1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397620475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1397620475
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1742445420
Short name T556
Test name
Test status
Simulation time 2513754280 ps
CPU time 1.57 seconds
Started Aug 15 05:22:51 PM PDT 24
Finished Aug 15 05:22:53 PM PDT 24
Peak memory 201112 kb
Host smart-c0a79719-d47a-4064-bcb2-5aeb56996e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742445420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.1742445420
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3379024685
Short name T537
Test name
Test status
Simulation time 2121983109 ps
CPU time 5.83 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:23 PM PDT 24
Peak memory 200992 kb
Host smart-72ea98c1-e3d2-46be-94ff-470a4f635491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379024685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.3379024685
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.89812053
Short name T589
Test name
Test status
Simulation time 2511594596 ps
CPU time 7.11 seconds
Started Aug 15 05:23:09 PM PDT 24
Finished Aug 15 05:23:17 PM PDT 24
Peak memory 201124 kb
Host smart-f5d14d85-c4d9-444f-a4d3-2d5cc5b771ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89812053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.89812053
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.4255183597
Short name T226
Test name
Test status
Simulation time 2111123387 ps
CPU time 5.87 seconds
Started Aug 15 05:22:59 PM PDT 24
Finished Aug 15 05:23:05 PM PDT 24
Peak memory 201028 kb
Host smart-9d8e2cb6-66b2-4f27-83ea-cf13e78d1d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255183597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.4255183597
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.1545121113
Short name T349
Test name
Test status
Simulation time 8688573760 ps
CPU time 6.49 seconds
Started Aug 15 05:23:01 PM PDT 24
Finished Aug 15 05:23:08 PM PDT 24
Peak memory 201084 kb
Host smart-a475f637-0e74-4538-9f20-98a19025d124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545121113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.1545121113
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2489926672
Short name T204
Test name
Test status
Simulation time 694317498759 ps
CPU time 17.68 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:35 PM PDT 24
Peak memory 217832 kb
Host smart-5e473682-65e9-443c-ada3-df49384ba2d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489926672 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.2489926672
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.3592456050
Short name T112
Test name
Test status
Simulation time 5798586637 ps
CPU time 3.83 seconds
Started Aug 15 05:23:04 PM PDT 24
Finished Aug 15 05:23:08 PM PDT 24
Peak memory 201080 kb
Host smart-1b0b951f-9e7f-423b-ae7c-93c5d447582b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592456050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.3592456050
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.2602448492
Short name T636
Test name
Test status
Simulation time 2012955907 ps
CPU time 5.74 seconds
Started Aug 15 05:23:01 PM PDT 24
Finished Aug 15 05:23:07 PM PDT 24
Peak memory 201088 kb
Host smart-61705f04-5ec5-47b8-8f03-52420f1ba8bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602448492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.2602448492
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.626214715
Short name T701
Test name
Test status
Simulation time 3866364677 ps
CPU time 11.28 seconds
Started Aug 15 05:22:51 PM PDT 24
Finished Aug 15 05:23:02 PM PDT 24
Peak memory 201204 kb
Host smart-aae1b58e-34d4-4fab-a7b8-34c6b6ccb575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626214715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.626214715
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1487965019
Short name T217
Test name
Test status
Simulation time 138899673246 ps
CPU time 356.77 seconds
Started Aug 15 05:23:11 PM PDT 24
Finished Aug 15 05:29:08 PM PDT 24
Peak memory 201172 kb
Host smart-00010489-16c3-4fef-9631-39cbfed0d48f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487965019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.1487965019
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3200911839
Short name T93
Test name
Test status
Simulation time 51206154564 ps
CPU time 33.02 seconds
Started Aug 15 05:23:01 PM PDT 24
Finished Aug 15 05:23:34 PM PDT 24
Peak memory 201376 kb
Host smart-8488a152-8225-438d-ace8-a839a89a79f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200911839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.3200911839
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.877972611
Short name T697
Test name
Test status
Simulation time 4249048185 ps
CPU time 12.28 seconds
Started Aug 15 05:23:01 PM PDT 24
Finished Aug 15 05:23:13 PM PDT 24
Peak memory 201072 kb
Host smart-5b8146e3-9e60-4ad8-8e06-9065903ec15f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877972611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_ec_pwr_on_rst.877972611
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.1311122422
Short name T206
Test name
Test status
Simulation time 3946749589 ps
CPU time 0.99 seconds
Started Aug 15 05:22:50 PM PDT 24
Finished Aug 15 05:22:51 PM PDT 24
Peak memory 201064 kb
Host smart-6a344ddb-316f-4b4b-84d7-2e5570da88a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311122422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.1311122422
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.4217789567
Short name T494
Test name
Test status
Simulation time 2614678782 ps
CPU time 7.21 seconds
Started Aug 15 05:23:03 PM PDT 24
Finished Aug 15 05:23:11 PM PDT 24
Peak memory 201060 kb
Host smart-98b1ebdb-ed6d-4e7c-9f4a-4df852c86fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217789567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.4217789567
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.3167760448
Short name T458
Test name
Test status
Simulation time 2490145833 ps
CPU time 1.36 seconds
Started Aug 15 05:22:56 PM PDT 24
Finished Aug 15 05:22:58 PM PDT 24
Peak memory 201072 kb
Host smart-ffeb005c-090b-4311-b99b-90f755652223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167760448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.3167760448
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.660733691
Short name T473
Test name
Test status
Simulation time 2082150119 ps
CPU time 5.57 seconds
Started Aug 15 05:22:56 PM PDT 24
Finished Aug 15 05:23:02 PM PDT 24
Peak memory 201028 kb
Host smart-356f89cd-2bcb-4d2b-ae8b-c1eedce08154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660733691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.660733691
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.1360663449
Short name T637
Test name
Test status
Simulation time 2537252334 ps
CPU time 2.34 seconds
Started Aug 15 05:23:00 PM PDT 24
Finished Aug 15 05:23:02 PM PDT 24
Peak memory 201112 kb
Host smart-ca56f9b2-9c7a-4c18-a8cd-ae904a01d27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360663449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.1360663449
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.2993004276
Short name T755
Test name
Test status
Simulation time 2181514789 ps
CPU time 1.12 seconds
Started Aug 15 05:22:59 PM PDT 24
Finished Aug 15 05:23:01 PM PDT 24
Peak memory 201048 kb
Host smart-f11eacad-71c5-47c8-8ce7-7a594b082046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993004276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.2993004276
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.2213145511
Short name T531
Test name
Test status
Simulation time 14659178112 ps
CPU time 32.68 seconds
Started Aug 15 05:22:55 PM PDT 24
Finished Aug 15 05:23:28 PM PDT 24
Peak memory 201080 kb
Host smart-3dbb2816-2785-4364-bc27-212091abf722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213145511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.2213145511
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1393226027
Short name T317
Test name
Test status
Simulation time 11695402054 ps
CPU time 4.65 seconds
Started Aug 15 05:23:04 PM PDT 24
Finished Aug 15 05:23:09 PM PDT 24
Peak memory 201400 kb
Host smart-a0e8b181-a2af-4cc2-a567-6b483f7a9810
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393226027 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.1393226027
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1667253895
Short name T538
Test name
Test status
Simulation time 6923646456 ps
CPU time 7.57 seconds
Started Aug 15 05:22:50 PM PDT 24
Finished Aug 15 05:22:58 PM PDT 24
Peak memory 201152 kb
Host smart-f59f0b08-6bad-4459-bf62-1d55a37e8906
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667253895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.1667253895
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.4050638919
Short name T610
Test name
Test status
Simulation time 2038638148 ps
CPU time 1.73 seconds
Started Aug 15 05:23:05 PM PDT 24
Finished Aug 15 05:23:07 PM PDT 24
Peak memory 200972 kb
Host smart-615aa713-e32f-494a-b6b6-fc1e88b7162e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050638919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.4050638919
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2856863056
Short name T539
Test name
Test status
Simulation time 3158563789 ps
CPU time 8.84 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:23:24 PM PDT 24
Peak memory 201124 kb
Host smart-3b5b6c31-de22-452d-bbab-4bc86d4b7693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856863056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.2
856863056
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.3041609168
Short name T588
Test name
Test status
Simulation time 63698914464 ps
CPU time 81.9 seconds
Started Aug 15 05:23:01 PM PDT 24
Finished Aug 15 05:24:23 PM PDT 24
Peak memory 201236 kb
Host smart-0f226f0c-5190-4d65-b3c5-5227abc7f6d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041609168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.3041609168
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.580739860
Short name T477
Test name
Test status
Simulation time 3092623754 ps
CPU time 8.67 seconds
Started Aug 15 05:22:48 PM PDT 24
Finished Aug 15 05:22:57 PM PDT 24
Peak memory 199740 kb
Host smart-a83fd09a-d51b-476c-b7cd-a54df6d3b62d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580739860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_ec_pwr_on_rst.580739860
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.3836464725
Short name T172
Test name
Test status
Simulation time 3883230194 ps
CPU time 1.78 seconds
Started Aug 15 05:22:57 PM PDT 24
Finished Aug 15 05:22:59 PM PDT 24
Peak memory 201088 kb
Host smart-08b6f65d-1f15-4863-8723-f052c4b3865f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836464725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.3836464725
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2061158319
Short name T426
Test name
Test status
Simulation time 2611758871 ps
CPU time 7.18 seconds
Started Aug 15 05:22:59 PM PDT 24
Finished Aug 15 05:23:07 PM PDT 24
Peak memory 201112 kb
Host smart-52d3c161-2493-4f56-a471-d4751af1cc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061158319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.2061158319
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.1522680418
Short name T84
Test name
Test status
Simulation time 2497353809 ps
CPU time 2.17 seconds
Started Aug 15 05:22:49 PM PDT 24
Finished Aug 15 05:22:51 PM PDT 24
Peak memory 199752 kb
Host smart-df7de531-4397-4945-9ee6-0b5877c3a41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522680418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.1522680418
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.2809502968
Short name T690
Test name
Test status
Simulation time 2085435164 ps
CPU time 1.34 seconds
Started Aug 15 05:22:55 PM PDT 24
Finished Aug 15 05:22:56 PM PDT 24
Peak memory 200988 kb
Host smart-a8ceebc7-d017-4ab4-ba74-ca69d7e6803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809502968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2809502968
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.2547678780
Short name T647
Test name
Test status
Simulation time 2511390953 ps
CPU time 6.53 seconds
Started Aug 15 05:23:02 PM PDT 24
Finished Aug 15 05:23:09 PM PDT 24
Peak memory 201080 kb
Host smart-9e5e10bb-25e3-44a0-b52d-fdb0bfc1bfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547678780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.2547678780
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.4189522549
Short name T709
Test name
Test status
Simulation time 2132199621 ps
CPU time 1.92 seconds
Started Aug 15 05:23:05 PM PDT 24
Finished Aug 15 05:23:07 PM PDT 24
Peak memory 200996 kb
Host smart-7b39021e-f4fa-42e3-bdbe-b3cf18736bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189522549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.4189522549
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3265693705
Short name T242
Test name
Test status
Simulation time 5442769545 ps
CPU time 15.86 seconds
Started Aug 15 05:23:13 PM PDT 24
Finished Aug 15 05:23:29 PM PDT 24
Peak memory 209536 kb
Host smart-943d088d-61e6-4dd4-b64f-2e42db3572e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265693705 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.3265693705
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1474554316
Short name T9
Test name
Test status
Simulation time 7257706125 ps
CPU time 7.03 seconds
Started Aug 15 05:22:56 PM PDT 24
Finished Aug 15 05:23:04 PM PDT 24
Peak memory 201052 kb
Host smart-6eeb9f39-490f-4200-bcf5-39cb880393c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474554316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.1474554316
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.3010652690
Short name T62
Test name
Test status
Simulation time 2027812497 ps
CPU time 1.89 seconds
Started Aug 15 05:23:13 PM PDT 24
Finished Aug 15 05:23:15 PM PDT 24
Peak memory 201340 kb
Host smart-404262c5-7779-4c31-b613-cf09a1be4d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010652690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.3010652690
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3284581486
Short name T200
Test name
Test status
Simulation time 3356493388 ps
CPU time 9.35 seconds
Started Aug 15 05:23:00 PM PDT 24
Finished Aug 15 05:23:10 PM PDT 24
Peak memory 201176 kb
Host smart-e31a9a6b-649f-4623-86ba-b7ce6a4da9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284581486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.3
284581486
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.857748482
Short name T373
Test name
Test status
Simulation time 87055827481 ps
CPU time 224.2 seconds
Started Aug 15 05:23:09 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 201152 kb
Host smart-4edc53bc-983d-4010-af0c-97f68783de1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857748482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_combo_detect.857748482
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.4054102609
Short name T416
Test name
Test status
Simulation time 33351660581 ps
CPU time 14.29 seconds
Started Aug 15 05:22:56 PM PDT 24
Finished Aug 15 05:23:10 PM PDT 24
Peak memory 201348 kb
Host smart-733b7268-cd94-4b36-93c5-7b8413d2632c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054102609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.4054102609
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.544887906
Short name T778
Test name
Test status
Simulation time 3025644220 ps
CPU time 8.85 seconds
Started Aug 15 05:23:11 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 201120 kb
Host smart-7cbd60d7-518a-4dd6-8e97-26e167ec4eb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544887906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_ec_pwr_on_rst.544887906
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.1460082791
Short name T231
Test name
Test status
Simulation time 4522573753 ps
CPU time 2.29 seconds
Started Aug 15 05:23:02 PM PDT 24
Finished Aug 15 05:23:04 PM PDT 24
Peak memory 201048 kb
Host smart-a5568c81-4fe6-4ec0-8596-01922c06f4aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460082791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.1460082791
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2842939125
Short name T266
Test name
Test status
Simulation time 2631514123 ps
CPU time 2.5 seconds
Started Aug 15 05:22:59 PM PDT 24
Finished Aug 15 05:23:02 PM PDT 24
Peak memory 201088 kb
Host smart-4b599184-d76c-4644-84d1-c523ca211b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842939125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.2842939125
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.3306081033
Short name T779
Test name
Test status
Simulation time 2477914921 ps
CPU time 2.39 seconds
Started Aug 15 05:23:13 PM PDT 24
Finished Aug 15 05:23:15 PM PDT 24
Peak memory 201052 kb
Host smart-c94a2f65-30a0-46b8-959c-b3968ff46f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306081033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.3306081033
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.649840963
Short name T347
Test name
Test status
Simulation time 2086153162 ps
CPU time 5.57 seconds
Started Aug 15 05:23:05 PM PDT 24
Finished Aug 15 05:23:11 PM PDT 24
Peak memory 201044 kb
Host smart-6ecc5433-4d29-47ab-a8ac-e9d7714c23a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649840963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.649840963
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3400181380
Short name T479
Test name
Test status
Simulation time 2535763109 ps
CPU time 2.3 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:23:18 PM PDT 24
Peak memory 201052 kb
Host smart-70c2c235-024d-4f77-a902-76da91319336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400181380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3400181380
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.1910559641
Short name T674
Test name
Test status
Simulation time 2116055745 ps
CPU time 3.24 seconds
Started Aug 15 05:22:51 PM PDT 24
Finished Aug 15 05:22:54 PM PDT 24
Peak memory 200968 kb
Host smart-85a42cd5-5ac5-4cec-9271-2643ee0efc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910559641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.1910559641
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.4216023401
Short name T583
Test name
Test status
Simulation time 4457384472 ps
CPU time 6.4 seconds
Started Aug 15 05:23:11 PM PDT 24
Finished Aug 15 05:23:17 PM PDT 24
Peak memory 201112 kb
Host smart-64022409-7cb9-4130-862f-ee7222743df6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216023401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.4216023401
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.408962775
Short name T513
Test name
Test status
Simulation time 3079057652 ps
CPU time 2.54 seconds
Started Aug 15 05:22:05 PM PDT 24
Finished Aug 15 05:22:08 PM PDT 24
Peak memory 201176 kb
Host smart-1464240b-5b06-4bed-a8e4-ad61dbdfdafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408962775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.408962775
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.977919947
Short name T37
Test name
Test status
Simulation time 113635590210 ps
CPU time 303.89 seconds
Started Aug 15 05:22:05 PM PDT 24
Finished Aug 15 05:27:10 PM PDT 24
Peak memory 201204 kb
Host smart-7d61a5f6-7b4f-4c85-a323-99451f51b205
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977919947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_combo_detect.977919947
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.4080118166
Short name T553
Test name
Test status
Simulation time 2413224154 ps
CPU time 2.13 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:09 PM PDT 24
Peak memory 201100 kb
Host smart-707d3f90-0387-434c-bdf5-a430c2ccbb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080118166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.4080118166
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3199012402
Short name T271
Test name
Test status
Simulation time 2315700939 ps
CPU time 2.75 seconds
Started Aug 15 05:21:59 PM PDT 24
Finished Aug 15 05:22:02 PM PDT 24
Peak memory 201120 kb
Host smart-eeb0da1c-da66-42b4-80d6-15e14d5fa41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199012402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3199012402
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.947647927
Short name T560
Test name
Test status
Simulation time 3575987294 ps
CPU time 10.05 seconds
Started Aug 15 05:22:08 PM PDT 24
Finished Aug 15 05:22:18 PM PDT 24
Peak memory 201096 kb
Host smart-032123e1-48fc-4140-be38-a5da4dd4a72b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947647927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_ec_pwr_on_rst.947647927
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.354146211
Short name T8
Test name
Test status
Simulation time 3062952536 ps
CPU time 7.25 seconds
Started Aug 15 05:22:09 PM PDT 24
Finished Aug 15 05:22:16 PM PDT 24
Peak memory 201040 kb
Host smart-142f9afe-2709-463e-bd5f-877a78886032
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354146211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_edge_detect.354146211
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2973297575
Short name T516
Test name
Test status
Simulation time 2626642307 ps
CPU time 2.38 seconds
Started Aug 15 05:22:05 PM PDT 24
Finished Aug 15 05:22:08 PM PDT 24
Peak memory 201108 kb
Host smart-820286a3-502a-456e-af85-e54465ca5cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973297575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.2973297575
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.3246943904
Short name T634
Test name
Test status
Simulation time 2460915236 ps
CPU time 6.75 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:14 PM PDT 24
Peak memory 201060 kb
Host smart-34eb117a-627d-4504-abcf-1230f8d77c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246943904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.3246943904
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.2517347369
Short name T562
Test name
Test status
Simulation time 2090221673 ps
CPU time 6.05 seconds
Started Aug 15 05:22:05 PM PDT 24
Finished Aug 15 05:22:11 PM PDT 24
Peak memory 200996 kb
Host smart-6d953554-6edc-47f4-aeea-a8c5e890fcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517347369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.2517347369
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.2668885549
Short name T694
Test name
Test status
Simulation time 2529102808 ps
CPU time 2.55 seconds
Started Aug 15 05:22:12 PM PDT 24
Finished Aug 15 05:22:15 PM PDT 24
Peak memory 201112 kb
Host smart-09411e1d-1476-4ddc-978d-88cf1937b073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668885549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.2668885549
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.946403121
Short name T295
Test name
Test status
Simulation time 43121149143 ps
CPU time 20.69 seconds
Started Aug 15 05:22:08 PM PDT 24
Finished Aug 15 05:22:29 PM PDT 24
Peak memory 220964 kb
Host smart-78be5635-98cb-411b-8711-9c840052a100
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946403121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.946403121
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.1978635274
Short name T563
Test name
Test status
Simulation time 2116975915 ps
CPU time 3.49 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:11 PM PDT 24
Peak memory 200968 kb
Host smart-ffa2d9f1-dbea-4588-a5f1-28163b7cf004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978635274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.1978635274
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.934395983
Short name T511
Test name
Test status
Simulation time 6907713508 ps
CPU time 17.16 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:25 PM PDT 24
Peak memory 201080 kb
Host smart-758cdef1-2a3f-4229-9fad-ab84f172071e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934395983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_str
ess_all.934395983
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1275820208
Short name T740
Test name
Test status
Simulation time 6279742809 ps
CPU time 12.61 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:20 PM PDT 24
Peak memory 209592 kb
Host smart-11ffa2fb-b7b1-4c7f-b17a-94f260f1bfbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275820208 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.1275820208
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.1397023171
Short name T452
Test name
Test status
Simulation time 2096451216 ps
CPU time 1.07 seconds
Started Aug 15 05:23:01 PM PDT 24
Finished Aug 15 05:23:02 PM PDT 24
Peak memory 201036 kb
Host smart-414b8cd9-b6b2-4faf-9c53-425b4a833f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397023171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.1397023171
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.524712485
Short name T568
Test name
Test status
Simulation time 3196196350 ps
CPU time 8.54 seconds
Started Aug 15 05:23:05 PM PDT 24
Finished Aug 15 05:23:13 PM PDT 24
Peak memory 201196 kb
Host smart-0dad2c2d-69f9-4a8e-8190-72efd35d8f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524712485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.524712485
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.1658808227
Short name T378
Test name
Test status
Simulation time 131517465113 ps
CPU time 283.46 seconds
Started Aug 15 05:23:02 PM PDT 24
Finished Aug 15 05:27:46 PM PDT 24
Peak memory 201268 kb
Host smart-be5043b0-8680-4e0d-af3a-490fb474a671
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658808227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.1658808227
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2523652382
Short name T586
Test name
Test status
Simulation time 21348536211 ps
CPU time 13.84 seconds
Started Aug 15 05:23:11 PM PDT 24
Finished Aug 15 05:23:25 PM PDT 24
Peak memory 201296 kb
Host smart-b3515551-ab29-430a-902a-f82ee2daf4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523652382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.2523652382
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3854515354
Short name T209
Test name
Test status
Simulation time 4357496786 ps
CPU time 3.34 seconds
Started Aug 15 05:23:01 PM PDT 24
Finished Aug 15 05:23:04 PM PDT 24
Peak memory 201088 kb
Host smart-03890b12-563b-44a6-b678-f26604391929
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854515354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.3854515354
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.1096315985
Short name T648
Test name
Test status
Simulation time 3373624454 ps
CPU time 7.82 seconds
Started Aug 15 05:23:11 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201088 kb
Host smart-38fb7f84-d9e1-43a4-84e8-74fe31fd460f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096315985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.1096315985
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.4115775965
Short name T443
Test name
Test status
Simulation time 2628466580 ps
CPU time 2.3 seconds
Started Aug 15 05:23:04 PM PDT 24
Finished Aug 15 05:23:06 PM PDT 24
Peak memory 201024 kb
Host smart-81683eb1-896e-46b3-bef9-f5a38d0b2a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115775965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.4115775965
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.3306121810
Short name T142
Test name
Test status
Simulation time 2475511485 ps
CPU time 6.13 seconds
Started Aug 15 05:23:05 PM PDT 24
Finished Aug 15 05:23:11 PM PDT 24
Peak memory 201136 kb
Host smart-934c98b4-5acb-4d94-b072-a25e9f8478c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306121810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.3306121810
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.2945911940
Short name T657
Test name
Test status
Simulation time 2180237420 ps
CPU time 2.01 seconds
Started Aug 15 05:23:08 PM PDT 24
Finished Aug 15 05:23:10 PM PDT 24
Peak memory 201064 kb
Host smart-a4e96917-aabe-44b4-96f9-c7ccf92d91ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945911940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.2945911940
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.352534344
Short name T734
Test name
Test status
Simulation time 2508620738 ps
CPU time 6.57 seconds
Started Aug 15 05:23:01 PM PDT 24
Finished Aug 15 05:23:08 PM PDT 24
Peak memory 201108 kb
Host smart-27e55f2b-e823-46ce-9a48-6ae635f2a33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352534344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.352534344
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.3158737738
Short name T182
Test name
Test status
Simulation time 2113539577 ps
CPU time 5.54 seconds
Started Aug 15 05:23:06 PM PDT 24
Finished Aug 15 05:23:11 PM PDT 24
Peak memory 200992 kb
Host smart-10c3cb29-33fd-4ac9-9d2f-74b1de31cfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158737738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.3158737738
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.2845580360
Short name T765
Test name
Test status
Simulation time 9998412527 ps
CPU time 5.91 seconds
Started Aug 15 05:23:11 PM PDT 24
Finished Aug 15 05:23:17 PM PDT 24
Peak memory 201160 kb
Host smart-5e0f6192-7036-4861-a3a7-d889fd242df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845580360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.2845580360
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.708662001
Short name T319
Test name
Test status
Simulation time 8899887045 ps
CPU time 6.94 seconds
Started Aug 15 05:22:57 PM PDT 24
Finished Aug 15 05:23:04 PM PDT 24
Peak memory 209616 kb
Host smart-34a6b23e-aa34-40f1-bfb0-06af1b92e243
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708662001 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.708662001
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2125759074
Short name T587
Test name
Test status
Simulation time 8712846529 ps
CPU time 1.19 seconds
Started Aug 15 05:23:07 PM PDT 24
Finished Aug 15 05:23:08 PM PDT 24
Peak memory 201112 kb
Host smart-24a218fe-f63f-4a94-bb1a-123615a76f8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125759074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.2125759074
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.4237341507
Short name T559
Test name
Test status
Simulation time 2015379833 ps
CPU time 5.73 seconds
Started Aug 15 05:23:02 PM PDT 24
Finished Aug 15 05:23:08 PM PDT 24
Peak memory 201100 kb
Host smart-58e38b23-a579-4b65-b080-9095ea4a1be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237341507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.4237341507
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.2661482809
Short name T579
Test name
Test status
Simulation time 3380304698 ps
CPU time 2.83 seconds
Started Aug 15 05:23:04 PM PDT 24
Finished Aug 15 05:23:07 PM PDT 24
Peak memory 201148 kb
Host smart-516eef70-8904-4a7e-942d-2006627b7229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661482809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.2
661482809
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.116741941
Short name T38
Test name
Test status
Simulation time 185867153205 ps
CPU time 115.27 seconds
Started Aug 15 05:23:00 PM PDT 24
Finished Aug 15 05:24:55 PM PDT 24
Peak memory 201264 kb
Host smart-a41b0478-d925-4a42-a4de-3e7e3da20dbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116741941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_combo_detect.116741941
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2268663907
Short name T400
Test name
Test status
Simulation time 56425943938 ps
CPU time 37.79 seconds
Started Aug 15 05:23:12 PM PDT 24
Finished Aug 15 05:23:50 PM PDT 24
Peak memory 201372 kb
Host smart-1c5c7537-aed7-4e72-af17-86abc5845e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268663907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.2268663907
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3824639170
Short name T729
Test name
Test status
Simulation time 611275784468 ps
CPU time 1498.08 seconds
Started Aug 15 05:23:02 PM PDT 24
Finished Aug 15 05:48:00 PM PDT 24
Peak memory 201068 kb
Host smart-8e8ec3bd-23a6-4259-96ae-d4a0c247fd7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824639170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.3824639170
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.3367265745
Short name T207
Test name
Test status
Simulation time 3305963126 ps
CPU time 4.21 seconds
Started Aug 15 05:23:02 PM PDT 24
Finished Aug 15 05:23:06 PM PDT 24
Peak memory 201328 kb
Host smart-51b1aba5-2384-4872-9ced-9fdc3bad7798
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367265745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.3367265745
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1012792415
Short name T137
Test name
Test status
Simulation time 2620281459 ps
CPU time 4.06 seconds
Started Aug 15 05:23:03 PM PDT 24
Finished Aug 15 05:23:07 PM PDT 24
Peak memory 201072 kb
Host smart-190088b9-861e-4fab-9530-84e77f8db74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012792415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.1012792415
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1029884161
Short name T351
Test name
Test status
Simulation time 2465323846 ps
CPU time 2.09 seconds
Started Aug 15 05:23:08 PM PDT 24
Finished Aug 15 05:23:10 PM PDT 24
Peak memory 201064 kb
Host smart-94e08c2b-20d9-4a51-bde0-b2aeccdf2068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029884161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1029884161
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.986909651
Short name T739
Test name
Test status
Simulation time 2230011613 ps
CPU time 6.86 seconds
Started Aug 15 05:23:03 PM PDT 24
Finished Aug 15 05:23:11 PM PDT 24
Peak memory 201052 kb
Host smart-5d363534-c48f-470e-adbb-aa9759fcb160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986909651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.986909651
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.1153000928
Short name T708
Test name
Test status
Simulation time 2518902465 ps
CPU time 3.6 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201108 kb
Host smart-4819f051-6049-4aba-813b-7af856c00a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153000928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.1153000928
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.3811880875
Short name T698
Test name
Test status
Simulation time 2123267088 ps
CPU time 2.07 seconds
Started Aug 15 05:23:08 PM PDT 24
Finished Aug 15 05:23:10 PM PDT 24
Peak memory 201004 kb
Host smart-05daa853-492b-4ec2-ab53-b01055e820d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811880875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.3811880875
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.3135536506
Short name T650
Test name
Test status
Simulation time 9189187254 ps
CPU time 8.47 seconds
Started Aug 15 05:23:13 PM PDT 24
Finished Aug 15 05:23:22 PM PDT 24
Peak memory 201100 kb
Host smart-24e80d97-824e-449c-85a0-6b2c7e1c75a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135536506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.3135536506
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1110249643
Short name T136
Test name
Test status
Simulation time 4999901390 ps
CPU time 7.26 seconds
Started Aug 15 05:23:12 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 209420 kb
Host smart-b8d166b8-1fdb-4b74-a5f9-54f45bcea7e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110249643 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.1110249643
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2275415952
Short name T751
Test name
Test status
Simulation time 3527611336 ps
CPU time 5.68 seconds
Started Aug 15 05:23:02 PM PDT 24
Finished Aug 15 05:23:08 PM PDT 24
Peak memory 201020 kb
Host smart-0d9c8664-2a52-4647-a00c-16104a6f071a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275415952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.2275415952
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.585740120
Short name T679
Test name
Test status
Simulation time 2016943553 ps
CPU time 3.24 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 201096 kb
Host smart-6bf487f8-2987-4734-b88d-e231a7b3c398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585740120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_tes
t.585740120
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2879584451
Short name T487
Test name
Test status
Simulation time 3289793534 ps
CPU time 2.56 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:21 PM PDT 24
Peak memory 201204 kb
Host smart-19526da4-81ed-4994-a079-4bbd117f9067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879584451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.2
879584451
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.1024474403
Short name T2
Test name
Test status
Simulation time 142438236432 ps
CPU time 81.47 seconds
Started Aug 15 05:23:08 PM PDT 24
Finished Aug 15 05:24:30 PM PDT 24
Peak memory 201244 kb
Host smart-f8428754-a2e2-4537-b063-292ee806c52d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024474403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.1024474403
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.4173655045
Short name T51
Test name
Test status
Simulation time 86533950498 ps
CPU time 54.58 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:24:12 PM PDT 24
Peak memory 201400 kb
Host smart-01532b31-5e3a-4a2a-81f9-8c7c9176e2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173655045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.4173655045
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2104397627
Short name T475
Test name
Test status
Simulation time 3987287996 ps
CPU time 7.95 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:23:23 PM PDT 24
Peak memory 201088 kb
Host smart-00e945de-b692-44e6-aa32-e82a686659cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104397627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.2104397627
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.3814903642
Short name T10
Test name
Test status
Simulation time 3211384378 ps
CPU time 9.16 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:26 PM PDT 24
Peak memory 200936 kb
Host smart-a6d74a55-0481-4e18-8c71-1197580f7e0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814903642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.3814903642
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.2362979125
Short name T601
Test name
Test status
Simulation time 2623717888 ps
CPU time 2.23 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201060 kb
Host smart-553ba381-65f9-4686-9443-b33595f26e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362979125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.2362979125
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.1028449206
Short name T222
Test name
Test status
Simulation time 2462846612 ps
CPU time 3.85 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 201100 kb
Host smart-09839415-b472-4647-a0dc-3481af0e5b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028449206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.1028449206
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.3749076470
Short name T338
Test name
Test status
Simulation time 2197235372 ps
CPU time 5.38 seconds
Started Aug 15 05:23:09 PM PDT 24
Finished Aug 15 05:23:15 PM PDT 24
Peak memory 201040 kb
Host smart-d691c2f7-de66-4292-9bcd-a2d237578331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749076470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.3749076470
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.2325488117
Short name T759
Test name
Test status
Simulation time 2511085429 ps
CPU time 7.24 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:24 PM PDT 24
Peak memory 201088 kb
Host smart-8fbdb62b-6a57-4660-9d48-2e5d7ce52b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325488117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.2325488117
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.3008368296
Short name T468
Test name
Test status
Simulation time 2129885809 ps
CPU time 1.71 seconds
Started Aug 15 05:23:04 PM PDT 24
Finished Aug 15 05:23:05 PM PDT 24
Peak memory 200996 kb
Host smart-b52c6987-8f12-4a1a-98e4-5824f5ee711b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008368296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.3008368296
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.2392063119
Short name T175
Test name
Test status
Simulation time 10120355418 ps
CPU time 25.6 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:23:41 PM PDT 24
Peak memory 201152 kb
Host smart-65da029a-354c-464f-ad29-42cec9aea1d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392063119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.2392063119
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.239872304
Short name T143
Test name
Test status
Simulation time 13655763575 ps
CPU time 9.52 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:26 PM PDT 24
Peak memory 209604 kb
Host smart-d2727ed6-2fb6-4f21-ab61-f97b7f98da3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239872304 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.239872304
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1456872907
Short name T101
Test name
Test status
Simulation time 9797991012 ps
CPU time 2.16 seconds
Started Aug 15 05:23:23 PM PDT 24
Finished Aug 15 05:23:25 PM PDT 24
Peak memory 201044 kb
Host smart-2f831b53-dd39-4372-86b3-92982a4857cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456872907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.1456872907
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.1132295033
Short name T462
Test name
Test status
Simulation time 2093320268 ps
CPU time 1.2 seconds
Started Aug 15 05:23:14 PM PDT 24
Finished Aug 15 05:23:15 PM PDT 24
Peak memory 201084 kb
Host smart-586b1843-d5c5-4f6b-a6f3-bf6f2be8bc5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132295033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.1132295033
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2278418182
Short name T218
Test name
Test status
Simulation time 3219129511 ps
CPU time 5.19 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:23 PM PDT 24
Peak memory 201216 kb
Host smart-5e1e6a40-9fac-473c-b97a-c244d248b752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278418182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.2
278418182
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3220157170
Short name T748
Test name
Test status
Simulation time 3867123531 ps
CPU time 10.78 seconds
Started Aug 15 05:23:10 PM PDT 24
Finished Aug 15 05:23:21 PM PDT 24
Peak memory 201104 kb
Host smart-5a9e8fc4-d8ae-496b-ad4a-f2ea5c7ca070
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220157170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.3220157170
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.2230734716
Short name T167
Test name
Test status
Simulation time 2926003033 ps
CPU time 6.27 seconds
Started Aug 15 05:23:04 PM PDT 24
Finished Aug 15 05:23:10 PM PDT 24
Peak memory 201084 kb
Host smart-9eff813a-bec3-4f39-be5a-5f59a2343d0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230734716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.2230734716
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.4287935241
Short name T489
Test name
Test status
Simulation time 2734397544 ps
CPU time 1.08 seconds
Started Aug 15 05:23:11 PM PDT 24
Finished Aug 15 05:23:12 PM PDT 24
Peak memory 201108 kb
Host smart-5ab5246e-686e-469c-9bbc-bfd0d0bf72b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287935241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.4287935241
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1608086711
Short name T696
Test name
Test status
Simulation time 2467278558 ps
CPU time 2.14 seconds
Started Aug 15 05:23:04 PM PDT 24
Finished Aug 15 05:23:06 PM PDT 24
Peak memory 201100 kb
Host smart-b4daf72b-cf1f-43e6-a9f2-f6be394a0e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608086711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.1608086711
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.348714980
Short name T593
Test name
Test status
Simulation time 2154368389 ps
CPU time 2.02 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:18 PM PDT 24
Peak memory 201068 kb
Host smart-e6423ee0-27ec-44aa-b925-f268e1417820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348714980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.348714980
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.3649718855
Short name T608
Test name
Test status
Simulation time 2525252045 ps
CPU time 2.37 seconds
Started Aug 15 05:23:09 PM PDT 24
Finished Aug 15 05:23:12 PM PDT 24
Peak memory 201100 kb
Host smart-46b6656e-cc57-49b4-bbd5-62c0c66b4d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649718855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.3649718855
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.2301939480
Short name T146
Test name
Test status
Simulation time 2112504279 ps
CPU time 4.31 seconds
Started Aug 15 05:23:02 PM PDT 24
Finished Aug 15 05:23:07 PM PDT 24
Peak memory 201064 kb
Host smart-f87278a1-edf4-4c71-bc2b-125d1c91facb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301939480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.2301939480
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.3201429094
Short name T59
Test name
Test status
Simulation time 276592178709 ps
CPU time 173.33 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:26:09 PM PDT 24
Peak memory 201176 kb
Host smart-97a28d55-60e2-4c11-b91a-2bacacf0145d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201429094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.3201429094
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.1086640130
Short name T754
Test name
Test status
Simulation time 3944234225 ps
CPU time 6.92 seconds
Started Aug 15 05:23:11 PM PDT 24
Finished Aug 15 05:23:18 PM PDT 24
Peak memory 201380 kb
Host smart-d7756e5b-6b9c-4f75-8fe8-01f97b5bc71d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086640130 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.1086640130
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.3142069279
Short name T557
Test name
Test status
Simulation time 2018890879 ps
CPU time 4.3 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 201140 kb
Host smart-409b8ae5-bd08-4d8d-b0d8-ec93d44cfea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142069279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.3142069279
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1690709339
Short name T28
Test name
Test status
Simulation time 3363452712 ps
CPU time 1.06 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201188 kb
Host smart-b9d75fde-40a5-4eaf-9dbb-06a50238948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690709339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.1
690709339
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.4059709104
Short name T372
Test name
Test status
Simulation time 184935371184 ps
CPU time 231.41 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:27:09 PM PDT 24
Peak memory 201252 kb
Host smart-dc39ea07-d083-476c-86ea-eed319d5fe21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059709104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.4059709104
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2243804768
Short name T661
Test name
Test status
Simulation time 3043489528 ps
CPU time 8.53 seconds
Started Aug 15 05:23:10 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201064 kb
Host smart-45417cad-1605-4550-8070-2e2963d55d91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243804768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.2243804768
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1965828778
Short name T25
Test name
Test status
Simulation time 2631583299 ps
CPU time 2.28 seconds
Started Aug 15 05:23:11 PM PDT 24
Finished Aug 15 05:23:13 PM PDT 24
Peak memory 201108 kb
Host smart-796117f3-5249-4766-9010-87ca53233ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965828778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1965828778
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.2678728910
Short name T481
Test name
Test status
Simulation time 2479133454 ps
CPU time 2.48 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201104 kb
Host smart-8e399069-ade1-4bea-b351-4483b94a38f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678728910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.2678728910
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.1932835351
Short name T689
Test name
Test status
Simulation time 2111652351 ps
CPU time 1.37 seconds
Started Aug 15 05:23:14 PM PDT 24
Finished Aug 15 05:23:16 PM PDT 24
Peak memory 200980 kb
Host smart-6e2949cc-a74a-44bf-b0af-2b066cf2929c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932835351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.1932835351
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.3724493021
Short name T246
Test name
Test status
Simulation time 2514439806 ps
CPU time 3.77 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201044 kb
Host smart-b9c83396-8e88-42fc-8da7-95af28c5ac79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724493021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.3724493021
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.1641806057
Short name T437
Test name
Test status
Simulation time 2113506800 ps
CPU time 6.2 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:23:21 PM PDT 24
Peak memory 201048 kb
Host smart-de938803-5089-4fda-aa02-0e4a7477f01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641806057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.1641806057
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.35021439
Short name T667
Test name
Test status
Simulation time 10014003361 ps
CPU time 13.85 seconds
Started Aug 15 05:23:09 PM PDT 24
Finished Aug 15 05:23:23 PM PDT 24
Peak memory 210980 kb
Host smart-97f4b247-4f7f-47d8-b28d-82cf8f2de3b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35021439 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.35021439
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.369250342
Short name T224
Test name
Test status
Simulation time 2018348803 ps
CPU time 3.34 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:22 PM PDT 24
Peak memory 201068 kb
Host smart-35e9a5a9-1c79-4d02-99e5-ebe3d707a113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369250342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_tes
t.369250342
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.4257031027
Short name T663
Test name
Test status
Simulation time 3703930792 ps
CPU time 9.71 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:27 PM PDT 24
Peak memory 201184 kb
Host smart-48d5f317-9441-4cbe-bf51-9803a7268b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257031027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.4
257031027
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.417886185
Short name T131
Test name
Test status
Simulation time 28228186050 ps
CPU time 16.01 seconds
Started Aug 15 05:23:14 PM PDT 24
Finished Aug 15 05:23:30 PM PDT 24
Peak memory 200780 kb
Host smart-ef7aa262-3f55-45be-94bb-e4005a2913f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417886185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.417886185
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2933228624
Short name T592
Test name
Test status
Simulation time 38403311087 ps
CPU time 70.3 seconds
Started Aug 15 05:23:19 PM PDT 24
Finished Aug 15 05:24:29 PM PDT 24
Peak memory 201344 kb
Host smart-fc63f986-84bf-4849-a5ee-6dda1555367a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933228624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.2933228624
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.3640193063
Short name T170
Test name
Test status
Simulation time 4503991556 ps
CPU time 8.27 seconds
Started Aug 15 05:23:04 PM PDT 24
Finished Aug 15 05:23:12 PM PDT 24
Peak memory 201104 kb
Host smart-c652fec3-7030-40cb-98d4-77107400e8b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640193063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.3640193063
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.568674476
Short name T776
Test name
Test status
Simulation time 2637839216 ps
CPU time 2.04 seconds
Started Aug 15 05:23:10 PM PDT 24
Finished Aug 15 05:23:13 PM PDT 24
Peak memory 201028 kb
Host smart-a11e38e7-77ad-43d8-a2b9-86edf99186af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568674476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.568674476
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.3983379007
Short name T784
Test name
Test status
Simulation time 2481960783 ps
CPU time 4.24 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:23:25 PM PDT 24
Peak memory 201128 kb
Host smart-708fd6ec-a3be-4c95-be26-4f5e5040ad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983379007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.3983379007
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.3802966149
Short name T427
Test name
Test status
Simulation time 2267785299 ps
CPU time 2.11 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201092 kb
Host smart-10d5ba48-1bf9-40a2-b186-29ee0d83e288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802966149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.3802966149
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.2166169333
Short name T331
Test name
Test status
Simulation time 2537029190 ps
CPU time 2.32 seconds
Started Aug 15 05:23:09 PM PDT 24
Finished Aug 15 05:23:11 PM PDT 24
Peak memory 201068 kb
Host smart-57ca9911-e123-47a3-80d9-0e1010af1bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166169333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.2166169333
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.1121245539
Short name T466
Test name
Test status
Simulation time 2126479039 ps
CPU time 1.96 seconds
Started Aug 15 05:23:10 PM PDT 24
Finished Aug 15 05:23:12 PM PDT 24
Peak memory 201064 kb
Host smart-6db90088-4f7e-4a27-810e-10e4f7b33be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121245539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.1121245539
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.1658437752
Short name T503
Test name
Test status
Simulation time 7309767680 ps
CPU time 4.2 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:22 PM PDT 24
Peak memory 201080 kb
Host smart-a06dd897-d9fa-49e5-8cba-075bd66a6c68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658437752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.1658437752
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2785210468
Short name T693
Test name
Test status
Simulation time 4908538846 ps
CPU time 1.94 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:23:17 PM PDT 24
Peak memory 201108 kb
Host smart-84f697e2-4b7a-4c34-955a-2caebf4cdbd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785210468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.2785210468
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.2947232097
Short name T162
Test name
Test status
Simulation time 2042313783 ps
CPU time 1.66 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 201136 kb
Host smart-00be01aa-3b25-4b46-a84d-181433b6eba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947232097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.2947232097
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.616869510
Short name T348
Test name
Test status
Simulation time 3245683411 ps
CPU time 8.75 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:31 PM PDT 24
Peak memory 201136 kb
Host smart-625a3153-4d00-42c2-b972-7307316f0a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616869510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.616869510
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.498442115
Short name T505
Test name
Test status
Simulation time 43140605899 ps
CPU time 116.71 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:25:14 PM PDT 24
Peak memory 201308 kb
Host smart-c27c54a1-85d4-4db7-89a2-7e037c97992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498442115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_wi
th_pre_cond.498442115
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.304414792
Short name T147
Test name
Test status
Simulation time 3142777648 ps
CPU time 2.79 seconds
Started Aug 15 05:23:21 PM PDT 24
Finished Aug 15 05:23:24 PM PDT 24
Peak memory 201056 kb
Host smart-c3937df2-1016-4399-a2fd-8fa63d06b27c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304414792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_ec_pwr_on_rst.304414792
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.3017518766
Short name T173
Test name
Test status
Simulation time 4995446368 ps
CPU time 3.58 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:22 PM PDT 24
Peak memory 201136 kb
Host smart-10c0c067-e3a5-4665-ade1-1cf558754c31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017518766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.3017518766
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1822201355
Short name T493
Test name
Test status
Simulation time 2636412305 ps
CPU time 2.21 seconds
Started Aug 15 05:23:22 PM PDT 24
Finished Aug 15 05:23:25 PM PDT 24
Peak memory 201136 kb
Host smart-c2c2f0be-c4b5-411d-afc6-9251fc856a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822201355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.1822201355
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.2513994058
Short name T23
Test name
Test status
Simulation time 2471016088 ps
CPU time 2.18 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 201120 kb
Host smart-9b12e876-54fe-4353-8d3c-1e26e59a2396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513994058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.2513994058
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.3761684703
Short name T540
Test name
Test status
Simulation time 2193098788 ps
CPU time 6.04 seconds
Started Aug 15 05:23:23 PM PDT 24
Finished Aug 15 05:23:29 PM PDT 24
Peak memory 201064 kb
Host smart-f0f92c31-887c-4ab2-98a1-4a2d6d25c7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761684703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.3761684703
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2347656047
Short name T673
Test name
Test status
Simulation time 2558431339 ps
CPU time 1.51 seconds
Started Aug 15 05:23:21 PM PDT 24
Finished Aug 15 05:23:22 PM PDT 24
Peak memory 201136 kb
Host smart-50256ef1-326b-4147-8e8d-80d8ec7598ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347656047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.2347656047
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.1047291234
Short name T570
Test name
Test status
Simulation time 2112570735 ps
CPU time 3.51 seconds
Started Aug 15 05:23:22 PM PDT 24
Finished Aug 15 05:23:25 PM PDT 24
Peak memory 201004 kb
Host smart-c42e65ac-6ea6-498f-942d-e27a6d61c2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047291234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1047291234
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.2209260021
Short name T252
Test name
Test status
Simulation time 6722579385 ps
CPU time 18.02 seconds
Started Aug 15 05:23:21 PM PDT 24
Finished Aug 15 05:23:39 PM PDT 24
Peak memory 201104 kb
Host smart-54927737-245d-48b7-a641-652aa74da093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209260021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.2209260021
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1299909712
Short name T345
Test name
Test status
Simulation time 8552851242 ps
CPU time 7.47 seconds
Started Aug 15 05:23:20 PM PDT 24
Finished Aug 15 05:23:28 PM PDT 24
Peak memory 209612 kb
Host smart-1469af92-5f23-481b-85e4-e638c0a3b70c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299909712 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.1299909712
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.34656715
Short name T234
Test name
Test status
Simulation time 2022058981 ps
CPU time 3.06 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201028 kb
Host smart-598db046-f05a-4c84-ad89-7ddd75146b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34656715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test
.34656715
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.104062187
Short name T371
Test name
Test status
Simulation time 3814934078 ps
CPU time 2.16 seconds
Started Aug 15 05:23:20 PM PDT 24
Finished Aug 15 05:23:23 PM PDT 24
Peak memory 201184 kb
Host smart-79023b57-ab40-49b0-af9a-4bf988e0e59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104062187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.104062187
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.1030267597
Short name T290
Test name
Test status
Simulation time 115489014312 ps
CPU time 281.45 seconds
Started Aug 15 05:23:25 PM PDT 24
Finished Aug 15 05:28:07 PM PDT 24
Peak memory 201188 kb
Host smart-5fcdc8d6-d245-40a3-b8b7-4b9100d78e1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030267597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.1030267597
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.4126636067
Short name T270
Test name
Test status
Simulation time 46620021834 ps
CPU time 30.47 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:47 PM PDT 24
Peak memory 201244 kb
Host smart-a45a5e4c-04e6-4c92-825c-2414d1cb9c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126636067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.4126636067
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.4201026353
Short name T512
Test name
Test status
Simulation time 2730725926 ps
CPU time 1.39 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 201124 kb
Host smart-066584ff-51e1-40c5-8205-a58cee2a6175
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201026353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.4201026353
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.201221440
Short name T190
Test name
Test status
Simulation time 3594084552 ps
CPU time 3.93 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 201144 kb
Host smart-45940c32-2e13-4808-9578-442e23fbb285
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201221440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctr
l_edge_detect.201221440
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.4113314322
Short name T87
Test name
Test status
Simulation time 2664342126 ps
CPU time 1.44 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 201108 kb
Host smart-944c6b0f-c652-497b-b431-a205769985e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113314322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.4113314322
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.1765237028
Short name T780
Test name
Test status
Simulation time 2462870281 ps
CPU time 7.42 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:26 PM PDT 24
Peak memory 201068 kb
Host smart-b6165a67-a92a-48ae-9305-55c2c87498f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765237028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.1765237028
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.444746556
Short name T239
Test name
Test status
Simulation time 2044693459 ps
CPU time 5.5 seconds
Started Aug 15 05:23:19 PM PDT 24
Finished Aug 15 05:23:24 PM PDT 24
Peak memory 201060 kb
Host smart-2e096fb5-ac74-4312-acee-1c57b881ca38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444746556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.444746556
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.3575046252
Short name T654
Test name
Test status
Simulation time 2510265195 ps
CPU time 6.47 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:24 PM PDT 24
Peak memory 201096 kb
Host smart-68b693b0-10e1-40fb-803d-c269ffe952f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575046252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.3575046252
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.644542934
Short name T609
Test name
Test status
Simulation time 2113948812 ps
CPU time 6.31 seconds
Started Aug 15 05:23:20 PM PDT 24
Finished Aug 15 05:23:27 PM PDT 24
Peak memory 201044 kb
Host smart-c482402b-2957-4828-b3d1-5ef8b5e1c6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644542934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.644542934
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.2481567883
Short name T176
Test name
Test status
Simulation time 76179558932 ps
CPU time 50.17 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:24:08 PM PDT 24
Peak memory 201300 kb
Host smart-99f4b90a-c5f2-4a24-a040-2f9942b52e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481567883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.2481567883
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2270095924
Short name T227
Test name
Test status
Simulation time 24390554240 ps
CPU time 6.63 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:25 PM PDT 24
Peak memory 201428 kb
Host smart-6f5d54b4-facb-4ebc-9120-a9e17d970530
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270095924 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.2270095924
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2542088
Short name T34
Test name
Test status
Simulation time 8399470171 ps
CPU time 2.24 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201140 kb
Host smart-ceaa18a8-cfbc-4c29-b946-13867926f905
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctr
l_ultra_low_pwr.2542088
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.3445747053
Short name T210
Test name
Test status
Simulation time 2014381161 ps
CPU time 5.22 seconds
Started Aug 15 05:23:30 PM PDT 24
Finished Aug 15 05:23:35 PM PDT 24
Peak memory 201092 kb
Host smart-26e4de1d-8f5f-4a21-8f2c-0b8e8a9c3812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445747053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.3445747053
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.631905667
Short name T337
Test name
Test status
Simulation time 3590790652 ps
CPU time 9.72 seconds
Started Aug 15 05:23:29 PM PDT 24
Finished Aug 15 05:23:39 PM PDT 24
Peak memory 201188 kb
Host smart-7123fa5f-8ffd-476f-a7be-6dd4ffb3388e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631905667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.631905667
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.219481532
Short name T600
Test name
Test status
Simulation time 121945269016 ps
CPU time 84.32 seconds
Started Aug 15 05:23:25 PM PDT 24
Finished Aug 15 05:24:49 PM PDT 24
Peak memory 201288 kb
Host smart-f08796b1-079b-47fc-8f76-2009b5e0cd1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219481532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_combo_detect.219481532
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3379097197
Short name T660
Test name
Test status
Simulation time 67890747256 ps
CPU time 45.97 seconds
Started Aug 15 05:23:25 PM PDT 24
Finished Aug 15 05:24:11 PM PDT 24
Peak memory 201304 kb
Host smart-bf86f0a0-e372-4a1f-a17c-be288a0fa345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379097197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.3379097197
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.455781900
Short name T532
Test name
Test status
Simulation time 2975694014 ps
CPU time 4.55 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:22 PM PDT 24
Peak memory 201120 kb
Host smart-cdf96edb-211e-4a78-a279-d49120766b84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455781900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ec_pwr_on_rst.455781900
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.835229371
Short name T256
Test name
Test status
Simulation time 3582595261 ps
CPU time 8.67 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:25 PM PDT 24
Peak memory 201052 kb
Host smart-39910266-7eb6-40db-9c7c-28826060b059
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835229371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctr
l_edge_detect.835229371
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3363964919
Short name T730
Test name
Test status
Simulation time 2612025952 ps
CPU time 4.06 seconds
Started Aug 15 05:23:19 PM PDT 24
Finished Aug 15 05:23:23 PM PDT 24
Peak memory 201072 kb
Host smart-fb385869-8f20-48d4-88fd-fbf89c9ce7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363964919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.3363964919
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.2608746926
Short name T490
Test name
Test status
Simulation time 2467976672 ps
CPU time 4.07 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:21 PM PDT 24
Peak memory 201072 kb
Host smart-76fa1f44-f912-4b03-aa86-2502eeb557f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608746926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.2608746926
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3130215018
Short name T630
Test name
Test status
Simulation time 2087089490 ps
CPU time 1.96 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201056 kb
Host smart-f3a3d3e5-778e-4329-9cf4-982da8ca62f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130215018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3130215018
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.159296353
Short name T549
Test name
Test status
Simulation time 2524085921 ps
CPU time 2.22 seconds
Started Aug 15 05:23:15 PM PDT 24
Finished Aug 15 05:23:18 PM PDT 24
Peak memory 201036 kb
Host smart-3b0fded8-5b33-494f-8ebf-e308b9127bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159296353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.159296353
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.2190281215
Short name T498
Test name
Test status
Simulation time 2130490949 ps
CPU time 1.9 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 201060 kb
Host smart-f5282b0a-46b5-452b-849f-74d06f7de2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190281215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.2190281215
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.470687922
Short name T74
Test name
Test status
Simulation time 10847964374 ps
CPU time 25.94 seconds
Started Aug 15 05:23:21 PM PDT 24
Finished Aug 15 05:23:47 PM PDT 24
Peak memory 201068 kb
Host smart-003c6a31-635c-4241-be72-9823a034eb3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470687922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_st
ress_all.470687922
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3409057378
Short name T310
Test name
Test status
Simulation time 15471433620 ps
CPU time 10.9 seconds
Started Aug 15 05:23:20 PM PDT 24
Finished Aug 15 05:23:31 PM PDT 24
Peak memory 217172 kb
Host smart-b68c6a55-50f0-4e04-9a4f-060558d27d25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409057378 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.3409057378
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1849132141
Short name T71
Test name
Test status
Simulation time 10420451619 ps
CPU time 3.09 seconds
Started Aug 15 05:23:29 PM PDT 24
Finished Aug 15 05:23:33 PM PDT 24
Peak memory 200384 kb
Host smart-d563e934-4e36-4f4f-9d35-0bcce8c31c80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849132141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.1849132141
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.3945758446
Short name T436
Test name
Test status
Simulation time 2026613418 ps
CPU time 3.04 seconds
Started Aug 15 05:23:29 PM PDT 24
Finished Aug 15 05:23:32 PM PDT 24
Peak memory 201084 kb
Host smart-95c1cefd-8038-479f-b2c5-e97b71c08a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945758446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.3945758446
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.3677209100
Short name T483
Test name
Test status
Simulation time 78782073164 ps
CPU time 36.79 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:54 PM PDT 24
Peak memory 201160 kb
Host smart-b117a744-653d-4ba1-afd9-404bead49582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677209100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.3
677209100
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.3648222079
Short name T52
Test name
Test status
Simulation time 137907112853 ps
CPU time 350.27 seconds
Started Aug 15 05:23:22 PM PDT 24
Finished Aug 15 05:29:12 PM PDT 24
Peak memory 201304 kb
Host smart-e102cc11-6f3e-4306-954e-fd31c56247c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648222079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.3648222079
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2750445189
Short name T123
Test name
Test status
Simulation time 26831291761 ps
CPU time 67.61 seconds
Started Aug 15 05:23:28 PM PDT 24
Finished Aug 15 05:24:36 PM PDT 24
Peak memory 201264 kb
Host smart-39202323-0bbe-43d1-bf55-fd80c9b5797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750445189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.2750445189
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1823760673
Short name T196
Test name
Test status
Simulation time 2717847296 ps
CPU time 7.95 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:26 PM PDT 24
Peak memory 201108 kb
Host smart-cffb825b-5d28-4684-8385-2022014a6015
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823760673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.1823760673
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.182052655
Short name T257
Test name
Test status
Simulation time 3780380611 ps
CPU time 7.8 seconds
Started Aug 15 05:23:21 PM PDT 24
Finished Aug 15 05:23:29 PM PDT 24
Peak memory 201060 kb
Host smart-b70151ca-70ea-4f84-aa6b-21b069b17afd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182052655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctr
l_edge_detect.182052655
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.878286145
Short name T659
Test name
Test status
Simulation time 2610403633 ps
CPU time 7.7 seconds
Started Aug 15 05:23:19 PM PDT 24
Finished Aug 15 05:23:27 PM PDT 24
Peak memory 201044 kb
Host smart-e1a9bde9-b157-4a8b-ac1b-92889b5d3121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878286145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.878286145
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.300125347
Short name T439
Test name
Test status
Simulation time 2461488230 ps
CPU time 7.1 seconds
Started Aug 15 05:23:20 PM PDT 24
Finished Aug 15 05:23:27 PM PDT 24
Peak memory 201092 kb
Host smart-17b9693b-66a1-42ab-b74b-e5a319df2aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300125347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.300125347
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.456975890
Short name T732
Test name
Test status
Simulation time 2154273478 ps
CPU time 1.45 seconds
Started Aug 15 05:23:18 PM PDT 24
Finished Aug 15 05:23:20 PM PDT 24
Peak memory 201064 kb
Host smart-2f9aede7-3d2f-46ba-b381-a0aaee2708a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456975890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.456975890
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.177028667
Short name T330
Test name
Test status
Simulation time 2536677940 ps
CPU time 1.67 seconds
Started Aug 15 05:23:30 PM PDT 24
Finished Aug 15 05:23:32 PM PDT 24
Peak memory 201080 kb
Host smart-23338af1-a072-48ba-b675-8893ec3ad895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177028667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.177028667
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.3078993717
Short name T675
Test name
Test status
Simulation time 2116884758 ps
CPU time 3.12 seconds
Started Aug 15 05:23:21 PM PDT 24
Finished Aug 15 05:23:24 PM PDT 24
Peak memory 201024 kb
Host smart-aa824a49-1def-46d1-a428-f10a0d4495c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078993717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.3078993717
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.505980100
Short name T304
Test name
Test status
Simulation time 16908081432 ps
CPU time 9.97 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:27 PM PDT 24
Peak memory 209640 kb
Host smart-d05ff7e4-4c4e-4f07-8cf1-3b1458785fa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505980100 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.505980100
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2808193829
Short name T151
Test name
Test status
Simulation time 7254249034 ps
CPU time 2.53 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:19 PM PDT 24
Peak memory 201092 kb
Host smart-a0cb0e16-ba89-4478-8d75-d558881cf4bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808193829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.2808193829
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.1873199894
Short name T424
Test name
Test status
Simulation time 2031511295 ps
CPU time 2 seconds
Started Aug 15 05:22:12 PM PDT 24
Finished Aug 15 05:22:14 PM PDT 24
Peak memory 201112 kb
Host smart-09092386-5603-4c6b-8881-3abca03b3612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873199894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.1873199894
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1525354655
Short name T656
Test name
Test status
Simulation time 3254863724 ps
CPU time 2.82 seconds
Started Aug 15 05:22:03 PM PDT 24
Finished Aug 15 05:22:06 PM PDT 24
Peak memory 201228 kb
Host smart-3813dce0-c612-4027-a435-1dc91f968ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525354655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.1525354655
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.2564634895
Short name T282
Test name
Test status
Simulation time 80680376281 ps
CPU time 222.7 seconds
Started Aug 15 05:22:14 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 201264 kb
Host smart-de7b7361-6f57-4bc7-a0d6-9d695a348c84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564634895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.2564634895
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1732126172
Short name T198
Test name
Test status
Simulation time 2191189554 ps
CPU time 6.75 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:14 PM PDT 24
Peak memory 201116 kb
Host smart-a1830c08-f1dd-4e06-b222-41152a1c0a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732126172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.1732126172
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2993151681
Short name T121
Test name
Test status
Simulation time 26596280389 ps
CPU time 19.89 seconds
Started Aug 15 05:22:04 PM PDT 24
Finished Aug 15 05:22:24 PM PDT 24
Peak memory 201304 kb
Host smart-129d4428-96b3-46a3-9f69-66c4064bb11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993151681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.2993151681
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.467931922
Short name T40
Test name
Test status
Simulation time 3730851833 ps
CPU time 7.84 seconds
Started Aug 15 05:22:09 PM PDT 24
Finished Aug 15 05:22:17 PM PDT 24
Peak memory 201056 kb
Host smart-2293d4c2-84c7-4448-850c-9aee03801378
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467931922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_edge_detect.467931922
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.737387693
Short name T13
Test name
Test status
Simulation time 2641653016 ps
CPU time 2.01 seconds
Started Aug 15 05:22:23 PM PDT 24
Finished Aug 15 05:22:25 PM PDT 24
Peak memory 201108 kb
Host smart-9426123e-0811-4bb4-a9e0-a0a917e23380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737387693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.737387693
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.2769140146
Short name T604
Test name
Test status
Simulation time 2453598494 ps
CPU time 3.85 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:11 PM PDT 24
Peak memory 201108 kb
Host smart-e47c95a2-0647-4c4a-bf7b-afe73387d67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769140146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.2769140146
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.574104737
Short name T79
Test name
Test status
Simulation time 2267415484 ps
CPU time 1.68 seconds
Started Aug 15 05:22:06 PM PDT 24
Finished Aug 15 05:22:08 PM PDT 24
Peak memory 201088 kb
Host smart-836c73a3-6b78-45a2-89ab-ba4b5092d50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574104737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.574104737
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.714737814
Short name T789
Test name
Test status
Simulation time 2536906639 ps
CPU time 2.58 seconds
Started Aug 15 05:22:10 PM PDT 24
Finished Aug 15 05:22:13 PM PDT 24
Peak memory 201144 kb
Host smart-5fea5e0e-607e-4730-9bf9-c1454a239840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714737814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.714737814
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.2184993997
Short name T695
Test name
Test status
Simulation time 2118596664 ps
CPU time 3.44 seconds
Started Aug 15 05:22:10 PM PDT 24
Finished Aug 15 05:22:13 PM PDT 24
Peak memory 201028 kb
Host smart-b00a3fa6-4116-4bd2-a804-188145cdc0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184993997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.2184993997
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.843587351
Short name T128
Test name
Test status
Simulation time 92327355818 ps
CPU time 58.82 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:23:06 PM PDT 24
Peak memory 201232 kb
Host smart-89308629-cc59-48bd-b672-b098fbc83062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843587351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_str
ess_all.843587351
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3564415714
Short name T298
Test name
Test status
Simulation time 8040061811 ps
CPU time 3.17 seconds
Started Aug 15 05:22:11 PM PDT 24
Finished Aug 15 05:22:14 PM PDT 24
Peak memory 201284 kb
Host smart-9ec57529-9102-4972-b23b-7a68cd062ac3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564415714 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.3564415714
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2483701156
Short name T526
Test name
Test status
Simulation time 5154806099 ps
CPU time 7.42 seconds
Started Aug 15 05:22:15 PM PDT 24
Finished Aug 15 05:22:23 PM PDT 24
Peak memory 201076 kb
Host smart-4ca95766-839e-47ae-a7a2-2ff5e39a7ac2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483701156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.2483701156
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.908437820
Short name T685
Test name
Test status
Simulation time 2014709725 ps
CPU time 5.72 seconds
Started Aug 15 05:23:26 PM PDT 24
Finished Aug 15 05:23:32 PM PDT 24
Peak memory 201124 kb
Host smart-043c1d89-d41c-4ea0-8c40-02a97f92e114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908437820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_tes
t.908437820
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1814637308
Short name T561
Test name
Test status
Simulation time 3185409597 ps
CPU time 3.18 seconds
Started Aug 15 05:23:21 PM PDT 24
Finished Aug 15 05:23:24 PM PDT 24
Peak memory 201184 kb
Host smart-be5a65b5-157c-457f-877d-0b4f7721a949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814637308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.1
814637308
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.1022081638
Short name T144
Test name
Test status
Simulation time 77565170005 ps
CPU time 196.74 seconds
Started Aug 15 05:23:20 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 201220 kb
Host smart-f974060d-ea98-4aea-b8e9-1458a070b5fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022081638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.1022081638
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2640352506
Short name T197
Test name
Test status
Simulation time 111339638189 ps
CPU time 55.27 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:24:12 PM PDT 24
Peak memory 201328 kb
Host smart-42bc748e-79ba-4131-9dd2-759c6d90a622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640352506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.2640352506
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2569993151
Short name T68
Test name
Test status
Simulation time 3268652520 ps
CPU time 2.93 seconds
Started Aug 15 05:23:22 PM PDT 24
Finished Aug 15 05:23:25 PM PDT 24
Peak memory 201128 kb
Host smart-9727b7f2-e17e-4d8b-8dcb-c3ba1780286a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569993151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.2569993151
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3117531464
Short name T44
Test name
Test status
Simulation time 2718635393 ps
CPU time 3.76 seconds
Started Aug 15 05:23:22 PM PDT 24
Finished Aug 15 05:23:26 PM PDT 24
Peak memory 201068 kb
Host smart-80c91912-ff12-4256-8b6c-0c673ab13aa4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117531464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.3117531464
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.401150146
Short name T238
Test name
Test status
Simulation time 2613499617 ps
CPU time 7.54 seconds
Started Aug 15 05:23:26 PM PDT 24
Finished Aug 15 05:23:34 PM PDT 24
Peak memory 201120 kb
Host smart-ebfe4e84-67b9-4ed8-b2b4-c0d912a0d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401150146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.401150146
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2676686798
Short name T753
Test name
Test status
Simulation time 2469756580 ps
CPU time 2.61 seconds
Started Aug 15 05:23:21 PM PDT 24
Finished Aug 15 05:23:24 PM PDT 24
Peak memory 201064 kb
Host smart-3498b9d6-722b-40b1-b6b5-676a6d28b0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676686798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.2676686798
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3745347949
Short name T429
Test name
Test status
Simulation time 2139949855 ps
CPU time 5.52 seconds
Started Aug 15 05:23:24 PM PDT 24
Finished Aug 15 05:23:30 PM PDT 24
Peak memory 201060 kb
Host smart-3c68d85b-b454-4855-a5f6-bdb4b882f1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745347949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.3745347949
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.136365888
Short name T195
Test name
Test status
Simulation time 2514106317 ps
CPU time 7.04 seconds
Started Aug 15 05:23:16 PM PDT 24
Finished Aug 15 05:23:23 PM PDT 24
Peak memory 201064 kb
Host smart-47031699-52e9-4437-9884-99519a5645ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136365888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.136365888
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.2312042185
Short name T618
Test name
Test status
Simulation time 2119985679 ps
CPU time 2.34 seconds
Started Aug 15 05:23:25 PM PDT 24
Finished Aug 15 05:23:28 PM PDT 24
Peak memory 201032 kb
Host smart-19c1a525-6908-4113-b1e6-eb82fa2c0dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312042185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.2312042185
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.4257482001
Short name T212
Test name
Test status
Simulation time 11746427666 ps
CPU time 7.99 seconds
Started Aug 15 05:23:24 PM PDT 24
Finished Aug 15 05:23:33 PM PDT 24
Peak memory 201356 kb
Host smart-1206e3a8-2ba0-47a9-9acc-a1f52aaf77bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257482001 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.4257482001
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.625984662
Short name T417
Test name
Test status
Simulation time 2409132072964 ps
CPU time 751.01 seconds
Started Aug 15 05:23:22 PM PDT 24
Finished Aug 15 05:35:53 PM PDT 24
Peak memory 201048 kb
Host smart-969d0f2a-ef1b-4385-8a00-6b65120db7a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625984662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_ultra_low_pwr.625984662
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.2160457168
Short name T569
Test name
Test status
Simulation time 2038231358 ps
CPU time 1.93 seconds
Started Aug 15 05:23:27 PM PDT 24
Finished Aug 15 05:23:29 PM PDT 24
Peak memory 201084 kb
Host smart-74340437-2862-4bc6-93a3-6c79b430fb84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160457168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.2160457168
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.798986215
Short name T60
Test name
Test status
Simulation time 3527756455 ps
CPU time 2.92 seconds
Started Aug 15 05:23:27 PM PDT 24
Finished Aug 15 05:23:30 PM PDT 24
Peak memory 200996 kb
Host smart-47371025-2407-49a6-9481-ecf1c2c5737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798986215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.798986215
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.2489526411
Short name T715
Test name
Test status
Simulation time 64772064773 ps
CPU time 150.7 seconds
Started Aug 15 05:23:33 PM PDT 24
Finished Aug 15 05:26:03 PM PDT 24
Peak memory 201292 kb
Host smart-68b40589-406d-440f-b6b7-d783c4ce4e60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489526411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.2489526411
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3619837754
Short name T712
Test name
Test status
Simulation time 60833638750 ps
CPU time 165.66 seconds
Started Aug 15 05:23:33 PM PDT 24
Finished Aug 15 05:26:19 PM PDT 24
Peak memory 201328 kb
Host smart-79a6af98-95f0-4491-8b98-8db95d5de74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619837754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.3619837754
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1110139928
Short name T470
Test name
Test status
Simulation time 4677535472 ps
CPU time 1.26 seconds
Started Aug 15 05:23:28 PM PDT 24
Finished Aug 15 05:23:29 PM PDT 24
Peak memory 201092 kb
Host smart-edca08d9-c255-4cca-872d-f3173cf5467d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110139928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.1110139928
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.589982207
Short name T237
Test name
Test status
Simulation time 2411347300 ps
CPU time 3.62 seconds
Started Aug 15 05:23:27 PM PDT 24
Finished Aug 15 05:23:31 PM PDT 24
Peak memory 201144 kb
Host smart-7df13cca-fffe-4206-a287-8757e0bb4fe6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589982207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctr
l_edge_detect.589982207
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2431280497
Short name T91
Test name
Test status
Simulation time 2631237243 ps
CPU time 2.59 seconds
Started Aug 15 05:23:41 PM PDT 24
Finished Aug 15 05:23:43 PM PDT 24
Peak memory 201128 kb
Host smart-e7bd14c7-1e0f-42d9-8033-3c57f207e95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431280497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.2431280497
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.867094730
Short name T81
Test name
Test status
Simulation time 2458889431 ps
CPU time 7.01 seconds
Started Aug 15 05:23:30 PM PDT 24
Finished Aug 15 05:23:37 PM PDT 24
Peak memory 201084 kb
Host smart-cb837b30-53d8-49bc-ac71-35e318812103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867094730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.867094730
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2945854741
Short name T666
Test name
Test status
Simulation time 2239633269 ps
CPU time 1.39 seconds
Started Aug 15 05:23:29 PM PDT 24
Finished Aug 15 05:23:30 PM PDT 24
Peak memory 201080 kb
Host smart-698a66a2-491d-42a5-b31b-2d8af1a1101b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945854741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.2945854741
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3214722335
Short name T564
Test name
Test status
Simulation time 2555825023 ps
CPU time 1.66 seconds
Started Aug 15 05:23:29 PM PDT 24
Finished Aug 15 05:23:31 PM PDT 24
Peak memory 200488 kb
Host smart-b2c2c0fc-6812-4e9a-807e-da447b244048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214722335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.3214722335
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.1038062846
Short name T756
Test name
Test status
Simulation time 2110506566 ps
CPU time 6.06 seconds
Started Aug 15 05:23:17 PM PDT 24
Finished Aug 15 05:23:24 PM PDT 24
Peak memory 201064 kb
Host smart-9c259066-a3c0-4f22-ba04-20a72a498770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038062846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1038062846
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.281584382
Short name T431
Test name
Test status
Simulation time 6897513995 ps
CPU time 18.26 seconds
Started Aug 15 05:23:28 PM PDT 24
Finished Aug 15 05:23:46 PM PDT 24
Peak memory 201100 kb
Host smart-ca23b767-81e5-4b46-8689-dd1c2222448e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281584382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_st
ress_all.281584382
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.879969083
Short name T145
Test name
Test status
Simulation time 2864863354 ps
CPU time 2.13 seconds
Started Aug 15 05:23:39 PM PDT 24
Finished Aug 15 05:23:41 PM PDT 24
Peak memory 201180 kb
Host smart-cb1e38f5-8e02-4e17-9293-d4eb8532297a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879969083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_ultra_low_pwr.879969083
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.3142488764
Short name T723
Test name
Test status
Simulation time 2019876248 ps
CPU time 3.13 seconds
Started Aug 15 05:23:41 PM PDT 24
Finished Aug 15 05:23:44 PM PDT 24
Peak memory 201128 kb
Host smart-d89da0dc-75a6-4e4b-80ff-cafd4280db6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142488764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.3142488764
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.289094475
Short name T178
Test name
Test status
Simulation time 3403241915 ps
CPU time 2.6 seconds
Started Aug 15 05:23:41 PM PDT 24
Finished Aug 15 05:23:44 PM PDT 24
Peak memory 201192 kb
Host smart-90ed116b-aa6e-466d-beef-6c31cc14d9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289094475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.289094475
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.3552209259
Short name T405
Test name
Test status
Simulation time 171365186373 ps
CPU time 212.64 seconds
Started Aug 15 05:23:26 PM PDT 24
Finished Aug 15 05:26:59 PM PDT 24
Peak memory 201268 kb
Host smart-13caded1-a470-4ae0-a0b5-485bbe84f66b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552209259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.3552209259
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3786665701
Short name T119
Test name
Test status
Simulation time 26907901478 ps
CPU time 7.86 seconds
Started Aug 15 05:23:28 PM PDT 24
Finished Aug 15 05:23:36 PM PDT 24
Peak memory 201304 kb
Host smart-930d1904-525f-4ed1-9f37-a60278b82e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786665701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.3786665701
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.161436902
Short name T64
Test name
Test status
Simulation time 3372431733 ps
CPU time 1.21 seconds
Started Aug 15 05:23:25 PM PDT 24
Finished Aug 15 05:23:26 PM PDT 24
Peak memory 201044 kb
Host smart-7f4ced61-4e2a-4e16-a35a-f3409c201893
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161436902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_ec_pwr_on_rst.161436902
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.249928590
Short name T216
Test name
Test status
Simulation time 3109374568 ps
CPU time 3.56 seconds
Started Aug 15 05:23:30 PM PDT 24
Finished Aug 15 05:23:33 PM PDT 24
Peak memory 201056 kb
Host smart-7a39c777-7c3c-44b6-bfcf-b3085e6ba959
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249928590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctr
l_edge_detect.249928590
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.255147972
Short name T714
Test name
Test status
Simulation time 2623230278 ps
CPU time 3.83 seconds
Started Aug 15 05:23:26 PM PDT 24
Finished Aug 15 05:23:30 PM PDT 24
Peak memory 201112 kb
Host smart-25de274f-fc49-4319-8a66-1ba7c9666c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255147972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.255147972
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.4139328459
Short name T250
Test name
Test status
Simulation time 2458941994 ps
CPU time 2.17 seconds
Started Aug 15 05:23:36 PM PDT 24
Finished Aug 15 05:23:38 PM PDT 24
Peak memory 201132 kb
Host smart-3de4bea0-3c4d-4c2f-b4aa-e3feb7e47ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139328459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.4139328459
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.712674536
Short name T455
Test name
Test status
Simulation time 2081247017 ps
CPU time 1.93 seconds
Started Aug 15 05:23:41 PM PDT 24
Finished Aug 15 05:23:43 PM PDT 24
Peak memory 201052 kb
Host smart-4e7ae90d-2273-4e9c-8924-f75f7c809b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712674536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.712674536
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2672030881
Short name T90
Test name
Test status
Simulation time 2534216519 ps
CPU time 2.32 seconds
Started Aug 15 05:23:37 PM PDT 24
Finished Aug 15 05:23:40 PM PDT 24
Peak memory 201136 kb
Host smart-00cce836-0053-43ff-90a5-cd7b93e9686c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672030881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.2672030881
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.1304205535
Short name T629
Test name
Test status
Simulation time 2167239607 ps
CPU time 1.2 seconds
Started Aug 15 05:23:26 PM PDT 24
Finished Aug 15 05:23:27 PM PDT 24
Peak memory 201112 kb
Host smart-b6bd6d1c-31e5-4e10-a904-a8c97436134e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304205535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.1304205535
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.46107052
Short name T684
Test name
Test status
Simulation time 154993127168 ps
CPU time 386.06 seconds
Started Aug 15 05:23:34 PM PDT 24
Finished Aug 15 05:30:01 PM PDT 24
Peak memory 201244 kb
Host smart-dc228955-8a25-4d54-af43-eb7a0c9fa2e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46107052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_str
ess_all.46107052
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2708070455
Short name T333
Test name
Test status
Simulation time 2954540085 ps
CPU time 8.09 seconds
Started Aug 15 05:23:42 PM PDT 24
Finished Aug 15 05:23:50 PM PDT 24
Peak memory 201288 kb
Host smart-32db4643-d005-48ce-983e-0e13f74f08c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708070455 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2708070455
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2279106428
Short name T152
Test name
Test status
Simulation time 5096030701 ps
CPU time 1.42 seconds
Started Aug 15 05:23:27 PM PDT 24
Finished Aug 15 05:23:28 PM PDT 24
Peak memory 201076 kb
Host smart-27847788-7658-43f5-ad0f-98ee55247276
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279106428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.2279106428
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.926133715
Short name T558
Test name
Test status
Simulation time 2035910019 ps
CPU time 1.79 seconds
Started Aug 15 05:23:27 PM PDT 24
Finished Aug 15 05:23:29 PM PDT 24
Peak memory 201112 kb
Host smart-8a0a44c8-5139-42a4-ba0d-1f38906a0658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926133715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_tes
t.926133715
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3471657953
Short name T510
Test name
Test status
Simulation time 3718106580 ps
CPU time 3.04 seconds
Started Aug 15 05:23:35 PM PDT 24
Finished Aug 15 05:23:38 PM PDT 24
Peak memory 201196 kb
Host smart-e85f4e58-0e79-4c96-a36f-1eac2ab5b5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471657953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.3
471657953
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.4025384793
Short name T284
Test name
Test status
Simulation time 57971133875 ps
CPU time 38.78 seconds
Started Aug 15 05:23:28 PM PDT 24
Finished Aug 15 05:24:07 PM PDT 24
Peak memory 201168 kb
Host smart-2f779374-30b3-4f6d-8243-024d74e717dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025384793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.4025384793
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.864770015
Short name T504
Test name
Test status
Simulation time 38431530503 ps
CPU time 26.59 seconds
Started Aug 15 05:23:40 PM PDT 24
Finished Aug 15 05:24:07 PM PDT 24
Peak memory 201380 kb
Host smart-b4033c1a-3523-49c4-ae6c-0636013ab2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864770015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_wi
th_pre_cond.864770015
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1610904591
Short name T528
Test name
Test status
Simulation time 2901596875 ps
CPU time 4.37 seconds
Started Aug 15 05:23:41 PM PDT 24
Finished Aug 15 05:23:46 PM PDT 24
Peak memory 201120 kb
Host smart-6b517be5-4767-4c00-940c-ce5b649ad099
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610904591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.1610904591
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.1592963265
Short name T248
Test name
Test status
Simulation time 3551233840 ps
CPU time 7.85 seconds
Started Aug 15 05:23:34 PM PDT 24
Finished Aug 15 05:23:43 PM PDT 24
Peak memory 201020 kb
Host smart-1c668687-8d50-46e3-8ac7-1cf06264379d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592963265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.1592963265
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2878170155
Short name T78
Test name
Test status
Simulation time 2610490194 ps
CPU time 7.53 seconds
Started Aug 15 05:23:31 PM PDT 24
Finished Aug 15 05:23:39 PM PDT 24
Peak memory 201112 kb
Host smart-b5a8a43f-c2fd-4d32-b288-5c5b6cd8bba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878170155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.2878170155
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1235616356
Short name T265
Test name
Test status
Simulation time 2464884236 ps
CPU time 2.99 seconds
Started Aug 15 05:23:27 PM PDT 24
Finished Aug 15 05:23:30 PM PDT 24
Peak memory 201080 kb
Host smart-f864fb37-b7ba-4b68-8dba-058b57c1dbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235616356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.1235616356
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.725821317
Short name T469
Test name
Test status
Simulation time 2237084108 ps
CPU time 1.99 seconds
Started Aug 15 05:23:25 PM PDT 24
Finished Aug 15 05:23:27 PM PDT 24
Peak memory 201336 kb
Host smart-266e07dc-10b8-4a99-bef8-367c3f7ba719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725821317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.725821317
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.644017965
Short name T219
Test name
Test status
Simulation time 2533354455 ps
CPU time 2.44 seconds
Started Aug 15 05:23:35 PM PDT 24
Finished Aug 15 05:23:37 PM PDT 24
Peak memory 201056 kb
Host smart-29b41952-8e28-4ad4-89d0-921e86be89cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644017965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.644017965
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.3270782597
Short name T423
Test name
Test status
Simulation time 2111545848 ps
CPU time 6.65 seconds
Started Aug 15 05:23:27 PM PDT 24
Finished Aug 15 05:23:33 PM PDT 24
Peak memory 201004 kb
Host smart-cc5e9cdc-d1d5-4521-a3a1-f1fe100c1082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270782597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.3270782597
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.2102000324
Short name T149
Test name
Test status
Simulation time 14481623961 ps
CPU time 6.24 seconds
Started Aug 15 05:23:28 PM PDT 24
Finished Aug 15 05:23:35 PM PDT 24
Peak memory 201108 kb
Host smart-9cca8319-1bb0-4260-b92e-fc609939e3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102000324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.2102000324
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.4052243208
Short name T334
Test name
Test status
Simulation time 7772291792 ps
CPU time 19.9 seconds
Started Aug 15 05:23:23 PM PDT 24
Finished Aug 15 05:23:43 PM PDT 24
Peak memory 209560 kb
Host smart-dd7be782-a1f2-4f4e-acbc-32e8ebfece68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052243208 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.4052243208
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2195829941
Short name T103
Test name
Test status
Simulation time 6419879719 ps
CPU time 7.12 seconds
Started Aug 15 05:23:48 PM PDT 24
Finished Aug 15 05:23:55 PM PDT 24
Peak memory 201120 kb
Host smart-98dc4df5-0b1b-419b-a4a7-084e0ebb4245
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195829941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.2195829941
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.2449741318
Short name T76
Test name
Test status
Simulation time 2023662492 ps
CPU time 1.94 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:23:56 PM PDT 24
Peak memory 201096 kb
Host smart-fc711449-1183-4d07-8a6c-4e7cd4ef4fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449741318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.2449741318
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3422727483
Short name T183
Test name
Test status
Simulation time 3574270327 ps
CPU time 2.98 seconds
Started Aug 15 05:23:39 PM PDT 24
Finished Aug 15 05:23:42 PM PDT 24
Peak memory 201192 kb
Host smart-0e9a4a07-0056-47d7-a6c2-30cd371e63ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422727483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.3
422727483
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.3752847047
Short name T480
Test name
Test status
Simulation time 67837846740 ps
CPU time 46.15 seconds
Started Aug 15 05:23:33 PM PDT 24
Finished Aug 15 05:24:19 PM PDT 24
Peak memory 201236 kb
Host smart-c2f987a6-64cc-4ec4-92b0-60cc0bc9197a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752847047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.3752847047
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2618513168
Short name T599
Test name
Test status
Simulation time 32302743530 ps
CPU time 13.87 seconds
Started Aug 15 05:23:39 PM PDT 24
Finished Aug 15 05:23:53 PM PDT 24
Peak memory 201284 kb
Host smart-ca5f276f-c206-4a5c-868b-ba42d834fad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618513168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.2618513168
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.234413918
Short name T686
Test name
Test status
Simulation time 4362043944 ps
CPU time 3.27 seconds
Started Aug 15 05:23:35 PM PDT 24
Finished Aug 15 05:23:38 PM PDT 24
Peak memory 200912 kb
Host smart-7eda24ea-43c0-4ba9-b331-9f8b67b7035f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234413918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_ec_pwr_on_rst.234413918
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.3338055424
Short name T41
Test name
Test status
Simulation time 3247179890 ps
CPU time 8.68 seconds
Started Aug 15 05:23:34 PM PDT 24
Finished Aug 15 05:23:43 PM PDT 24
Peak memory 201120 kb
Host smart-cf843f72-d725-4d71-8a43-8a9929d1e613
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338055424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.3338055424
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2494446642
Short name T638
Test name
Test status
Simulation time 2641780769 ps
CPU time 1.86 seconds
Started Aug 15 05:23:42 PM PDT 24
Finished Aug 15 05:23:44 PM PDT 24
Peak memory 201032 kb
Host smart-c0683ed9-44df-411d-b80f-630a7101ee07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494446642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.2494446642
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1241081139
Short name T82
Test name
Test status
Simulation time 2465222997 ps
CPU time 2.15 seconds
Started Aug 15 05:23:26 PM PDT 24
Finished Aug 15 05:23:29 PM PDT 24
Peak memory 201112 kb
Host smart-86741681-3102-44d8-afe5-34564a37c987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241081139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.1241081139
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1693694418
Short name T411
Test name
Test status
Simulation time 2141381913 ps
CPU time 6.47 seconds
Started Aug 15 05:23:26 PM PDT 24
Finished Aug 15 05:23:33 PM PDT 24
Peak memory 201020 kb
Host smart-a5eace0a-9baf-461e-8b36-0fc02822bce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693694418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.1693694418
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.845097393
Short name T653
Test name
Test status
Simulation time 2557136601 ps
CPU time 1.5 seconds
Started Aug 15 05:23:43 PM PDT 24
Finished Aug 15 05:23:45 PM PDT 24
Peak memory 201120 kb
Host smart-e813341a-54f4-41d7-936e-f31d9d577890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845097393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.845097393
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.1725259918
Short name T486
Test name
Test status
Simulation time 2122460683 ps
CPU time 3.08 seconds
Started Aug 15 05:23:32 PM PDT 24
Finished Aug 15 05:23:35 PM PDT 24
Peak memory 201036 kb
Host smart-60b4497d-8fc2-4518-b1ae-16094be9e6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725259918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.1725259918
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1884449736
Short name T323
Test name
Test status
Simulation time 5643350692 ps
CPU time 14.75 seconds
Started Aug 15 05:23:42 PM PDT 24
Finished Aug 15 05:23:57 PM PDT 24
Peak memory 212376 kb
Host smart-0d6cc6ef-f9b5-41ee-9095-b15733089d06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884449736 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.1884449736
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1448349246
Short name T646
Test name
Test status
Simulation time 3660939885 ps
CPU time 6.56 seconds
Started Aug 15 05:23:35 PM PDT 24
Finished Aug 15 05:23:42 PM PDT 24
Peak memory 201100 kb
Host smart-1ad5385e-d926-4b46-887a-e0332a68f00a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448349246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.1448349246
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.502660750
Short name T488
Test name
Test status
Simulation time 2013437854 ps
CPU time 5.71 seconds
Started Aug 15 05:23:46 PM PDT 24
Finished Aug 15 05:23:52 PM PDT 24
Peak memory 201096 kb
Host smart-9bd91968-b3f9-4d2c-8dad-969bebed5949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502660750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_tes
t.502660750
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2489498230
Short name T631
Test name
Test status
Simulation time 3265140870 ps
CPU time 2.62 seconds
Started Aug 15 05:23:37 PM PDT 24
Finished Aug 15 05:23:40 PM PDT 24
Peak memory 201124 kb
Host smart-7f45e65a-17f0-4855-9887-fcd1f12ff288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489498230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.2
489498230
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.4226821242
Short name T280
Test name
Test status
Simulation time 128806963695 ps
CPU time 86.18 seconds
Started Aug 15 05:23:40 PM PDT 24
Finished Aug 15 05:25:06 PM PDT 24
Peak memory 201212 kb
Host smart-664d2173-b012-49db-b568-a5135aaeaabb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226821242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.4226821242
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2893480760
Short name T662
Test name
Test status
Simulation time 37303871456 ps
CPU time 25.13 seconds
Started Aug 15 05:23:35 PM PDT 24
Finished Aug 15 05:24:00 PM PDT 24
Peak memory 201340 kb
Host smart-5274144e-eea0-4df0-b0a4-80e65a3f2d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893480760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.2893480760
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2649623582
Short name T639
Test name
Test status
Simulation time 4014293441 ps
CPU time 3.2 seconds
Started Aug 15 05:23:34 PM PDT 24
Finished Aug 15 05:23:37 PM PDT 24
Peak memory 201112 kb
Host smart-8d9d24ad-7961-42b3-8a4d-334867aa9d5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649623582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.2649623582
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.1238023129
Short name T232
Test name
Test status
Simulation time 4436760411 ps
CPU time 1.93 seconds
Started Aug 15 05:23:35 PM PDT 24
Finished Aug 15 05:23:37 PM PDT 24
Peak memory 200768 kb
Host smart-0a66082e-9555-4eb3-97d6-3395c2f3dd94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238023129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.1238023129
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.870830294
Short name T672
Test name
Test status
Simulation time 2619245082 ps
CPU time 3.95 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:23:55 PM PDT 24
Peak memory 201112 kb
Host smart-9279c5a3-d064-4389-9d86-44aa01f5aaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870830294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.870830294
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3017701795
Short name T329
Test name
Test status
Simulation time 2484741531 ps
CPU time 2.24 seconds
Started Aug 15 05:23:34 PM PDT 24
Finished Aug 15 05:23:36 PM PDT 24
Peak memory 201112 kb
Host smart-f6d5eb6f-177a-4d44-987f-54fa2b5fd1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017701795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.3017701795
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.288050432
Short name T158
Test name
Test status
Simulation time 2167663777 ps
CPU time 3.46 seconds
Started Aug 15 05:23:34 PM PDT 24
Finished Aug 15 05:23:38 PM PDT 24
Peak memory 201104 kb
Host smart-f079fe47-17be-445f-bfd0-63d13aefcf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288050432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.288050432
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.1289812476
Short name T774
Test name
Test status
Simulation time 2182114383 ps
CPU time 0.99 seconds
Started Aug 15 05:23:31 PM PDT 24
Finished Aug 15 05:23:32 PM PDT 24
Peak memory 201108 kb
Host smart-2e9c7991-b13d-435e-882d-e200351d1633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289812476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.1289812476
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.1911907080
Short name T703
Test name
Test status
Simulation time 10208883659 ps
CPU time 27.3 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:24:19 PM PDT 24
Peak memory 201072 kb
Host smart-9451a53f-b937-4c43-8b4c-d0a91d0039b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911907080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.1911907080
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2280007702
Short name T297
Test name
Test status
Simulation time 6489350813 ps
CPU time 5.35 seconds
Started Aug 15 05:23:35 PM PDT 24
Finished Aug 15 05:23:41 PM PDT 24
Peak memory 200960 kb
Host smart-f4b52605-35d4-488c-a827-2d1fe850b1dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280007702 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.2280007702
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.763404026
Short name T135
Test name
Test status
Simulation time 6563049952 ps
CPU time 7.26 seconds
Started Aug 15 05:23:38 PM PDT 24
Finished Aug 15 05:23:46 PM PDT 24
Peak memory 201148 kb
Host smart-8cf5b036-6e40-4ee5-ba51-ff952ac53852
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763404026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_ultra_low_pwr.763404026
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.2357274655
Short name T17
Test name
Test status
Simulation time 2014490982 ps
CPU time 5.33 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:23:59 PM PDT 24
Peak memory 201056 kb
Host smart-8e40b4ee-6144-483c-b725-272e1c27937a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357274655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.2357274655
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.3731457219
Short name T376
Test name
Test status
Simulation time 139047702860 ps
CPU time 359.37 seconds
Started Aug 15 05:23:37 PM PDT 24
Finished Aug 15 05:29:36 PM PDT 24
Peak memory 201232 kb
Host smart-bdd59acf-84f7-4d7e-a71a-53234edc94b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731457219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.3731457219
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1138318484
Short name T391
Test name
Test status
Simulation time 61634690080 ps
CPU time 150.89 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:26:25 PM PDT 24
Peak memory 201388 kb
Host smart-e5bd5248-6d4a-4ab7-996e-086f0d991339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138318484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.1138318484
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3932902669
Short name T632
Test name
Test status
Simulation time 3022570930 ps
CPU time 2.39 seconds
Started Aug 15 05:23:38 PM PDT 24
Finished Aug 15 05:23:40 PM PDT 24
Peak memory 201060 kb
Host smart-6a82a6d4-9927-4e8a-9061-9d0e169a2b6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932902669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.3932902669
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.2833736036
Short name T716
Test name
Test status
Simulation time 3397160646 ps
CPU time 6.62 seconds
Started Aug 15 05:23:36 PM PDT 24
Finished Aug 15 05:23:43 PM PDT 24
Peak memory 201156 kb
Host smart-442495f7-d89b-4b9c-8dea-b19a42596a57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833736036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.2833736036
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.496572412
Short name T736
Test name
Test status
Simulation time 2610319715 ps
CPU time 7.05 seconds
Started Aug 15 05:25:36 PM PDT 24
Finished Aug 15 05:25:43 PM PDT 24
Peak memory 201108 kb
Host smart-01f9632c-3ffa-4112-8b1b-f73a41778fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496572412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.496572412
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2594389122
Short name T453
Test name
Test status
Simulation time 2453962823 ps
CPU time 7.88 seconds
Started Aug 15 05:23:37 PM PDT 24
Finished Aug 15 05:23:45 PM PDT 24
Peak memory 201056 kb
Host smart-37efbef2-6eab-4e13-8c30-cb56ed24f395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594389122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.2594389122
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2756536543
Short name T340
Test name
Test status
Simulation time 2223993877 ps
CPU time 1.89 seconds
Started Aug 15 05:23:48 PM PDT 24
Finished Aug 15 05:23:50 PM PDT 24
Peak memory 201040 kb
Host smart-de57e4b2-073a-4868-a47d-3ed0014fc3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756536543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.2756536543
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2742574053
Short name T527
Test name
Test status
Simulation time 2581326517 ps
CPU time 1.45 seconds
Started Aug 15 05:23:36 PM PDT 24
Finished Aug 15 05:23:38 PM PDT 24
Peak memory 201120 kb
Host smart-25c8302a-55be-4357-9b8a-87b0ec8f413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742574053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.2742574053
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.1336682697
Short name T611
Test name
Test status
Simulation time 2116734262 ps
CPU time 3.51 seconds
Started Aug 15 05:23:35 PM PDT 24
Finished Aug 15 05:23:39 PM PDT 24
Peak memory 201036 kb
Host smart-72b05ee7-d15e-40af-bbcd-81b318ad102b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336682697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.1336682697
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.2981848314
Short name T104
Test name
Test status
Simulation time 7422510560 ps
CPU time 19.03 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:24:10 PM PDT 24
Peak memory 201008 kb
Host smart-a6d00dcd-c30b-45d5-844b-ddcbb2d8b6d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981848314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.2981848314
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1102019256
Short name T325
Test name
Test status
Simulation time 4104189416 ps
CPU time 5.61 seconds
Started Aug 15 05:25:09 PM PDT 24
Finished Aug 15 05:25:15 PM PDT 24
Peak memory 201264 kb
Host smart-0e757542-85fa-4836-8014-b902e04eed42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102019256 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.1102019256
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2600218435
Short name T156
Test name
Test status
Simulation time 7722994238 ps
CPU time 2.34 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:23:54 PM PDT 24
Peak memory 201040 kb
Host smart-278533e2-f66a-4e08-96d9-de5fe5fb2e2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600218435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.2600218435
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.178921649
Short name T341
Test name
Test status
Simulation time 2032918253 ps
CPU time 1.81 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:23:56 PM PDT 24
Peak memory 201120 kb
Host smart-c04a6ccf-20fd-468c-8022-c5ef0686d866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178921649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_tes
t.178921649
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.180604228
Short name T720
Test name
Test status
Simulation time 3400356731 ps
CPU time 5.07 seconds
Started Aug 15 05:23:52 PM PDT 24
Finished Aug 15 05:23:58 PM PDT 24
Peak memory 201132 kb
Host smart-9be9957e-3b69-4b64-aad5-fc74dbe50c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180604228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.180604228
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.280275882
Short name T286
Test name
Test status
Simulation time 105245245177 ps
CPU time 278.99 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:28:31 PM PDT 24
Peak memory 201212 kb
Host smart-f405896c-3cf6-4ffd-aeeb-09b28705ab8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280275882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_combo_detect.280275882
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3958898797
Short name T775
Test name
Test status
Simulation time 25835131585 ps
CPU time 33.95 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:24:28 PM PDT 24
Peak memory 201256 kb
Host smart-c59a159e-c49e-4f0c-b59f-b1f2aa48d4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958898797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.3958898797
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2701712515
Short name T352
Test name
Test status
Simulation time 4818062095 ps
CPU time 6.48 seconds
Started Aug 15 05:23:52 PM PDT 24
Finished Aug 15 05:23:59 PM PDT 24
Peak memory 201072 kb
Host smart-a6395d0b-8982-4187-ac84-8e808da2a15b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701712515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.2701712515
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.666240278
Short name T442
Test name
Test status
Simulation time 2618918741 ps
CPU time 3.34 seconds
Started Aug 15 05:23:52 PM PDT 24
Finished Aug 15 05:23:55 PM PDT 24
Peak memory 201116 kb
Host smart-9948ccd1-3d7b-4dc3-8f7e-455b5e81ddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666240278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.666240278
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.3442254382
Short name T163
Test name
Test status
Simulation time 2485918725 ps
CPU time 2.38 seconds
Started Aug 15 05:23:53 PM PDT 24
Finished Aug 15 05:23:55 PM PDT 24
Peak memory 200724 kb
Host smart-111aa702-4c06-481b-b01f-79a4774aa754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442254382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.3442254382
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2744931975
Short name T464
Test name
Test status
Simulation time 2161072042 ps
CPU time 6.55 seconds
Started Aug 15 05:23:48 PM PDT 24
Finished Aug 15 05:23:54 PM PDT 24
Peak memory 200920 kb
Host smart-65f7723b-998f-4d64-b0de-935829b6d0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744931975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.2744931975
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1131863046
Short name T138
Test name
Test status
Simulation time 2511105622 ps
CPU time 7.57 seconds
Started Aug 15 05:23:52 PM PDT 24
Finished Aug 15 05:23:59 PM PDT 24
Peak memory 201112 kb
Host smart-e2823d21-aff7-42b8-88b7-1619841abfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131863046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1131863046
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.3833336291
Short name T440
Test name
Test status
Simulation time 2110968404 ps
CPU time 5.84 seconds
Started Aug 15 05:23:52 PM PDT 24
Finished Aug 15 05:23:58 PM PDT 24
Peak memory 201000 kb
Host smart-0e9f86a0-d8bb-416c-8eb7-f91398e3757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833336291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.3833336291
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.764746305
Short name T545
Test name
Test status
Simulation time 12904505039 ps
CPU time 28.61 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:24:20 PM PDT 24
Peak memory 201156 kb
Host smart-59c9d1c8-3580-4677-8d14-fa8dda619c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764746305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_st
ress_all.764746305
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2302773855
Short name T309
Test name
Test status
Simulation time 16514376562 ps
CPU time 9.68 seconds
Started Aug 15 05:23:56 PM PDT 24
Finished Aug 15 05:24:06 PM PDT 24
Peak memory 209560 kb
Host smart-bbb83168-5296-4dcc-8573-2960d5c7b137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302773855 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.2302773855
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.2027341458
Short name T585
Test name
Test status
Simulation time 2031810833 ps
CPU time 1.83 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:23:56 PM PDT 24
Peak memory 201092 kb
Host smart-a3838689-d6bb-4b63-a0a9-1ae9e904ac0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027341458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.2027341458
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1463925797
Short name T342
Test name
Test status
Simulation time 3569544882 ps
CPU time 10.18 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:24:02 PM PDT 24
Peak memory 201220 kb
Host smart-7bcf3a7a-7b8e-4799-8f64-0365d7f90cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463925797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.1
463925797
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.657737609
Short name T53
Test name
Test status
Simulation time 140891601187 ps
CPU time 186.37 seconds
Started Aug 15 05:23:50 PM PDT 24
Finished Aug 15 05:26:56 PM PDT 24
Peak memory 201216 kb
Host smart-9e9c9735-1c44-4eec-9c8b-0436ebd3f2d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657737609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_combo_detect.657737609
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2323595656
Short name T744
Test name
Test status
Simulation time 36516363572 ps
CPU time 97.19 seconds
Started Aug 15 05:23:50 PM PDT 24
Finished Aug 15 05:25:28 PM PDT 24
Peak memory 201352 kb
Host smart-cf84c486-e2fb-4076-ad03-c80cb0ee4318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323595656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.2323595656
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2620769385
Short name T327
Test name
Test status
Simulation time 2512497049 ps
CPU time 6.59 seconds
Started Aug 15 05:23:49 PM PDT 24
Finished Aug 15 05:23:56 PM PDT 24
Peak memory 201128 kb
Host smart-c2edf81b-9547-44ad-8fa4-e8ba4f890908
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620769385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.2620769385
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.886364304
Short name T208
Test name
Test status
Simulation time 3339673603 ps
CPU time 2.22 seconds
Started Aug 15 05:23:50 PM PDT 24
Finished Aug 15 05:23:52 PM PDT 24
Peak memory 201144 kb
Host smart-332ee65f-e545-4397-8206-1460ef5c24e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886364304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctr
l_edge_detect.886364304
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.526620128
Short name T705
Test name
Test status
Simulation time 2629947698 ps
CPU time 2.28 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:23:57 PM PDT 24
Peak memory 201080 kb
Host smart-a341495e-6f75-4e12-9902-5d400aa2fcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526620128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.526620128
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2646441441
Short name T769
Test name
Test status
Simulation time 2545191800 ps
CPU time 1.26 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:23:52 PM PDT 24
Peak memory 201112 kb
Host smart-66c033e7-048d-4733-81b4-a035e1705a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646441441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.2646441441
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2996835915
Short name T77
Test name
Test status
Simulation time 2051459480 ps
CPU time 1.82 seconds
Started Aug 15 05:23:56 PM PDT 24
Finished Aug 15 05:23:58 PM PDT 24
Peak memory 201040 kb
Host smart-211f11cf-53bb-49e7-81c9-4bbbc5decff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996835915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.2996835915
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1497418407
Short name T773
Test name
Test status
Simulation time 2514599350 ps
CPU time 3.66 seconds
Started Aug 15 05:23:52 PM PDT 24
Finished Aug 15 05:23:56 PM PDT 24
Peak memory 201132 kb
Host smart-70ab20d4-0f01-4609-8b72-6f9c85c74c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497418407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.1497418407
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.2905244640
Short name T547
Test name
Test status
Simulation time 2127342880 ps
CPU time 1.88 seconds
Started Aug 15 05:23:56 PM PDT 24
Finished Aug 15 05:23:58 PM PDT 24
Peak memory 201040 kb
Host smart-f6d8ab65-3dae-47bd-90be-28e09ee37ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905244640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.2905244640
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.4067128323
Short name T704
Test name
Test status
Simulation time 13719416948 ps
CPU time 9.53 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:24:03 PM PDT 24
Peak memory 201112 kb
Host smart-a47556ec-9280-46e5-84cd-bc501e8e2523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067128323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.4067128323
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3788512763
Short name T699
Test name
Test status
Simulation time 6022518542 ps
CPU time 16.51 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:24:08 PM PDT 24
Peak memory 209604 kb
Host smart-0d6c5d4b-1d32-47f9-abac-33658940067e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788512763 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.3788512763
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1172582236
Short name T153
Test name
Test status
Simulation time 2753472228 ps
CPU time 6.7 seconds
Started Aug 15 05:23:53 PM PDT 24
Finished Aug 15 05:24:00 PM PDT 24
Peak memory 201088 kb
Host smart-604646ee-f438-4d4f-9310-2f3f5ab81e32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172582236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.1172582236
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.2826822494
Short name T491
Test name
Test status
Simulation time 2016685850 ps
CPU time 5.4 seconds
Started Aug 15 05:23:56 PM PDT 24
Finished Aug 15 05:24:02 PM PDT 24
Peak memory 201096 kb
Host smart-e37e86ab-f7bf-4c48-a646-d325cf19f7d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826822494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.2826822494
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2565025599
Short name T770
Test name
Test status
Simulation time 42503655318 ps
CPU time 22.67 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:24:13 PM PDT 24
Peak memory 201136 kb
Host smart-416dd835-c25e-4c6d-844c-f9671a732ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565025599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.2
565025599
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.223011980
Short name T509
Test name
Test status
Simulation time 158926653336 ps
CPU time 84.29 seconds
Started Aug 15 05:23:53 PM PDT 24
Finished Aug 15 05:25:18 PM PDT 24
Peak memory 201100 kb
Host smart-ab63c343-291d-48a7-9eb9-08689ade9371
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223011980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_combo_detect.223011980
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1458995717
Short name T120
Test name
Test status
Simulation time 27600093187 ps
CPU time 17.26 seconds
Started Aug 15 05:23:52 PM PDT 24
Finished Aug 15 05:24:10 PM PDT 24
Peak memory 201348 kb
Host smart-94d30a10-ccf8-4e18-8afb-ee7256106383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458995717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.1458995717
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1558486539
Short name T501
Test name
Test status
Simulation time 3187701632 ps
CPU time 9.34 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:24:01 PM PDT 24
Peak memory 201028 kb
Host smart-af9109df-dc0b-401f-9dfc-85e9fd179af6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558486539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.1558486539
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.3716268937
Short name T92
Test name
Test status
Simulation time 2562415829 ps
CPU time 0.94 seconds
Started Aug 15 05:23:49 PM PDT 24
Finished Aug 15 05:23:50 PM PDT 24
Peak memory 201160 kb
Host smart-0c0aeceb-ab9a-4998-b1ed-fd8e898e209b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716268937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.3716268937
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.122216557
Short name T641
Test name
Test status
Simulation time 2668272554 ps
CPU time 1.18 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:23:53 PM PDT 24
Peak memory 201068 kb
Host smart-452d3db5-7bab-43a0-bb40-ecba2e424a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122216557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.122216557
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3411646535
Short name T484
Test name
Test status
Simulation time 2455193240 ps
CPU time 6.67 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:23:58 PM PDT 24
Peak memory 201036 kb
Host smart-97e9d8b7-d87d-49bb-8ac8-246c74c00827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411646535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.3411646535
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.2808948638
Short name T529
Test name
Test status
Simulation time 2183953942 ps
CPU time 2.04 seconds
Started Aug 15 05:23:56 PM PDT 24
Finished Aug 15 05:23:58 PM PDT 24
Peak memory 201328 kb
Host smart-5eeb2bfd-1b78-4823-b1f6-c85337af1544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808948638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.2808948638
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2956852573
Short name T499
Test name
Test status
Simulation time 2536046509 ps
CPU time 2.3 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:23:57 PM PDT 24
Peak memory 201044 kb
Host smart-c6b95ca7-7c9d-4e6e-85d2-23c28ca2db8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956852573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.2956852573
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.1584268144
Short name T605
Test name
Test status
Simulation time 2113446504 ps
CPU time 3.44 seconds
Started Aug 15 05:23:50 PM PDT 24
Finished Aug 15 05:23:54 PM PDT 24
Peak memory 201048 kb
Host smart-cd5b45e8-07c8-4e65-a409-e2ad4daabcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584268144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.1584268144
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.415155337
Short name T229
Test name
Test status
Simulation time 12784262978 ps
CPU time 32.99 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:24:27 PM PDT 24
Peak memory 201108 kb
Host smart-86fe40cc-a01f-4290-badc-bbf0a2ec025f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415155337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_st
ress_all.415155337
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3221864528
Short name T445
Test name
Test status
Simulation time 3806584351 ps
CPU time 9.82 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:24:04 PM PDT 24
Peak memory 201272 kb
Host smart-c70b74b0-d614-4898-903a-ad1f4749a284
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221864528 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.3221864528
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3745985966
Short name T114
Test name
Test status
Simulation time 2918241660 ps
CPU time 7.14 seconds
Started Aug 15 05:23:52 PM PDT 24
Finished Aug 15 05:24:00 PM PDT 24
Peak memory 201116 kb
Host smart-015a6a74-362a-412a-951e-464ed88ecd5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745985966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.3745985966
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.2526391832
Short name T737
Test name
Test status
Simulation time 2009525823 ps
CPU time 4.9 seconds
Started Aug 15 05:22:14 PM PDT 24
Finished Aug 15 05:22:19 PM PDT 24
Peak memory 201076 kb
Host smart-387e5dec-1ea0-4191-bb99-7928f3717478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526391832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.2526391832
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1108373434
Short name T613
Test name
Test status
Simulation time 3607305871 ps
CPU time 10.42 seconds
Started Aug 15 05:22:00 PM PDT 24
Finished Aug 15 05:22:16 PM PDT 24
Peak memory 201160 kb
Host smart-b809127b-3dc8-45ac-bab5-b9166bdf7b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108373434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.1108373434
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3811374752
Short name T375
Test name
Test status
Simulation time 119839013648 ps
CPU time 311.33 seconds
Started Aug 15 05:22:09 PM PDT 24
Finished Aug 15 05:27:20 PM PDT 24
Peak memory 201160 kb
Host smart-05767da6-40d6-4738-9a6d-ef56a1e70e57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811374752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.3811374752
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.282616865
Short name T392
Test name
Test status
Simulation time 93580373069 ps
CPU time 117.06 seconds
Started Aug 15 05:22:09 PM PDT 24
Finished Aug 15 05:24:06 PM PDT 24
Peak memory 201360 kb
Host smart-1be95d57-3330-406d-ba87-20b2853aef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282616865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wit
h_pre_cond.282616865
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.992832290
Short name T622
Test name
Test status
Simulation time 3631823919 ps
CPU time 5.52 seconds
Started Aug 15 05:22:08 PM PDT 24
Finished Aug 15 05:22:13 PM PDT 24
Peak memory 201088 kb
Host smart-076ecf6c-daf5-48af-83d2-35ef28f73543
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992832290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_ec_pwr_on_rst.992832290
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.877058493
Short name T202
Test name
Test status
Simulation time 2301243328 ps
CPU time 6.67 seconds
Started Aug 15 05:22:19 PM PDT 24
Finished Aug 15 05:22:26 PM PDT 24
Peak memory 201120 kb
Host smart-bbf5a87a-09d4-4db6-be7f-e007eff239cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877058493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl
_edge_detect.877058493
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3794758634
Short name T681
Test name
Test status
Simulation time 2609267981 ps
CPU time 7.47 seconds
Started Aug 15 05:22:13 PM PDT 24
Finished Aug 15 05:22:20 PM PDT 24
Peak memory 201092 kb
Host smart-0a1bd8bc-f9f8-445c-b7f6-298237aa26ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794758634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.3794758634
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2794322530
Short name T652
Test name
Test status
Simulation time 2481258572 ps
CPU time 2.35 seconds
Started Aug 15 05:22:08 PM PDT 24
Finished Aug 15 05:22:11 PM PDT 24
Peak memory 201112 kb
Host smart-b51ab239-e134-46b3-a18e-84392de06beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794322530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.2794322530
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2349347119
Short name T655
Test name
Test status
Simulation time 2249801603 ps
CPU time 6.51 seconds
Started Aug 15 05:22:06 PM PDT 24
Finished Aug 15 05:22:13 PM PDT 24
Peak memory 201128 kb
Host smart-349506d1-ac9e-4f59-be3b-1f595d965319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349347119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.2349347119
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.432659328
Short name T626
Test name
Test status
Simulation time 2512028498 ps
CPU time 7.28 seconds
Started Aug 15 05:22:04 PM PDT 24
Finished Aug 15 05:22:12 PM PDT 24
Peak memory 201060 kb
Host smart-7b9f9eba-3b57-4aea-bcb5-614be9def06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432659328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.432659328
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.499902141
Short name T240
Test name
Test status
Simulation time 2108980210 ps
CPU time 6.19 seconds
Started Aug 15 05:22:14 PM PDT 24
Finished Aug 15 05:22:20 PM PDT 24
Peak memory 201028 kb
Host smart-7174f815-3592-40f2-972b-1696608cf040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499902141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.499902141
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.1950467184
Short name T187
Test name
Test status
Simulation time 91356927920 ps
CPU time 142.6 seconds
Started Aug 15 05:22:19 PM PDT 24
Finished Aug 15 05:24:41 PM PDT 24
Peak memory 201204 kb
Host smart-576e5104-17ff-4b50-ac45-e9ca9b763c22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950467184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.1950467184
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3615701777
Short name T307
Test name
Test status
Simulation time 12985066370 ps
CPU time 9.44 seconds
Started Aug 15 05:22:18 PM PDT 24
Finished Aug 15 05:22:27 PM PDT 24
Peak memory 209548 kb
Host smart-1c64692c-4895-45c5-a118-3bd8c55e03ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615701777 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.3615701777
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2053935151
Short name T787
Test name
Test status
Simulation time 2651124070 ps
CPU time 5.91 seconds
Started Aug 15 05:22:04 PM PDT 24
Finished Aug 15 05:22:10 PM PDT 24
Peak memory 201116 kb
Host smart-8b15ca47-d279-4422-bc42-26f562377aba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053935151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.2053935151
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3889443305
Short name T254
Test name
Test status
Simulation time 23354585139 ps
CPU time 15.52 seconds
Started Aug 15 05:23:55 PM PDT 24
Finished Aug 15 05:24:10 PM PDT 24
Peak memory 201324 kb
Host smart-1afc372c-9dac-4f44-83eb-6694d2088b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889443305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.3889443305
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2334851339
Short name T106
Test name
Test status
Simulation time 33783105186 ps
CPU time 24.61 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:24:19 PM PDT 24
Peak memory 201256 kb
Host smart-c8c60f1b-d798-4d2f-86bf-fc704c6e78c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334851339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.2334851339
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3350371288
Short name T788
Test name
Test status
Simulation time 69722246264 ps
CPU time 170.99 seconds
Started Aug 15 05:23:56 PM PDT 24
Finished Aug 15 05:26:47 PM PDT 24
Peak memory 201212 kb
Host smart-873edc47-640a-4b58-be7c-fe7f6adc3e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350371288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.3350371288
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.105901152
Short name T725
Test name
Test status
Simulation time 34318265738 ps
CPU time 13.19 seconds
Started Aug 15 05:23:50 PM PDT 24
Finished Aug 15 05:24:03 PM PDT 24
Peak memory 201572 kb
Host smart-a1aaa9aa-b7a3-48fa-9761-5b89dcb5dd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105901152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_wi
th_pre_cond.105901152
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2977471451
Short name T401
Test name
Test status
Simulation time 43516270244 ps
CPU time 55.61 seconds
Started Aug 15 05:23:56 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 201300 kb
Host smart-52e36d56-4158-465f-8724-af53aa6a6a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977471451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.2977471451
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.700264157
Short name T139
Test name
Test status
Simulation time 73822416016 ps
CPU time 41.95 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:24:33 PM PDT 24
Peak memory 201220 kb
Host smart-b4354608-bb26-49ab-a693-a1cd3d9c1ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700264157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_wi
th_pre_cond.700264157
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.730511068
Short name T397
Test name
Test status
Simulation time 84533300114 ps
CPU time 38.4 seconds
Started Aug 15 05:23:56 PM PDT 24
Finished Aug 15 05:24:34 PM PDT 24
Peak memory 201276 kb
Host smart-1cb9f961-3eb5-431d-903d-eb6bf77925fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730511068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_wi
th_pre_cond.730511068
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.1643625287
Short name T581
Test name
Test status
Simulation time 2039622576 ps
CPU time 1.75 seconds
Started Aug 15 05:22:18 PM PDT 24
Finished Aug 15 05:22:20 PM PDT 24
Peak memory 201096 kb
Host smart-40b2c515-19d2-411c-99b0-19a8b01f3e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643625287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.1643625287
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1926938232
Short name T757
Test name
Test status
Simulation time 3863405977 ps
CPU time 10.89 seconds
Started Aug 15 05:22:14 PM PDT 24
Finished Aug 15 05:22:25 PM PDT 24
Peak memory 201144 kb
Host smart-75e7fa1d-041b-4ccf-8aa4-2e1471cdbc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926938232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.1926938232
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.570806077
Short name T281
Test name
Test status
Simulation time 146011773674 ps
CPU time 145.6 seconds
Started Aug 15 05:22:22 PM PDT 24
Finished Aug 15 05:24:48 PM PDT 24
Peak memory 201216 kb
Host smart-8da5d216-f284-4cd2-83c2-6716f7b081c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570806077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_combo_detect.570806077
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3801876761
Short name T244
Test name
Test status
Simulation time 91572176829 ps
CPU time 237.16 seconds
Started Aug 15 05:22:23 PM PDT 24
Finished Aug 15 05:26:21 PM PDT 24
Peak memory 201356 kb
Host smart-e44b0bda-ea4b-4011-a5e0-23da53ae4968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801876761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.3801876761
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.437251893
Short name T454
Test name
Test status
Simulation time 3756652345 ps
CPU time 5.1 seconds
Started Aug 15 05:22:15 PM PDT 24
Finished Aug 15 05:22:20 PM PDT 24
Peak memory 201076 kb
Host smart-66ce909a-297c-4f0e-9377-7f62eda83546
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437251893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_ec_pwr_on_rst.437251893
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3145116641
Short name T448
Test name
Test status
Simulation time 2829119280 ps
CPU time 1.11 seconds
Started Aug 15 05:22:13 PM PDT 24
Finished Aug 15 05:22:14 PM PDT 24
Peak memory 201112 kb
Host smart-8fb3fd3c-723e-4518-a6c3-d150d101be65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145116641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3145116641
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1113949326
Short name T670
Test name
Test status
Simulation time 2480048714 ps
CPU time 2.79 seconds
Started Aug 15 05:22:05 PM PDT 24
Finished Aug 15 05:22:08 PM PDT 24
Peak memory 201092 kb
Host smart-e4b275ea-3a8e-434f-bec3-0b24519decfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113949326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.1113949326
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.160076016
Short name T616
Test name
Test status
Simulation time 2187087284 ps
CPU time 3.71 seconds
Started Aug 15 05:22:17 PM PDT 24
Finished Aug 15 05:22:21 PM PDT 24
Peak memory 201108 kb
Host smart-ca77c925-e97e-40d1-82ff-84dafc05d009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160076016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.160076016
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.963436894
Short name T735
Test name
Test status
Simulation time 2511642408 ps
CPU time 6.86 seconds
Started Aug 15 05:22:20 PM PDT 24
Finished Aug 15 05:22:27 PM PDT 24
Peak memory 201076 kb
Host smart-8572b6dc-2624-4c57-95d1-154a56efa5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963436894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.963436894
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.3874531598
Short name T766
Test name
Test status
Simulation time 2108622859 ps
CPU time 5.68 seconds
Started Aug 15 05:22:22 PM PDT 24
Finished Aug 15 05:22:28 PM PDT 24
Peak memory 200976 kb
Host smart-0a3c3d93-d178-49d5-9a92-a78611850e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874531598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.3874531598
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3146606770
Short name T461
Test name
Test status
Simulation time 19948697809 ps
CPU time 5.29 seconds
Started Aug 15 05:22:17 PM PDT 24
Finished Aug 15 05:22:22 PM PDT 24
Peak memory 201484 kb
Host smart-697c779d-f550-473b-8ba3-176ed320130d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146606770 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.3146606770
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1247420931
Short name T267
Test name
Test status
Simulation time 489064215479 ps
CPU time 68.3 seconds
Started Aug 15 05:22:05 PM PDT 24
Finished Aug 15 05:23:14 PM PDT 24
Peak memory 201100 kb
Host smart-85d60b05-a9f1-4420-ae77-b695fd4678d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247420931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.1247420931
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.217209914
Short name T245
Test name
Test status
Simulation time 51497365110 ps
CPU time 136.79 seconds
Started Aug 15 05:23:50 PM PDT 24
Finished Aug 15 05:26:07 PM PDT 24
Peak memory 201312 kb
Host smart-81b900a6-ac0c-4189-abd9-a563a5aebaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217209914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_wi
th_pre_cond.217209914
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3394010592
Short name T387
Test name
Test status
Simulation time 79263034095 ps
CPU time 133.62 seconds
Started Aug 15 05:23:53 PM PDT 24
Finished Aug 15 05:26:07 PM PDT 24
Peak memory 201396 kb
Host smart-ffa043b9-3f3e-475b-a0fc-083ad56d887c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394010592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.3394010592
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3609773682
Short name T495
Test name
Test status
Simulation time 48988654549 ps
CPU time 115.7 seconds
Started Aug 15 05:23:50 PM PDT 24
Finished Aug 15 05:25:46 PM PDT 24
Peak memory 201332 kb
Host smart-c5531fef-48cf-47eb-a6d4-8012c68ef005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609773682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.3609773682
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.941644910
Short name T126
Test name
Test status
Simulation time 25829764934 ps
CPU time 66.02 seconds
Started Aug 15 05:23:48 PM PDT 24
Finished Aug 15 05:24:54 PM PDT 24
Peak memory 201196 kb
Host smart-686b9359-7de9-43cf-ba8c-6ff263c73df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941644910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_wi
th_pre_cond.941644910
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1518259694
Short name T122
Test name
Test status
Simulation time 24340058692 ps
CPU time 33.59 seconds
Started Aug 15 05:23:55 PM PDT 24
Finished Aug 15 05:24:29 PM PDT 24
Peak memory 201364 kb
Host smart-e8e39dd2-73b4-4e4b-b1de-336600181cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518259694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.1518259694
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.415657747
Short name T125
Test name
Test status
Simulation time 27582989502 ps
CPU time 67.94 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:25:02 PM PDT 24
Peak memory 201212 kb
Host smart-983ec79a-160a-4426-9374-a5ad2dffae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415657747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_wi
th_pre_cond.415657747
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.2033730213
Short name T433
Test name
Test status
Simulation time 2019417492 ps
CPU time 3.36 seconds
Started Aug 15 05:22:25 PM PDT 24
Finished Aug 15 05:22:28 PM PDT 24
Peak memory 201116 kb
Host smart-512469c6-c8b2-4ba2-af74-22c68f8b2846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033730213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.2033730213
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2823822969
Short name T535
Test name
Test status
Simulation time 3678259181 ps
CPU time 1.27 seconds
Started Aug 15 05:22:14 PM PDT 24
Finished Aug 15 05:22:16 PM PDT 24
Peak memory 201092 kb
Host smart-0c2557c6-51dd-463e-9cfa-b52ec43e4772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823822969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.2823822969
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.3892517642
Short name T161
Test name
Test status
Simulation time 77103175889 ps
CPU time 172.36 seconds
Started Aug 15 05:22:09 PM PDT 24
Finished Aug 15 05:25:02 PM PDT 24
Peak memory 201308 kb
Host smart-28d4ab07-61bf-445a-9448-cc3c47474877
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892517642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.3892517642
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.517609951
Short name T410
Test name
Test status
Simulation time 58183494703 ps
CPU time 156.79 seconds
Started Aug 15 05:22:09 PM PDT 24
Finished Aug 15 05:24:46 PM PDT 24
Peak memory 201336 kb
Host smart-92b1da1c-e323-4373-8dee-950b0804b6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517609951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wit
h_pre_cond.517609951
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.942293854
Short name T635
Test name
Test status
Simulation time 4131356281 ps
CPU time 4.83 seconds
Started Aug 15 05:22:15 PM PDT 24
Finished Aug 15 05:22:20 PM PDT 24
Peak memory 201120 kb
Host smart-4b231512-1a85-4844-8b81-e54a793bd2ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942293854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_ec_pwr_on_rst.942293854
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2750029917
Short name T174
Test name
Test status
Simulation time 5279488754 ps
CPU time 7.08 seconds
Started Aug 15 05:22:14 PM PDT 24
Finished Aug 15 05:22:21 PM PDT 24
Peak memory 200996 kb
Host smart-5884285c-1935-4202-9c95-43c5fcf13c4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750029917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.2750029917
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.128414669
Short name T551
Test name
Test status
Simulation time 2628035325 ps
CPU time 2.34 seconds
Started Aug 15 05:22:12 PM PDT 24
Finished Aug 15 05:22:15 PM PDT 24
Peak memory 201148 kb
Host smart-dc2154d0-86ba-45be-b7ca-0f12df3ab9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128414669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.128414669
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.4175899512
Short name T500
Test name
Test status
Simulation time 2469876247 ps
CPU time 4.16 seconds
Started Aug 15 05:22:24 PM PDT 24
Finished Aug 15 05:22:28 PM PDT 24
Peak memory 201028 kb
Host smart-4707efd7-7760-43d1-a38a-3df87cb0ee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175899512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.4175899512
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1935294005
Short name T677
Test name
Test status
Simulation time 2061781440 ps
CPU time 6.19 seconds
Started Aug 15 05:22:14 PM PDT 24
Finished Aug 15 05:22:21 PM PDT 24
Peak memory 201040 kb
Host smart-4fbb3e59-2f34-4b10-b723-47c61599e1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935294005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1935294005
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.586892577
Short name T576
Test name
Test status
Simulation time 2535154210 ps
CPU time 2.46 seconds
Started Aug 15 05:22:25 PM PDT 24
Finished Aug 15 05:22:27 PM PDT 24
Peak memory 201112 kb
Host smart-c0a277b7-3b1f-469e-a52f-9300dcf534e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586892577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.586892577
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.332406518
Short name T428
Test name
Test status
Simulation time 2110421908 ps
CPU time 5.97 seconds
Started Aug 15 05:22:21 PM PDT 24
Finished Aug 15 05:22:27 PM PDT 24
Peak memory 201016 kb
Host smart-bc2ece61-f301-4e6b-a836-96db51974ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332406518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.332406518
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.1007983758
Short name T205
Test name
Test status
Simulation time 13387793111 ps
CPU time 34.92 seconds
Started Aug 15 05:22:14 PM PDT 24
Finished Aug 15 05:22:49 PM PDT 24
Peak memory 201080 kb
Host smart-241352c6-36ba-4678-a6ec-c6bb67129e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007983758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.1007983758
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2053950848
Short name T192
Test name
Test status
Simulation time 7566968934 ps
CPU time 5.28 seconds
Started Aug 15 05:22:11 PM PDT 24
Finished Aug 15 05:22:17 PM PDT 24
Peak memory 201248 kb
Host smart-951071f0-29c1-4726-b56a-0fa793ebb8c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053950848 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.2053950848
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1001027243
Short name T403
Test name
Test status
Simulation time 44202468902 ps
CPU time 17.82 seconds
Started Aug 15 05:23:55 PM PDT 24
Finished Aug 15 05:24:13 PM PDT 24
Peak memory 201304 kb
Host smart-5ba7305a-15f2-4718-b9d2-6be59a97efc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001027243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.1001027243
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2693416792
Short name T478
Test name
Test status
Simulation time 30081733993 ps
CPU time 79.7 seconds
Started Aug 15 05:23:53 PM PDT 24
Finished Aug 15 05:25:12 PM PDT 24
Peak memory 201264 kb
Host smart-d437227a-c1cc-4fb0-8193-e1c473f3769a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693416792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.2693416792
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2720137673
Short name T288
Test name
Test status
Simulation time 26084360872 ps
CPU time 54.5 seconds
Started Aug 15 05:23:56 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 201356 kb
Host smart-a6154390-6dd0-49dd-a794-80e8c91101fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720137673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.2720137673
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2378981993
Short name T758
Test name
Test status
Simulation time 114316815657 ps
CPU time 294.83 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:28:46 PM PDT 24
Peak memory 201244 kb
Host smart-fca42a23-3675-4f6f-9d38-36b730b0e306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378981993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.2378981993
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4137544780
Short name T414
Test name
Test status
Simulation time 82566246417 ps
CPU time 196.41 seconds
Started Aug 15 05:23:51 PM PDT 24
Finished Aug 15 05:27:08 PM PDT 24
Peak memory 201300 kb
Host smart-02ce4000-5d91-4ebb-8f7d-c97c06913e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137544780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.4137544780
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.4145642231
Short name T94
Test name
Test status
Simulation time 65408366562 ps
CPU time 32.85 seconds
Started Aug 15 05:23:47 PM PDT 24
Finished Aug 15 05:24:20 PM PDT 24
Peak memory 201312 kb
Host smart-f1a15d96-b543-4d16-b76e-8d137f72ee1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145642231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.4145642231
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.659004478
Short name T98
Test name
Test status
Simulation time 45143540256 ps
CPU time 21.55 seconds
Started Aug 15 05:23:50 PM PDT 24
Finished Aug 15 05:24:12 PM PDT 24
Peak memory 201304 kb
Host smart-7cda5a05-bedc-493a-9b96-0624b567ef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659004478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_wi
th_pre_cond.659004478
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.3248212943
Short name T141
Test name
Test status
Simulation time 2009439061 ps
CPU time 4.85 seconds
Started Aug 15 05:22:17 PM PDT 24
Finished Aug 15 05:22:22 PM PDT 24
Peak memory 201100 kb
Host smart-7e210bf9-bf85-444c-a836-035c94997398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248212943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.3248212943
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3989548049
Short name T58
Test name
Test status
Simulation time 3750980730 ps
CPU time 5.55 seconds
Started Aug 15 05:22:13 PM PDT 24
Finished Aug 15 05:22:19 PM PDT 24
Peak memory 201152 kb
Host smart-ae2d5fe1-1d94-4f43-be14-6a3281f3311b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989548049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.3989548049
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.3071974687
Short name T683
Test name
Test status
Simulation time 81410709111 ps
CPU time 46.43 seconds
Started Aug 15 05:22:21 PM PDT 24
Finished Aug 15 05:23:07 PM PDT 24
Peak memory 201196 kb
Host smart-4e5982dd-76f9-442a-b08b-81c7e3838e49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071974687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.3071974687
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2719566023
Short name T738
Test name
Test status
Simulation time 57682829683 ps
CPU time 153.18 seconds
Started Aug 15 05:22:13 PM PDT 24
Finished Aug 15 05:24:47 PM PDT 24
Peak memory 201360 kb
Host smart-032bfb54-36f7-44f5-91ca-d3c660b2999d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719566023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.2719566023
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1832211205
Short name T476
Test name
Test status
Simulation time 3350045220 ps
CPU time 4.89 seconds
Started Aug 15 05:22:09 PM PDT 24
Finished Aug 15 05:22:14 PM PDT 24
Peak memory 200912 kb
Host smart-d9e8a3f5-a5b1-410a-bd27-864db816b87d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832211205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.1832211205
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.4158840061
Short name T692
Test name
Test status
Simulation time 2625855924 ps
CPU time 2.27 seconds
Started Aug 15 05:22:12 PM PDT 24
Finished Aug 15 05:22:15 PM PDT 24
Peak memory 201108 kb
Host smart-51d517ec-416a-4e74-846d-2f2939ae81c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158840061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.4158840061
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1954156166
Short name T691
Test name
Test status
Simulation time 2534245032 ps
CPU time 1.38 seconds
Started Aug 15 05:22:13 PM PDT 24
Finished Aug 15 05:22:15 PM PDT 24
Peak memory 201140 kb
Host smart-45a7cc2f-de4d-4fd3-a4d9-136645a26501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954156166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1954156166
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3499168085
Short name T764
Test name
Test status
Simulation time 2199566336 ps
CPU time 2.03 seconds
Started Aug 15 05:22:12 PM PDT 24
Finished Aug 15 05:22:14 PM PDT 24
Peak memory 201080 kb
Host smart-ce174f44-2cfb-4541-a902-99b3798dfb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499168085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.3499168085
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1877184943
Short name T645
Test name
Test status
Simulation time 2540034281 ps
CPU time 2.35 seconds
Started Aug 15 05:22:14 PM PDT 24
Finished Aug 15 05:22:17 PM PDT 24
Peak memory 201040 kb
Host smart-0db7326e-8b5f-4597-8d0f-286c815e1618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877184943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.1877184943
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.168632072
Short name T783
Test name
Test status
Simulation time 2115322377 ps
CPU time 4.53 seconds
Started Aug 15 05:22:15 PM PDT 24
Finished Aug 15 05:22:20 PM PDT 24
Peak memory 201020 kb
Host smart-744f8328-37ce-411f-929b-5e4a1993361c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168632072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.168632072
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.1885061292
Short name T343
Test name
Test status
Simulation time 85810306483 ps
CPU time 226.17 seconds
Started Aug 15 05:22:22 PM PDT 24
Finished Aug 15 05:26:08 PM PDT 24
Peak memory 201208 kb
Host smart-ce76c0b3-169e-4aba-9d26-735ddb4e7eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885061292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.1885061292
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.124798270
Short name T614
Test name
Test status
Simulation time 5634912804 ps
CPU time 6.76 seconds
Started Aug 15 05:22:10 PM PDT 24
Finished Aug 15 05:22:17 PM PDT 24
Peak memory 201132 kb
Host smart-c36d1a71-1c69-4ec2-b13f-330535aa5846
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124798270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_ultra_low_pwr.124798270
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.687572950
Short name T507
Test name
Test status
Simulation time 43928305203 ps
CPU time 106.37 seconds
Started Aug 15 05:23:53 PM PDT 24
Finished Aug 15 05:25:40 PM PDT 24
Peak memory 201324 kb
Host smart-b9f3869b-db69-482c-8109-744ae2a520cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687572950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_wi
th_pre_cond.687572950
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1592361813
Short name T771
Test name
Test status
Simulation time 63078669964 ps
CPU time 33.43 seconds
Started Aug 15 05:25:25 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 201312 kb
Host smart-a28ef107-ee26-4797-9165-7bf309d615a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592361813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.1592361813
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3022365107
Short name T792
Test name
Test status
Simulation time 92211572547 ps
CPU time 235.86 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:27:50 PM PDT 24
Peak memory 201348 kb
Host smart-0e8ea41f-f0d2-433b-851d-2080ca28d37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022365107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.3022365107
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1858877361
Short name T550
Test name
Test status
Simulation time 25601798654 ps
CPU time 18.7 seconds
Started Aug 15 05:23:53 PM PDT 24
Finished Aug 15 05:24:11 PM PDT 24
Peak memory 200968 kb
Host smart-e402aae0-e821-4db4-b05c-a0bdef3299b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858877361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.1858877361
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3741793074
Short name T555
Test name
Test status
Simulation time 27078131608 ps
CPU time 70.17 seconds
Started Aug 15 05:23:48 PM PDT 24
Finished Aug 15 05:24:58 PM PDT 24
Peak memory 201288 kb
Host smart-520bc301-5962-4bda-8fa6-78ce8d805e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741793074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.3741793074
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3597612935
Short name T722
Test name
Test status
Simulation time 52362786417 ps
CPU time 46.19 seconds
Started Aug 15 05:23:55 PM PDT 24
Finished Aug 15 05:24:41 PM PDT 24
Peak memory 201260 kb
Host smart-ad74139d-bd0f-4aef-9ce7-f62e6a954d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597612935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.3597612935
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1595444189
Short name T350
Test name
Test status
Simulation time 91064643141 ps
CPU time 209.78 seconds
Started Aug 15 05:23:59 PM PDT 24
Finished Aug 15 05:27:29 PM PDT 24
Peak memory 201284 kb
Host smart-5e02467a-b39c-4507-a44e-7d6d1dc91825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595444189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.1595444189
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1040460267
Short name T573
Test name
Test status
Simulation time 66363146759 ps
CPU time 40.54 seconds
Started Aug 15 05:23:53 PM PDT 24
Finished Aug 15 05:24:34 PM PDT 24
Peak memory 201336 kb
Host smart-798c15e8-bfb3-43da-924e-23cfdadd8f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040460267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.1040460267
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.246029167
Short name T124
Test name
Test status
Simulation time 110359922788 ps
CPU time 50.08 seconds
Started Aug 15 05:23:53 PM PDT 24
Finished Aug 15 05:24:44 PM PDT 24
Peak memory 201276 kb
Host smart-76511449-c05c-4fd7-8342-fc091639e251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246029167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_wi
th_pre_cond.246029167
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.3321752839
Short name T731
Test name
Test status
Simulation time 2029364488 ps
CPU time 3.09 seconds
Started Aug 15 05:22:43 PM PDT 24
Finished Aug 15 05:22:46 PM PDT 24
Peak memory 201116 kb
Host smart-518a3a16-9f07-43d1-856a-b0aed5c1dc80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321752839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.3321752839
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3958252632
Short name T707
Test name
Test status
Simulation time 3252394013 ps
CPU time 2.02 seconds
Started Aug 15 05:22:31 PM PDT 24
Finished Aug 15 05:22:33 PM PDT 24
Peak memory 201180 kb
Host smart-b140328f-2ed7-4f97-8b10-82ab7d9e0098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958252632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.3958252632
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3946878919
Short name T382
Test name
Test status
Simulation time 132137294922 ps
CPU time 173.49 seconds
Started Aug 15 05:22:30 PM PDT 24
Finished Aug 15 05:25:24 PM PDT 24
Peak memory 201212 kb
Host smart-003e4b65-0990-4f7f-8640-302d367f3717
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946878919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.3946878919
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.252589339
Short name T742
Test name
Test status
Simulation time 5165698609 ps
CPU time 14.41 seconds
Started Aug 15 05:22:28 PM PDT 24
Finished Aug 15 05:22:42 PM PDT 24
Peak memory 201076 kb
Host smart-84509526-e262-4f0e-81fa-6f045a8b3957
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252589339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_ec_pwr_on_rst.252589339
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.2339414729
Short name T169
Test name
Test status
Simulation time 3875527680 ps
CPU time 1.37 seconds
Started Aug 15 05:22:32 PM PDT 24
Finished Aug 15 05:22:34 PM PDT 24
Peak memory 201132 kb
Host smart-53a66b15-0d4d-41e9-9a5b-2a899a39b799
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339414729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.2339414729
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3458875484
Short name T676
Test name
Test status
Simulation time 2628161052 ps
CPU time 2.35 seconds
Started Aug 15 05:22:23 PM PDT 24
Finished Aug 15 05:22:25 PM PDT 24
Peak memory 201128 kb
Host smart-0d657558-8027-472a-ba67-0ffe2abc4e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458875484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.3458875484
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3773194007
Short name T791
Test name
Test status
Simulation time 2452865634 ps
CPU time 7.23 seconds
Started Aug 15 05:22:15 PM PDT 24
Finished Aug 15 05:22:22 PM PDT 24
Peak memory 201108 kb
Host smart-009303a7-38e3-4554-86d0-7f998172e46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773194007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.3773194007
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.4212657822
Short name T160
Test name
Test status
Simulation time 2258062276 ps
CPU time 2.8 seconds
Started Aug 15 05:22:11 PM PDT 24
Finished Aug 15 05:22:14 PM PDT 24
Peak memory 201060 kb
Host smart-c74caced-9386-4356-9c96-e5c380fb0d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212657822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.4212657822
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2951611922
Short name T727
Test name
Test status
Simulation time 2547732656 ps
CPU time 1.95 seconds
Started Aug 15 05:22:08 PM PDT 24
Finished Aug 15 05:22:11 PM PDT 24
Peak memory 201128 kb
Host smart-eaefdb8a-cd1a-46c7-941b-1dc219800d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951611922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.2951611922
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.1163564188
Short name T541
Test name
Test status
Simulation time 2126858454 ps
CPU time 2 seconds
Started Aug 15 05:22:27 PM PDT 24
Finished Aug 15 05:22:29 PM PDT 24
Peak memory 201036 kb
Host smart-41a1f9c9-316d-4b50-9d76-dd2610528bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163564188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.1163564188
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.1805308960
Short name T287
Test name
Test status
Simulation time 40361992484 ps
CPU time 29.99 seconds
Started Aug 15 05:22:28 PM PDT 24
Finished Aug 15 05:22:58 PM PDT 24
Peak memory 201440 kb
Host smart-302b82de-7db4-41d3-a50d-8b079ff90f89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805308960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.1805308960
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3044002831
Short name T322
Test name
Test status
Simulation time 5496091488 ps
CPU time 14.92 seconds
Started Aug 15 05:22:29 PM PDT 24
Finished Aug 15 05:22:44 PM PDT 24
Peak memory 201316 kb
Host smart-8bbaccf3-d69d-4bc8-ad16-240b3578198f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044002831 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.3044002831
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.748843335
Short name T115
Test name
Test status
Simulation time 6301237063 ps
CPU time 4.19 seconds
Started Aug 15 05:22:30 PM PDT 24
Finished Aug 15 05:22:35 PM PDT 24
Peak memory 201084 kb
Host smart-054b9be4-1e0f-42d5-9168-5dac83b799d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748843335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_ultra_low_pwr.748843335
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.4063536872
Short name T785
Test name
Test status
Simulation time 104578367262 ps
CPU time 15.45 seconds
Started Aug 15 05:24:05 PM PDT 24
Finished Aug 15 05:24:21 PM PDT 24
Peak memory 201272 kb
Host smart-c11ba88c-4cf9-4cfd-835e-782b50947801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063536872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.4063536872
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.720001513
Short name T380
Test name
Test status
Simulation time 84960394313 ps
CPU time 107.3 seconds
Started Aug 15 05:23:55 PM PDT 24
Finished Aug 15 05:25:43 PM PDT 24
Peak memory 201272 kb
Host smart-734d3d41-e929-4539-b557-ce5a435f05df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720001513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_wi
th_pre_cond.720001513
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2301511767
Short name T717
Test name
Test status
Simulation time 47257446065 ps
CPU time 115.04 seconds
Started Aug 15 05:23:53 PM PDT 24
Finished Aug 15 05:25:48 PM PDT 24
Peak memory 201288 kb
Host smart-a8d2ee3d-f454-458e-90a5-249b3ca70759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301511767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.2301511767
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2349089469
Short name T607
Test name
Test status
Simulation time 27847515341 ps
CPU time 36.76 seconds
Started Aug 15 05:23:56 PM PDT 24
Finished Aug 15 05:24:33 PM PDT 24
Peak memory 201268 kb
Host smart-915e87c0-ef15-4183-9e5c-bfce73bbd5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349089469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.2349089469
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2331353044
Short name T383
Test name
Test status
Simulation time 98204698896 ps
CPU time 124.95 seconds
Started Aug 15 05:23:54 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 201276 kb
Host smart-4c551aee-cdd3-4aa3-9b66-43d5197d14d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331353044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.2331353044
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.839047696
Short name T275
Test name
Test status
Simulation time 59220389991 ps
CPU time 112.48 seconds
Started Aug 15 05:23:56 PM PDT 24
Finished Aug 15 05:25:49 PM PDT 24
Peak memory 201304 kb
Host smart-d010990b-dc55-453f-bd94-c737e43699df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839047696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_wi
th_pre_cond.839047696
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3043055333
Short name T658
Test name
Test status
Simulation time 25590271994 ps
CPU time 35.55 seconds
Started Aug 15 05:24:00 PM PDT 24
Finished Aug 15 05:24:36 PM PDT 24
Peak memory 201300 kb
Host smart-5bdb95a0-3d3e-4cee-b3e3-1cd8dc386c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043055333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.3043055333
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3103821945
Short name T394
Test name
Test status
Simulation time 109899003307 ps
CPU time 290.96 seconds
Started Aug 15 05:23:56 PM PDT 24
Finished Aug 15 05:28:47 PM PDT 24
Peak memory 201332 kb
Host smart-1cb80389-b3b7-40f5-91dc-90f3c48db478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103821945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.3103821945
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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