Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2028

1

T2

4

T3

28

T7

42

auto[1]

545

1

T2

6

T7

2

T45

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1991

1

T2

10

T3

21

T7

40

auto[1]

582

1

T3

7

T7

4

T45

12

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1983

1

T2

4

T3

28

T7

33

auto[1]

590

1

T2

6

T7

11

T8

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1890

1

T3

21

T7

44

T45

21

auto[1]

683

1

T2

10

T3

7

T45

7

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2373

1

T2

10

T3

21

T7

42

auto[1]

200

1

T3

7

T7

2

T8

6

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2284

1

T2

10

T3

28

T7

37

auto[1]

289

1

T7

7

T45

2

T8

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2315

1

T2

10

T3

21

T7

44

auto[1]

258

1

T3

7

T45

14

T47

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2365

1

T2

10

T3

28

T7

22

auto[1]

208

1

T7

22

T59

13

T237

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2306

1

T2

10

T3

28

T7

40

auto[1]

267

1

T7

4

T45

7

T47

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1964

1

T2

4

T3

28

T7

37

auto[1]

609

1

T2

6

T7

7

T45

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

764

1

T2

10

T10

32

T63

7

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

36

1

T8

4

T46

1

T60

14

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

82

1

T47

1

T59

7

T301

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T365

2

T366

1

T250

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T7

11

T59

8

T367

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T251

1

T368

7

T359

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

38

1

T7

2

T237

2

T366

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T7

2

-

-

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

61

1

T45

2

T47

1

T32

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

14

1

T3

7

T347

1

T250

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T45

2

T237

2

T365

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T88

1

T252

2

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

2

1

T369

1

T87

1

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T238

4

T370

1

T358

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T357

1

T254

1

T257

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

80

1

T8

3

T59

10

T60

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T301

4

T352

3

T353

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

27

1

T238

2

T371

1

T358

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T353

2

T362

1

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

25

1

T7

7

T238

5

T347

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T59

3

T238

3

T255

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1

1

T359

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T301

4

T359

2

T352

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T372

2

T373

1

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

13

1

T45

2

T346

2

T254

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

17

1

T368

2

T352

3

T358

6

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

87

1

T8

3

T256

3

T252

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

95

1

T7

7

T33

10

T205

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

50

1

T59

8

T237

5

T52

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

92

1

T47

1

T301

4

T88

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

84

1

T45

2

T63

2

T126

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

53

1

T2

4

T63

5

T33

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T84

6

T352

4

T374

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

118

1

T7

11

T46

1

T10

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T375

2

T359

1

T104

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T60

8

T238

8

T251

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

26

1

T126

5

T239

7

T116

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

95

1

T8

2

T10

5

T60

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T2

4

T85

1

T111

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21

1

T59

10

T376

3

T377

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T2

2

T34

2

T101

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

78

1

T7

2

T238

4

T366

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

51

1

T7

2

T239

7

T52

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

69

1

T45

2

T8

2

T10

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

12

1

T60

3

T378

4

T379

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

87

1

T3

7

T84

6

T365

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T45

2

T233

4

T111

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T116

2

T380

3

T345

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T32

2

T33

1

T99

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

34

1

T301

7

T381

6

T250

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

32

1

T33

2

T237

2

T34

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

27

1

T34

5

T380

4

T260

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T126

4

T34

3

T240

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

22

1

T10

5

T60

7

T116

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T47

1

T59

7

T344

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T374

2

T263

1

T351

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T101

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded