Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

632

1

T4

11

T26

12

T25

17

auto[1]

608

1

T4

9

T26

8

T25

3

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

295

1

T4

4

T26

5

T25

5

from_0to1

303

1

T4

4

T26

6

T25

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

629

1

T4

9

T26

13

T25

10

auto[1]

611

1

T4

11

T26

7

T25

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

629

1

T4

7

T26

12

T25

10

auto[1]

611

1

T4

13

T26

8

T25

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

35

1

T26

1

T25

2

T74

1

auto[0]

from_1to0

auto[0]

auto[1]

38

1

T26

1

T25

1

T74

1

auto[0]

from_1to0

auto[1]

auto[0]

38

1

T4

1

T26

1

T25

1

auto[0]

from_1to0

auto[1]

auto[1]

32

1

T4

1

T308

1

T57

1

auto[0]

from_0to1

auto[0]

auto[0]

39

1

T25

1

T78

2

T79

2

auto[0]

from_0to1

auto[0]

auto[1]

42

1

T4

1

T25

3

T79

1

auto[0]

from_0to1

auto[1]

auto[0]

36

1

T4

1

T26

3

T25

1

auto[0]

from_0to1

auto[1]

auto[1]

39

1

T78

1

T248

2

T115

1

auto[1]

from_1to0

auto[0]

auto[0]

32

1

T79

3

T248

1

T115

1

auto[1]

from_1to0

auto[0]

auto[1]

44

1

T4

2

T26

2

T25

1

auto[1]

from_1to0

auto[1]

auto[0]

37

1

T74

1

T78

2

T308

1

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T74

2

T308

1

T57

1

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T4

1

T26

2

T74

1

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T74

1

T308

2

T57

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T4

1

T26

1

T74

2

auto[1]

from_0to1

auto[1]

auto[1]

27

1

T74

3

T79

1

T57

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

642

1

T4

11

T26

13

T25

13

auto[1]

598

1

T4

9

T26

7

T25

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

309

1

T4

7

T26

4

T25

6

from_0to1

308

1

T4

8

T26

4

T25

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

594

1

T4

10

T26

11

T25

9

auto[1]

646

1

T4

10

T26

9

T25

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

600

1

T4

6

T26

6

T25

13

auto[1]

640

1

T4

14

T26

14

T25

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T25

1

T78

1

T79

1

auto[0]

from_1to0

auto[0]

auto[1]

45

1

T4

2

T26

2

T25

1

auto[0]

from_1to0

auto[1]

auto[0]

35

1

T26

2

T25

1

T74

1

auto[0]

from_1to0

auto[1]

auto[1]

47

1

T4

1

T74

1

T308

1

auto[0]

from_0to1

auto[0]

auto[0]

37

1

T4

2

T25

1

T79

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T4

1

T26

1

T25

1

auto[0]

from_0to1

auto[1]

auto[0]

33

1

T4

1

T26

1

T25

1

auto[0]

from_0to1

auto[1]

auto[1]

45

1

T4

1

T25

1

T74

3

auto[1]

from_1to0

auto[0]

auto[0]

34

1

T4

1

T25

1

T57

1

auto[1]

from_1to0

auto[0]

auto[1]

31

1

T4

1

T74

1

T78

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T25

1

T74

1

T308

2

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T4

2

T25

1

T79

1

auto[1]

from_0to1

auto[0]

auto[0]

35

1

T4

1

T26

1

T78

1

auto[1]

from_0to1

auto[0]

auto[1]

37

1

T26

1

T79

1

T308

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T25

1

T308

1

T392

1

auto[1]

from_0to1

auto[1]

auto[1]

37

1

T4

2

T74

1

T78

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

604

1

T4

6

T26

8

T25

12

auto[1]

636

1

T4

14

T26

12

T25

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

274

1

T4

6

T26

5

T25

6

from_0to1

282

1

T4

6

T26

5

T25

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

651

1

T4

9

T26

10

T25

11

auto[1]

589

1

T4

11

T26

10

T25

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

612

1

T4

10

T26

9

T25

8

auto[1]

628

1

T4

10

T26

11

T25

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

35

1

T26

1

T25

2

T219

3

auto[0]

from_1to0

auto[0]

auto[1]

39

1

T26

1

T74

2

T78

1

auto[0]

from_1to0

auto[1]

auto[0]

37

1

T4

2

T26

1

T74

2

auto[0]

from_1to0

auto[1]

auto[1]

29

1

T4

1

T25

1

T78

1

auto[0]

from_0to1

auto[0]

auto[0]

38

1

T26

1

T25

1

T79

2

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T4

2

T78

1

T79

3

auto[0]

from_0to1

auto[1]

auto[0]

28

1

T25

1

T74

1

T308

1

auto[0]

from_0to1

auto[1]

auto[1]

28

1

T78

1

T79

1

T57

1

auto[1]

from_1to0

auto[0]

auto[0]

34

1

T4

1

T26

1

T78

1

auto[1]

from_1to0

auto[0]

auto[1]

30

1

T26

1

T25

1

T57

1

auto[1]

from_1to0

auto[1]

auto[0]

32

1

T4

1

T25

1

T79

1

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T4

1

T25

1

T74

1

auto[1]

from_0to1

auto[0]

auto[0]

30

1

T26

1

T25

1

T219

1

auto[1]

from_0to1

auto[0]

auto[1]

42

1

T4

2

T26

1

T25

2

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T4

1

T74

1

T78

1

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T4

1

T26

2

T74

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

601

1

T4

11

T26

7

T25

10

auto[1]

639

1

T4

9

T26

13

T25

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

302

1

T4

5

T26

7

T25

4

from_0to1

304

1

T4

5

T26

6

T25

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

608

1

T4

9

T26

11

T25

12

auto[1]

632

1

T4

11

T26

9

T25

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

599

1

T4

11

T26

6

T25

10

auto[1]

641

1

T4

9

T26

14

T25

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T74

2

T78

2

T79

1

auto[0]

from_1to0

auto[0]

auto[1]

30

1

T74

1

T248

1

T393

1

auto[0]

from_1to0

auto[1]

auto[0]

29

1

T4

2

T74

1

T78

2

auto[0]

from_1to0

auto[1]

auto[1]

41

1

T26

2

T25

1

T74

1

auto[0]

from_0to1

auto[0]

auto[0]

38

1

T4

1

T26

1

T74

1

auto[0]

from_0to1

auto[0]

auto[1]

42

1

T25

2

T308

1

T57

1

auto[0]

from_0to1

auto[1]

auto[0]

36

1

T4

1

T26

1

T74

1

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T4

1

T25

1

T79

2

auto[1]

from_1to0

auto[0]

auto[0]

43

1

T4

1

T26

1

T25

1

auto[1]

from_1to0

auto[0]

auto[1]

46

1

T4

1

T26

2

T25

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T4

1

T26

1

T25

1

auto[1]

from_1to0

auto[1]

auto[1]

34

1

T26

1

T74

1

T57

1

auto[1]

from_0to1

auto[0]

auto[0]

32

1

T4

1

T25

1

T74

2

auto[1]

from_0to1

auto[0]

auto[1]

45

1

T26

4

T74

1

T78

2

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T4

1

T79

1

T248

1

auto[1]

from_0to1

auto[1]

auto[1]

31

1

T74

1

T78

1

T57

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616

1

T4

12

T26

13

T25

15

auto[1]

624

1

T4

8

T26

7

T25

5

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

298

1

T4

4

T26

3

T25

8

from_0to1

308

1

T4

3

T26

4

T25

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

619

1

T4

13

T26

10

T25

9

auto[1]

621

1

T4

7

T26

10

T25

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

607

1

T4

12

T26

8

T25

8

auto[1]

633

1

T4

8

T26

12

T25

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T4

1

T26

1

T25

1

auto[0]

from_1to0

auto[0]

auto[1]

38

1

T26

1

T25

2

T78

2

auto[0]

from_1to0

auto[1]

auto[0]

36

1

T4

1

T26

1

T74

1

auto[0]

from_1to0

auto[1]

auto[1]

35

1

T4

1

T25

1

T57

1

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T4

2

T25

1

T74

1

auto[0]

from_0to1

auto[0]

auto[1]

35

1

T26

1

T79

1

T57

2

auto[0]

from_0to1

auto[1]

auto[0]

32

1

T26

1

T25

1

T308

1

auto[0]

from_0to1

auto[1]

auto[1]

41

1

T26

1

T25

4

T74

1

auto[1]

from_1to0

auto[0]

auto[0]

35

1

T25

1

T78

1

T79

1

auto[1]

from_1to0

auto[0]

auto[1]

35

1

T25

2

T78

1

T219

2

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T4

1

T25

1

T74

2

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T74

2

T78

1

T79

1

auto[1]

from_0to1

auto[0]

auto[0]

42

1

T25

1

T74

1

T78

3

auto[1]

from_0to1

auto[0]

auto[1]

51

1

T26

1

T74

2

T308

1

auto[1]

from_0to1

auto[1]

auto[0]

35

1

T78

1

T308

1

T219

2

auto[1]

from_0to1

auto[1]

auto[1]

30

1

T4

1

T78

2

T57

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

647

1

T4

11

T26

9

T25

10

auto[1]

593

1

T4

9

T26

11

T25

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

306

1

T4

7

T26

5

T25

5

from_0to1

298

1

T4

6

T26

5

T25

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

606

1

T4

12

T26

7

T25

10

auto[1]

634

1

T4

8

T26

13

T25

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

614

1

T4

5

T26

10

T25

9

auto[1]

626

1

T4

15

T26

10

T25

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

32

1

T4

1

T78

1

T79

2

auto[0]

from_1to0

auto[0]

auto[1]

42

1

T4

2

T25

2

T308

2

auto[0]

from_1to0

auto[1]

auto[0]

33

1

T78

1

T308

1

T219

2

auto[0]

from_1to0

auto[1]

auto[1]

35

1

T4

1

T26

1

T74

1

auto[0]

from_0to1

auto[0]

auto[0]

47

1

T4

2

T26

1

T78

2

auto[0]

from_0to1

auto[0]

auto[1]

35

1

T4

1

T25

2

T74

2

auto[0]

from_0to1

auto[1]

auto[0]

38

1

T4

1

T74

1

T79

1

auto[0]

from_0to1

auto[1]

auto[1]

39

1

T26

1

T79

1

T308

1

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T26

1

T25

1

T78

1

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T4

1

T26

1

T25

1

auto[1]

from_1to0

auto[1]

auto[0]

37

1

T26

1

T25

1

T74

1

auto[1]

from_1to0

auto[1]

auto[1]

41

1

T4

2

T26

1

T308

1

auto[1]

from_0to1

auto[0]

auto[0]

38

1

T26

1

T25

1

T308

1

auto[1]

from_0to1

auto[0]

auto[1]

35

1

T4

2

T26

1

T78

1

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T26

1

T25

1

T57

1

auto[1]

from_0to1

auto[1]

auto[1]

26

1

T25

1

T79

2

T57

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

617

1

T4

8

T26

6

T25

10

auto[1]

623

1

T4

12

T26

14

T25

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

282

1

T4

5

T26

5

T25

3

from_0to1

294

1

T4

4

T26

5

T25

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

627

1

T4

10

T26

13

T25

12

auto[1]

613

1

T4

10

T26

7

T25

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

641

1

T4

12

T26

11

T25

8

auto[1]

599

1

T4

8

T26

9

T25

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T4

1

T26

1

T74

1

auto[0]

from_1to0

auto[0]

auto[1]

31

1

T25

1

T74

1

T219

1

auto[0]

from_1to0

auto[1]

auto[0]

32

1

T4

1

T79

1

T123

2

auto[0]

from_1to0

auto[1]

auto[1]

39

1

T26

1

T78

1

T248

1

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T4

1

T26

1

T74

1

auto[0]

from_0to1

auto[0]

auto[1]

29

1

T26

2

T74

1

T78

1

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T4

1

T74

1

T219

4

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T4

1

T25

2

T248

2

auto[1]

from_1to0

auto[0]

auto[0]

37

1

T4

2

T26

1

T308

2

auto[1]

from_1to0

auto[0]

auto[1]

34

1

T26

1

T78

1

T308

1

auto[1]

from_1to0

auto[1]

auto[0]

33

1

T26

1

T74

1

T78

1

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T4

1

T25

2

T57

1

auto[1]

from_0to1

auto[0]

auto[0]

35

1

T26

1

T78

1

T79

1

auto[1]

from_0to1

auto[0]

auto[1]

32

1

T4

1

T74

1

T308

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T26

1

T25

1

T78

1

auto[1]

from_0to1

auto[1]

auto[1]

32

1

T78

1

T79

1

T308

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

617

1

T4

11

T26

9

T25

11

auto[1]

623

1

T4

9

T26

11

T25

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

300

1

T4

3

T26

7

T25

6

from_0to1

298

1

T4

3

T26

7

T25

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

585

1

T4

12

T26

9

T25

5

auto[1]

655

1

T4

8

T26

11

T25

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

612

1

T4

10

T26

11

T25

13

auto[1]

628

1

T4

10

T26

9

T25

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

36

1

T4

2

T26

2

T25

2

auto[0]

from_1to0

auto[0]

auto[1]

28

1

T74

1

T78

2

T248

1

auto[0]

from_1to0

auto[1]

auto[0]

27

1

T25

3

T74

1

T78

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T25

1

T74

1

T78

3

auto[0]

from_0to1

auto[0]

auto[0]

34

1

T26

2

T74

1

T78

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T4

2

T25

1

T78

2

auto[0]

from_0to1

auto[1]

auto[0]

35

1

T26

1

T25

1

T74

2

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T25

1

T74

1

T79

2

auto[1]

from_1to0

auto[0]

auto[0]

41

1

T78

1

T79

1

T49

1

auto[1]

from_1to0

auto[0]

auto[1]

46

1

T26

1

T308

2

T57

2

auto[1]

from_1to0

auto[1]

auto[0]

43

1

T4

1

T26

3

T74

1

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T26

1

T79

1

T204

1

auto[1]

from_0to1

auto[0]

auto[0]

29

1

T79

1

T219

1

T115

1

auto[1]

from_0to1

auto[0]

auto[1]

31

1

T26

1

T78

2

T49

1

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T4

1

T26

1

T25

2

auto[1]

from_0to1

auto[1]

auto[1]

39

1

T26

2

T78

1

T49

1