Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147688	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

116750

1

T4

40

T5

3

T1

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	140983	1			T4	62		T5	3		T1	25
values[0x0]	61353	1			T4	29		T5	2		T1	7
values[0x1]	62102	1			T4	32		T1	6		T2	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	119140	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145298

1

T4

59

T5

4

T1

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1067	1			T4	8		T2	2		T3	3
valid_sources[0x01]	1004	1			T2	1		T3	5		T16	1
valid_sources[0x02]	822	1			T2	4		T3	3		T6	6
valid_sources[0x03]	944	1			T2	2		T3	2		T6	3
valid_sources[0x04]	784	1			T3	3		T6	3		T16	1
valid_sources[0x05]	890	1			T3	3		T16	2		T73	1
valid_sources[0x06]	947	1			T4	5		T1	38		T3	2
valid_sources[0x07]	999	1			T2	1		T3	4		T6	1
valid_sources[0x08]	906	1			T3	3		T16	2		T161	1
valid_sources[0x09]	947	1			T2	7		T3	5		T6	2
valid_sources[0x0a]	917	1			T3	4		T6	1		T16	3
valid_sources[0x0b]	988	1			T2	3		T3	3		T6	5
valid_sources[0x0c]	1004	1			T4	11		T2	4		T3	3
valid_sources[0x0d]	831	1			T4	6		T2	3		T3	3
valid_sources[0x0e]	828	1			T3	5		T6	5		T9	1
valid_sources[0x0f]	811	1			T2	2		T3	2		T16	2
valid_sources[0x10]	819	1			T2	2		T3	5		T6	1
valid_sources[0x11]	1490	1			T2	4		T3	7		T16	1
valid_sources[0x12]	2174	1			T3	6		T15	10		T16	2
valid_sources[0x13]	782	1			T2	5		T3	4		T6	2
valid_sources[0x14]	1134	1			T3	1		T6	6		T16	1
valid_sources[0x15]	1882	1			T2	1		T3	5		T6	2
valid_sources[0x16]	897	1			T2	2		T3	6		T6	3
valid_sources[0x17]	944	1			T5	1		T2	2		T3	7
valid_sources[0x18]	874	1			T2	6		T3	5		T6	1
valid_sources[0x19]	1252	1			T2	1		T3	4		T6	5
valid_sources[0x1a]	904	1			T2	2		T3	2		T6	4
valid_sources[0x1b]	849	1			T2	1		T3	6		T6	7
valid_sources[0x1c]	900	1			T2	1		T3	3		T16	3
valid_sources[0x1d]	899	1			T2	1		T3	3		T6	6
valid_sources[0x1e]	866	1			T3	5		T6	4		T16	3
valid_sources[0x1f]	889	1			T2	7		T3	4		T16	3
valid_sources[0x20]	1425	1			T2	4		T3	1		T6	1
valid_sources[0x21]	990	1			T2	4		T3	3		T25	5
valid_sources[0x22]	974	1			T4	2		T3	2		T16	2
valid_sources[0x23]	910	1			T2	2		T3	3		T6	1
valid_sources[0x24]	837	1			T2	1		T3	3		T16	1
valid_sources[0x25]	922	1			T2	3		T3	1		T6	2
valid_sources[0x26]	918	1			T2	1		T3	5		T16	1
valid_sources[0x27]	879	1			T3	2		T6	1		T16	4
valid_sources[0x28]	1148	1			T2	4		T3	5		T6	1
valid_sources[0x29]	847	1			T3	3		T6	4		T16	2
valid_sources[0x2a]	990	1			T2	2		T3	5		T16	3
valid_sources[0x2b]	985	1			T4	7		T2	5		T3	4
valid_sources[0x2c]	890	1			T2	2		T3	1		T16	1
valid_sources[0x2d]	898	1			T2	1		T3	3		T73	2
valid_sources[0x2e]	2705	1			T2	2		T3	4		T6	3
valid_sources[0x2f]	1751	1			T2	1		T3	6		T6	5
valid_sources[0x30]	865	1			T2	2		T3	3		T6	2
valid_sources[0x31]	828	1			T4	4		T2	3		T3	4
valid_sources[0x32]	824	1			T2	1		T3	3		T6	2
valid_sources[0x33]	1581	1			T3	1		T6	1		T16	2
valid_sources[0x34]	913	1			T2	1		T3	4		T6	8
valid_sources[0x35]	961	1			T3	3		T16	2		T72	4
valid_sources[0x36]	1194	1			T2	4		T3	7		T6	5
valid_sources[0x37]	875	1			T2	1		T3	8		T6	1
valid_sources[0x38]	855	1			T2	1		T3	1		T6	2
valid_sources[0x39]	941	1			T4	1		T2	4		T3	5
valid_sources[0x3a]	839	1			T4	5		T2	2		T3	7
valid_sources[0x3b]	905	1			T2	3		T3	5		T16	2
valid_sources[0x3c]	1045	1			T2	2		T3	6		T16	1
valid_sources[0x3d]	783	1			T3	3		T16	2		T25	2
valid_sources[0x3e]	828	1			T2	1		T3	1		T6	8
valid_sources[0x3f]	1670	1			T2	1		T3	5		T6	3
valid_sources[0x40]	974	1			T2	3		T6	6		T16	2
valid_sources[0x41]	1333	1			T2	1		T3	6		T6	3
valid_sources[0x42]	763	1			T3	6		T16	1		T25	7
valid_sources[0x43]	860	1			T2	3		T3	3		T72	1
valid_sources[0x44]	958	1			T2	1		T3	3		T6	2
valid_sources[0x45]	1050	1			T2	1		T13	1		T3	9
valid_sources[0x46]	784	1			T3	2		T6	2		T16	1
valid_sources[0x47]	990	1			T2	1		T3	5		T6	5
valid_sources[0x48]	1010	1			T4	3		T2	3		T3	2
valid_sources[0x49]	917	1			T4	1		T2	1		T3	2
valid_sources[0x4a]	1054	1			T3	3		T16	1		T25	13
valid_sources[0x4b]	1885	1			T2	5		T3	5		T6	2
valid_sources[0x4c]	1437	1			T6	1		T16	1		T160	2
valid_sources[0x4d]	924	1			T3	4		T6	4		T16	3
valid_sources[0x4e]	928	1			T2	3		T3	6		T6	1
valid_sources[0x4f]	1511	1			T2	2		T3	2		T6	1
valid_sources[0x50]	866	1			T2	3		T3	6		T6	4
valid_sources[0x51]	925	1			T2	2		T3	4		T17	1
valid_sources[0x52]	878	1			T2	1		T3	3		T6	1
valid_sources[0x53]	932	1			T2	3		T3	4		T16	4
valid_sources[0x54]	958	1			T2	3		T3	1		T6	1
valid_sources[0x55]	1037	1			T2	2		T3	2		T6	3
valid_sources[0x56]	802	1			T2	2		T13	2		T3	3
valid_sources[0x57]	942	1			T2	2		T3	5		T25	4
valid_sources[0x58]	949	1			T3	5		T6	4		T16	2
valid_sources[0x59]	1632	1			T2	3		T3	4		T6	1
valid_sources[0x5a]	907	1			T3	5		T6	5		T16	2
valid_sources[0x5b]	845	1			T4	2		T3	4		T6	1
valid_sources[0x5c]	895	1			T2	5		T3	4		T6	2
valid_sources[0x5d]	874	1			T2	1		T3	2		T6	2
valid_sources[0x5e]	797	1			T2	2		T3	1		T6	4
valid_sources[0x5f]	794	1			T2	1		T3	5		T6	2
valid_sources[0x60]	1038	1			T2	2		T3	8		T6	1
valid_sources[0x61]	921	1			T3	4		T6	1		T16	1
valid_sources[0x62]	857	1			T3	3		T6	2		T26	1
valid_sources[0x63]	1232	1			T2	5		T3	2		T6	2
valid_sources[0x64]	911	1			T2	1		T3	3		T16	1
valid_sources[0x65]	800	1			T2	1		T3	7		T6	1
valid_sources[0x66]	810	1			T3	3		T6	2		T26	2
valid_sources[0x67]	749	1			T2	3		T3	6		T6	1
valid_sources[0x68]	813	1			T4	4		T6	2		T25	1
valid_sources[0x69]	1066	1			T2	1		T3	1		T6	3
valid_sources[0x6a]	861	1			T2	1		T3	6		T6	2
valid_sources[0x6b]	1825	1			T2	1		T3	4		T6	8
valid_sources[0x6c]	995	1			T2	1		T3	5		T6	6
valid_sources[0x6d]	977	1			T2	3		T14	12		T3	1
valid_sources[0x6e]	853	1			T2	1		T3	4		T16	1
valid_sources[0x6f]	789	1			T2	2		T3	3		T6	2
valid_sources[0x70]	885	1			T2	2		T3	2		T6	1
valid_sources[0x71]	1105	1			T3	4		T6	2		T16	2
valid_sources[0x72]	1009	1			T2	3		T3	3		T6	2
valid_sources[0x73]	946	1			T2	6		T3	10		T6	1
valid_sources[0x74]	1196	1			T3	6		T6	6		T16	2
valid_sources[0x75]	821	1			T2	3		T3	2		T16	2
valid_sources[0x76]	838	1			T2	3		T3	3		T16	2
valid_sources[0x77]	986	1			T4	6		T2	1		T3	3
valid_sources[0x78]	843	1			T2	1		T3	4		T6	11
valid_sources[0x79]	941	1			T4	2		T2	3		T3	6
valid_sources[0x7a]	1002	1			T3	4		T6	1		T26	2
valid_sources[0x7b]	1864	1			T2	4		T3	3		T6	4
valid_sources[0x7c]	943	1			T3	3		T16	2		T72	1
valid_sources[0x7d]	1992	1			T3	5		T16	3		T72	2
valid_sources[0x7e]	802	1			T2	3		T3	1		T6	2
valid_sources[0x7f]	916	1			T2	1		T3	6		T16	1
valid_sources[0x80]	908	1			T3	6		T16	1		T72	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64168

1

T4

26

T5

2

T1

10

values[0x0]

all_enables

biggest_size

30604

1

T4

8

T5

1

T1

5

values[0x1]

all_enables

biggest_size

21978

1

T4

6

T2

17

T14

2