| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| sysrst_ctrl_auto_block_debounce_ctl_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 5 | 0 | 5 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_auto_block_enable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
| cp_debounce_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 720 | 1 | T6 | 12 | T72 | 4 | T21 | 4 | ||||
| auto[1] | 818 | 1 | T6 | 8 | T72 | 6 | T21 | 12 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 1106 | 1 | T6 | 20 | T72 | 10 | T21 | 16 | ||||
| mid_range | 224 | 1 | T27 | 6 | T29 | 2 | T48 | 10 | ||||
| min_range | 208 | 1 | T27 | 2 | T28 | 4 | T29 | 4 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |