Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T27,T28,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T27,T28,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T27,T48,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T48
1	0	Covered	T4,T1,T2
1	1	Covered	T27,T28,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T48,T49
0	1	Covered	T54,T105,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T48,T49
0	1	Covered	T27,T48,T49
1	0	Covered	T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T48,T49
1	-	Covered	T27,T48,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T28,T48
DetectSt	168	Covered	T27,T48,T49
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T27,T48,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T48,T49
DebounceSt->IdleSt	163	Covered	T27,T28,T48
DetectSt->IdleSt	186	Covered	T54,T105,T107
DetectSt->StableSt	191	Covered	T27,T48,T49
IdleSt->DebounceSt	148	Covered	T27,T28,T48
StableSt->IdleSt	206	Covered	T27,T48,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T28,T48
0	1	Covered	T27,T28,T48
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T48,T49
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T28,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T28
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T48,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T48,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T28,T48
DetectSt	-	-	-	-	1	-	-	Covered	T54,T105,T107
DetectSt	-	-	-	-	0	1	-	Covered	T27,T48,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T48,T49
StableSt	-	-	-	-	-	-	0	Covered	T27,T48,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	182	0	0
CntIncr_A	5407980	271094	0	0
CntNoWrap_A	5407980	4942403	0	0
DetectStDropOut_A	5407980	3	0	0
DetectedOut_A	5407980	591	0	0
DetectedPulseOut_A	5407980	82	0	0
DisabledIdleSt_A	5407980	4667305	0	0
DisabledNoDetection_A	5407980	4669202	0	0
EnterDebounceSt_A	5407980	97	0	0
EnterDetectSt_A	5407980	85	0	0
EnterStableSt_A	5407980	82	0	0
PulseIsPulse_A	5407980	82	0	0
StayInStableSt	5407980	509	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5407980	5448	0	0
gen_low_level_sva.LowLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	81	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	182	0	0
T22	1614	0	0	0
T27	725	3	0	0
T28	7577	1	0	0
T38	742	0	0	0
T48	0	3	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	5	0	0
T52	0	6	0	0
T53	0	6	0	0
T54	0	6	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T95	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	271094	0	0
T22	1614	0	0	0
T27	725	104	0	0
T28	7577	29	0	0
T38	742	0	0	0
T48	0	183	0	0
T49	0	85	0	0
T50	0	41	0	0
T51	0	128	0	0
T52	0	212	0	0
T53	0	114	0	0
T54	0	235	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T95	0	140	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4942403	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	3	0	0
T35	707	0	0	0
T54	747	1	0	0
T81	81271	0	0	0
T105	0	1	0	0
T107	0	1	0	0
T117	436	0	0	0
T118	493	0	0	0
T119	442	0	0	0
T120	2992	0	0	0
T121	417	0	0	0
T122	798	0	0	0
T123	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	591	0	0
T22	1614	0	0	0
T27	725	8	0	0
T28	7577	0	0	0
T38	742	0	0	0
T48	0	9	0	0
T49	0	7	0	0
T51	0	4	0	0
T52	0	33	0	0
T53	0	16	0	0
T54	0	12	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T95	0	13	0	0
T124	0	10	0	0
T125	0	14	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	82	0	0
T22	1614	0	0	0
T27	725	1	0	0
T28	7577	0	0	0
T38	742	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	0	2	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T95	0	2	0	0
T124	0	1	0	0
T125	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4667305	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4669202	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	97	0	0
T22	1614	0	0	0
T27	725	2	0	0
T28	7577	1	0	0
T38	742	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	3	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	0	3	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T95	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	85	0	0
T22	1614	0	0	0
T27	725	1	0	0
T28	7577	0	0	0
T38	742	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	0	3	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T95	0	2	0	0
T124	0	1	0	0
T125	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	82	0	0
T22	1614	0	0	0
T27	725	1	0	0
T28	7577	0	0	0
T38	742	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	0	2	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T95	0	2	0	0
T124	0	1	0	0
T125	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	82	0	0
T22	1614	0	0	0
T27	725	1	0	0
T28	7577	0	0	0
T38	742	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	0	2	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T95	0	2	0	0
T124	0	1	0	0
T125	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	509	0	0
T22	1614	0	0	0
T27	725	7	0	0
T28	7577	0	0	0
T38	742	0	0	0
T48	0	8	0	0
T49	0	6	0	0
T51	0	2	0	0
T52	0	30	0	0
T53	0	13	0	0
T54	0	10	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T95	0	11	0	0
T124	0	9	0	0
T125	0	12	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	5448	0	0
T1	1691	12	0	0
T2	13374	11	0	0
T3	21335	30	0	0
T4	502	4	0	0
T5	24510	0	0	0
T6	4608	7	0	0
T7	0	30	0	0
T8	0	28	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	20	0	0
T26	0	6	0	0
T45	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	81	0	0
T22	1614	0	0	0
T27	725	1	0	0
T28	7577	0	0	0
T38	742	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	0	2	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T95	0	2	0	0
T124	0	1	0	0
T125	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T22,T65

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T22
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T65
0	1	Covered	T81,T82,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T65
0	1	Unreachable
1	0	Covered	T21,T22,T65

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T21,T22
DetectSt	168	Covered	T21,T22,T65
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T21,T22,T65

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T22,T65
DebounceSt->IdleSt	163	Covered	T1,T28,T64
DetectSt->IdleSt	186	Covered	T81,T82,T94
DetectSt->StableSt	191	Covered	T21,T22,T65
IdleSt->DebounceSt	148	Covered	T1,T21,T22
StableSt->IdleSt	206	Covered	T21,T22,T65

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T21,T22
0	1	Covered	T1,T21,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T65
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T22,T65
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T64,T82
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T81,T82,T94
DetectSt	-	-	-	-	0	1	-	Covered	T21,T22,T65
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T22,T65
StableSt	-	-	-	-	-	-	0	Covered	T21,T22,T65
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	136	0	0
CntIncr_A	5407980	51179	0	0
CntNoWrap_A	5407980	4942449	0	0
DetectStDropOut_A	5407980	13	0	0
DetectedOut_A	5407980	54812	0	0
DetectedPulseOut_A	5407980	36	0	0
DisabledIdleSt_A	5407980	4456370	0	0
DisabledNoDetection_A	5407980	4458293	0	0
EnterDebounceSt_A	5407980	87	0	0
EnterDetectSt_A	5407980	49	0	0
EnterStableSt_A	5407980	36	0	0
PulseIsPulse_A	5407980	36	0	0
StayInStableSt	5407980	54776	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5407980	5448	0	0
gen_low_level_sva.LowLevelEvent_A	5407980	4944508	0	0
gen_sticky_sva.StableStDropOut_A	5407980	300592	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	136	0	0
T1	1691	5	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	2	0	0
T22	0	2	0	0
T28	0	2	0	0
T64	0	4	0	0
T65	0	2	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	7	0	0
T83	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	51179	0	0
T1	1691	330	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	73	0	0
T22	0	21	0	0
T28	0	71	0	0
T64	0	308	0	0
T65	0	69	0	0
T80	0	81	0	0
T81	0	55	0	0
T82	0	336	0	0
T83	0	2511	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4942449	0	0
T1	1691	1285	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	13	0	0
T35	707	0	0	0
T81	81271	1	0	0
T82	1048	3	0	0
T94	0	5	0	0
T119	442	0	0	0
T120	2992	0	0	0
T121	417	0	0	0
T122	798	0	0	0
T123	502	0	0	0
T131	0	1	0	0
T132	0	3	0	0
T133	422	0	0	0
T134	414	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	54812	0	0
T21	7045	189	0	0
T22	0	4	0	0
T27	725	0	0	0
T32	12260	0	0	0
T65	0	405	0	0
T69	490	0	0	0
T70	493	0	0	0
T80	0	26	0	0
T89	0	127	0	0
T94	0	12653	0	0
T127	0	58	0	0
T128	0	306	0	0
T129	0	163	0	0
T130	0	385	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	36	0	0
T21	7045	1	0	0
T22	0	1	0	0
T27	725	0	0	0
T32	12260	0	0	0
T65	0	1	0	0
T69	490	0	0	0
T70	493	0	0	0
T80	0	1	0	0
T89	0	1	0	0
T94	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	3	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4456370	0	0
T1	1691	751	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4458293	0	0
T1	1691	752	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	87	0	0
T1	1691	5	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T28	0	2	0	0
T64	0	4	0	0
T65	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	4	0	0
T83	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	49	0	0
T21	7045	1	0	0
T22	0	1	0	0
T27	725	0	0	0
T32	12260	0	0	0
T65	0	1	0	0
T69	490	0	0	0
T70	493	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	3	0	0
T89	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	36	0	0
T21	7045	1	0	0
T22	0	1	0	0
T27	725	0	0	0
T32	12260	0	0	0
T65	0	1	0	0
T69	490	0	0	0
T70	493	0	0	0
T80	0	1	0	0
T89	0	1	0	0
T94	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	3	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	36	0	0
T21	7045	1	0	0
T22	0	1	0	0
T27	725	0	0	0
T32	12260	0	0	0
T65	0	1	0	0
T69	490	0	0	0
T70	493	0	0	0
T80	0	1	0	0
T89	0	1	0	0
T94	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	3	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	54776	0	0
T21	7045	188	0	0
T22	0	3	0	0
T27	725	0	0	0
T32	12260	0	0	0
T65	0	404	0	0
T69	490	0	0	0
T70	493	0	0	0
T80	0	25	0	0
T89	0	126	0	0
T94	0	12652	0	0
T127	0	57	0	0
T128	0	305	0	0
T129	0	162	0	0
T130	0	382	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	5448	0	0
T1	1691	12	0	0
T2	13374	11	0	0
T3	21335	30	0	0
T4	502	4	0	0
T5	24510	0	0	0
T6	4608	7	0	0
T7	0	30	0	0
T8	0	28	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	20	0	0
T26	0	6	0	0
T45	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	300592	0	0
T21	7045	155	0	0
T22	0	101	0	0
T27	725	0	0	0
T32	12260	0	0	0
T65	0	247	0	0
T69	490	0	0	0
T70	493	0	0	0
T80	0	52	0	0
T89	0	315	0	0
T94	0	87	0	0
T127	0	112	0	0
T128	0	32977	0	0
T129	0	212	0	0
T130	0	660	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T6
1	1	Covered	T4,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T22,T64

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T22
1	0	Covered	T4,T1,T6
1	1	Covered	T1,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T64
0	1	Covered	T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T64
0	1	Unreachable
1	0	Covered	T1,T22,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T21,T22
DetectSt	168	Covered	T1,T22,T64
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T22,T64

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T22,T64
DebounceSt->IdleSt	163	Covered	T21,T28,T64
DetectSt->IdleSt	186	Covered	T92,T93
DetectSt->StableSt	191	Covered	T1,T22,T64
IdleSt->DebounceSt	148	Covered	T1,T21,T22
StableSt->IdleSt	206	Covered	T1,T22,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T21,T22
0	1	Covered	T1,T21,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T64
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T22,T64
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T64,T65
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T92,T93
DetectSt	-	-	-	-	0	1	-	Covered	T1,T22,T64
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T22,T64
StableSt	-	-	-	-	-	-	0	Covered	T1,T22,T64
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	117	0	0
CntIncr_A	5407980	60277	0	0
CntNoWrap_A	5407980	4942468	0	0
DetectStDropOut_A	5407980	4	0	0
DetectedOut_A	5407980	138023	0	0
DetectedPulseOut_A	5407980	44	0	0
DisabledIdleSt_A	5407980	4456370	0	0
DisabledNoDetection_A	5407980	4458293	0	0
EnterDebounceSt_A	5407980	69	0	0
EnterDetectSt_A	5407980	48	0	0
EnterStableSt_A	5407980	44	0	0
PulseIsPulse_A	5407980	44	0	0
StayInStableSt	5407980	137979	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_sticky_sva.StableStDropOut_A	5407980	285122	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	117	0	0
T1	1691	2	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	2	0	0
T22	0	2	0	0
T28	0	2	0	0
T64	0	5	0	0
T65	0	4	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	60277	0	0
T1	1691	45	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	188	0	0
T22	0	68	0	0
T28	0	69	0	0
T64	0	219	0	0
T65	0	180	0	0
T80	0	55	0	0
T81	0	60	0	0
T82	0	38	0	0
T83	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4942468	0	0
T1	1691	1288	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4	0	0
T92	590	1	0	0
T93	0	3	0	0
T140	504	0	0	0
T141	502	0	0	0
T142	54954	0	0	0
T143	2828	0	0	0
T144	416	0	0	0
T145	422	0	0	0
T146	846	0	0	0
T147	2065	0	0	0
T148	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	138023	0	0
T1	1691	264	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T22	0	32	0	0
T64	0	76	0	0
T80	0	2	0	0
T81	0	38	0	0
T82	0	228	0	0
T83	0	201	0	0
T89	0	311	0	0
T127	0	83	0	0
T128	0	28078	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	44	0	0
T1	1691	1	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T22	0	1	0	0
T64	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T89	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4456370	0	0
T1	1691	751	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4458293	0	0
T1	1691	752	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	69	0	0
T1	1691	1	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T28	0	2	0	0
T64	0	3	0	0
T65	0	4	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	48	0	0
T1	1691	1	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T22	0	1	0	0
T64	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T89	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	44	0	0
T1	1691	1	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T22	0	1	0	0
T64	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T89	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	44	0	0
T1	1691	1	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T22	0	1	0	0
T64	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T89	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	137979	0	0
T1	1691	263	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T22	0	31	0	0
T64	0	74	0	0
T80	0	1	0	0
T81	0	37	0	0
T82	0	227	0	0
T83	0	200	0	0
T89	0	310	0	0
T127	0	82	0	0
T128	0	28077	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	285122	0	0
T1	1691	216	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T22	0	26	0	0
T64	0	252	0	0
T80	0	105	0	0
T81	0	75381	0	0
T82	0	316	0	0
T83	0	2338	0	0
T89	0	120	0	0
T127	0	77	0	0
T128	0	130	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T22,T64

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T22
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T64,T65
0	1	Covered	T1,T89,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T64,T65
0	1	Unreachable
1	0	Covered	T22,T64,T65

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T21,T22
DetectSt	168	Covered	T1,T22,T64
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T22,T64,T65

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T22,T64
DebounceSt->IdleSt	163	Covered	T1,T21,T28
DetectSt->IdleSt	186	Covered	T1,T89,T90
DetectSt->StableSt	191	Covered	T22,T64,T65
IdleSt->DebounceSt	148	Covered	T1,T21,T22
StableSt->IdleSt	206	Covered	T22,T64,T65

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T21,T22
0	1	Covered	T1,T21,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T64
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T22,T64
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T21,T128
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T1,T89,T90
DetectSt	-	-	-	-	0	1	-	Covered	T22,T64,T65
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T64,T65
StableSt	-	-	-	-	-	-	0	Covered	T22,T64,T65
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	130	0	0
CntIncr_A	5407980	172306	0	0
CntNoWrap_A	5407980	4942455	0	0
DetectStDropOut_A	5407980	8	0	0
DetectedOut_A	5407980	43471	0	0
DetectedPulseOut_A	5407980	41	0	0
DisabledIdleSt_A	5407980	4456370	0	0
DisabledNoDetection_A	5407980	4458293	0	0
EnterDebounceSt_A	5407980	81	0	0
EnterDetectSt_A	5407980	49	0	0
EnterStableSt_A	5407980	41	0	0
PulseIsPulse_A	5407980	41	0	0
StayInStableSt	5407980	43430	0	0
gen_high_event_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_sticky_sva.StableStDropOut_A	5407980	100031	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	130	0	0
T1	1691	6	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	2	0	0
T22	0	2	0	0
T28	0	2	0	0
T64	0	4	0	0
T65	0	2	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	172306	0	0
T1	1691	450	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	32	0	0
T22	0	95	0	0
T28	0	71	0	0
T64	0	26	0	0
T65	0	83	0	0
T80	0	96	0	0
T81	0	39802	0	0
T82	0	98	0	0
T83	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4942455	0	0
T1	1691	1284	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	8	0	0
T1	1691	1	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T89	0	3	0	0
T90	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	43471	0	0
T22	1614	24	0	0
T28	7577	0	0	0
T38	742	0	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T64	1711	60	0	0
T65	0	492	0	0
T80	0	41	0	0
T81	0	35659	0	0
T82	0	438	0	0
T83	0	258	0	0
T89	0	56	0	0
T127	0	36	0	0
T129	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	41	0	0
T22	1614	1	0	0
T28	7577	0	0	0
T38	742	0	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T64	1711	2	0	0
T65	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T89	0	1	0	0
T127	0	1	0	0
T129	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4456370	0	0
T1	1691	751	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4458293	0	0
T1	1691	752	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	81	0	0
T1	1691	5	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T28	0	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	49	0	0
T1	1691	1	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T22	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T89	0	4	0	0
T127	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	41	0	0
T22	1614	1	0	0
T28	7577	0	0	0
T38	742	0	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T64	1711	2	0	0
T65	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T89	0	1	0	0
T127	0	1	0	0
T129	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	41	0	0
T22	1614	1	0	0
T28	7577	0	0	0
T38	742	0	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T64	1711	2	0	0
T65	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T89	0	1	0	0
T127	0	1	0	0
T129	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	43430	0	0
T22	1614	23	0	0
T28	7577	0	0	0
T38	742	0	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T64	1711	58	0	0
T65	0	491	0	0
T80	0	40	0	0
T81	0	35658	0	0
T82	0	437	0	0
T83	0	257	0	0
T89	0	55	0	0
T127	0	35	0	0
T129	0	38	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	100031	0	0
T22	1614	25	0	0
T28	7577	0	0	0
T38	742	0	0	0
T56	491	0	0	0
T57	504	0	0	0
T58	422	0	0	0
T59	25455	0	0	0
T60	26983	0	0	0
T61	494	0	0	0
T64	1711	549	0	0
T65	0	158	0	0
T80	0	26	0	0
T81	0	24	0	0
T82	0	58	0	0
T83	0	2259	0	0
T89	0	102	0	0
T127	0	152	0	0
T129	0	385	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T12,T22,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T12,T22,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T12,T22,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T22
1	0	Covered	T4,T5,T1
1	1	Covered	T12,T22,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T39
0	1	Covered	T12,T22,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T22,T39
1	-	Covered	T12,T22,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T22,T28
DetectSt	168	Covered	T12,T22,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T12,T22,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T22,T39
DebounceSt->IdleSt	163	Covered	T28,T86
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T22,T39
IdleSt->DebounceSt	148	Covered	T12,T22,T28
StableSt->IdleSt	206	Covered	T12,T22,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T22,T28
0	1	Covered	T12,T22,T28
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T22,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T22,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T22,T39
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T22,T28
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T22,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T22,T39
StableSt	-	-	-	-	-	-	0	Covered	T12,T22,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	69	0	0
CntIncr_A	5407980	1999	0	0
CntNoWrap_A	5407980	4942516	0	0
DetectStDropOut_A	5407980	0	0	0
DetectedOut_A	5407980	2205	0	0
DetectedPulseOut_A	5407980	34	0	0
DisabledIdleSt_A	5407980	4929762	0	0
DisabledNoDetection_A	5407980	4931646	0	0
EnterDebounceSt_A	5407980	36	0	0
EnterDetectSt_A	5407980	34	0	0
EnterStableSt_A	5407980	33	0	0
PulseIsPulse_A	5407980	33	0	0
StayInStableSt	5407980	2157	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	69	0	0
T12	1104	4	0	0
T21	7045	0	0	0
T22	0	2	0	0
T28	0	1	0	0
T32	12260	0	0	0
T37	0	4	0	0
T39	0	4	0	0
T43	0	2	0	0
T63	21009	0	0	0
T69	490	0	0	0
T91	0	4	0	0
T120	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	4	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1999	0	0
T12	1104	184	0	0
T21	7045	0	0	0
T22	0	15	0	0
T28	0	37	0	0
T32	12260	0	0	0
T37	0	178	0	0
T39	0	64	0	0
T43	0	34	0	0
T63	21009	0	0	0
T69	490	0	0	0
T91	0	178	0	0
T120	0	15	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	60	0	0
T152	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4942516	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	2205	0	0
T12	1104	83	0	0
T21	7045	0	0	0
T22	0	48	0	0
T32	12260	0	0	0
T37	0	80	0	0
T39	0	83	0	0
T43	0	159	0	0
T63	21009	0	0	0
T69	490	0	0	0
T91	0	80	0	0
T120	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	140	0	0
T152	0	57	0	0
T153	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	34	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T91	0	2	0	0
T120	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4929762	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4931646	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	36	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T32	12260	0	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T91	0	2	0	0
T120	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	2	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	34	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T91	0	2	0	0
T120	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	33	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T91	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	33	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T91	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	2157	0	0
T12	1104	80	0	0
T21	7045	0	0	0
T22	0	47	0	0
T32	12260	0	0	0
T37	0	78	0	0
T39	0	80	0	0
T43	0	157	0	0
T63	21009	0	0	0
T69	490	0	0	0
T91	0	77	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	138	0	0
T152	0	56	0	0
T153	0	39	0	0
T154	0	223	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	19	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T91	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	2	0	0
T152	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T4,T2,T3
1	1	Covered	T6,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T12
0	1	Covered	T157,T158,T159
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T12
0	1	Covered	T12,T44,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T12
1	-	Covered	T12,T44,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T11
DetectSt	168	Covered	T9,T11,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T12
DebounceSt->IdleSt	163	Covered	T6,T28,T39
DetectSt->IdleSt	186	Covered	T157,T158,T159
DetectSt->StableSt	191	Covered	T9,T11,T12
IdleSt->DebounceSt	148	Covered	T6,T9,T11
StableSt->IdleSt	206	Covered	T12,T44,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T12
0	1	Covered	T6,T9,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T151,T91
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T157,T158,T159
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T44,T39
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	111	0	0
CntIncr_A	5407980	58197	0	0
CntNoWrap_A	5407980	4942474	0	0
DetectStDropOut_A	5407980	3	0	0
DetectedOut_A	5407980	14032	0	0
DetectedPulseOut_A	5407980	49	0	0
DisabledIdleSt_A	5407980	4801514	0	0
DisabledNoDetection_A	5407980	4803392	0	0
EnterDebounceSt_A	5407980	60	0	0
EnterDetectSt_A	5407980	52	0	0
EnterStableSt_A	5407980	49	0	0
PulseIsPulse_A	5407980	49	0	0
StayInStableSt	5407980	13962	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5407980	1567	0	0
gen_low_level_sva.LowLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	111	0	0
T9	2217	2	0	0
T10	41181	0	0	0
T11	518	2	0	0
T12	0	4	0	0
T23	491	0	0	0
T24	490	0	0	0
T28	0	1	0	0
T39	0	3	0	0
T42	0	4	0	0
T44	0	2	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	2	0	0
T120	0	2	0	0
T151	0	5	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	58197	0	0
T6	4608	78	0	0
T7	19290	0	0	0
T8	14289	0	0	0
T9	0	90	0	0
T11	0	26	0	0
T12	0	184	0	0
T16	5220	0	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	36	0	0
T39	0	64	0	0
T42	0	100	0	0
T44	0	68	0	0
T45	8443	0	0	0
T55	402	0	0	0
T72	1267	0	0	0
T81	0	88	0	0
T151	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4942474	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	3	0	0
T90	2774	0	0	0
T157	2482	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T163	492	0	0	0
T164	1810	0	0	0
T165	502	0	0	0
T166	522	0	0	0
T167	492	0	0	0
T168	779	0	0	0
T169	4425	0	0	0
T170	753	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	14032	0	0
T9	2217	42	0	0
T10	41181	0	0	0
T11	518	82	0	0
T12	0	240	0	0
T23	491	0	0	0
T24	490	0	0	0
T35	0	81	0	0
T39	0	76	0	0
T42	0	186	0	0
T44	0	26	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	427	0	0
T120	0	59	0	0
T151	0	73	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	49	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	1	0	0
T12	0	2	0	0
T23	491	0	0	0
T24	490	0	0	0
T35	0	2	0	0
T39	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T151	0	2	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4801514	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	240	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4803392	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	254	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	60	0	0
T6	4608	1	0	0
T7	19290	0	0	0
T8	14289	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T16	5220	0	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	1	0	0
T39	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T45	8443	0	0	0
T55	402	0	0	0
T72	1267	0	0	0
T81	0	1	0	0
T151	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	52	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	1	0	0
T12	0	2	0	0
T23	491	0	0	0
T24	490	0	0	0
T35	0	2	0	0
T39	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T151	0	2	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	49	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	1	0	0
T12	0	2	0	0
T23	491	0	0	0
T24	490	0	0	0
T35	0	2	0	0
T39	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T151	0	2	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	49	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	1	0	0
T12	0	2	0	0
T23	491	0	0	0
T24	490	0	0	0
T35	0	2	0	0
T39	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T151	0	2	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	13962	0	0
T9	2217	40	0	0
T10	41181	0	0	0
T11	518	80	0	0
T12	0	238	0	0
T23	491	0	0	0
T24	490	0	0	0
T35	0	78	0	0
T39	0	75	0	0
T42	0	184	0	0
T44	0	25	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	425	0	0
T120	0	58	0	0
T151	0	70	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1567	0	0
T1	1691	0	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T4	502	7	0	0
T5	24510	0	0	0
T6	4608	7	0	0
T9	0	4	0	0
T11	0	1	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T23	0	6	0	0
T24	0	5	0	0
T25	0	7	0	0
T26	0	6	0	0
T73	0	3	0	0
T74	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	28	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T32	12260	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T91	0	1	0	0
T120	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	1	0	0
T152	0	1	0	0