Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T12,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T9,T12,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T12,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T4,T5,T1
1	1	Covered	T9,T12,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T22
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T22
0	1	Covered	T9,T12,T151
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T22
1	-	Covered	T9,T12,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T12,T22
DetectSt	168	Covered	T9,T12,T22
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T12,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T12,T22
DebounceSt->IdleSt	163	Covered	T28,T86,T171
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T12,T22
IdleSt->DebounceSt	148	Covered	T9,T12,T22
StableSt->IdleSt	206	Covered	T9,T12,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T12,T22
0	1	Covered	T9,T12,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T22
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T12,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T12,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T171
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T12,T22
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T12,T151
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	51	0	0
CntIncr_A	5407980	2210	0	0
CntNoWrap_A	5407980	4942534	0	0
DetectStDropOut_A	5407980	0	0	0
DetectedOut_A	5407980	5779	0	0
DetectedPulseOut_A	5407980	24	0	0
DisabledIdleSt_A	5407980	4925333	0	0
DisabledNoDetection_A	5407980	4927220	0	0
EnterDebounceSt_A	5407980	27	0	0
EnterDetectSt_A	5407980	24	0	0
EnterStableSt_A	5407980	24	0	0
PulseIsPulse_A	5407980	24	0	0
StayInStableSt	5407980	5741	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	51	0	0
T9	2217	2	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	2	0	0
T22	0	2	0	0
T23	491	0	0	0
T24	490	0	0	0
T28	0	1	0	0
T40	0	2	0	0
T42	0	4	0	0
T43	0	4	0	0
T47	12528	0	0	0
T68	499	0	0	0
T91	0	2	0	0
T151	0	2	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0
T172	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	2210	0	0
T9	2217	90	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	92	0	0
T22	0	15	0	0
T23	491	0	0	0
T24	490	0	0	0
T28	0	38	0	0
T40	0	46	0	0
T42	0	100	0	0
T43	0	68	0	0
T47	12528	0	0	0
T68	499	0	0	0
T91	0	89	0	0
T151	0	30	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0
T172	0	182	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4942534	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	5779	0	0
T9	2217	213	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	250	0	0
T22	0	65	0	0
T23	491	0	0	0
T24	490	0	0	0
T40	0	48	0	0
T42	0	140	0	0
T43	0	82	0	0
T47	12528	0	0	0
T68	499	0	0	0
T91	0	259	0	0
T151	0	23	0	0
T152	0	40	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0
T172	0	307	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	24	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	1	0	0
T22	0	1	0	0
T23	491	0	0	0
T24	490	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T47	12528	0	0	0
T68	499	0	0	0
T91	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0
T172	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4925333	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	240	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4927220	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	254	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	27	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	1	0	0
T22	0	1	0	0
T23	491	0	0	0
T24	490	0	0	0
T28	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T47	12528	0	0	0
T68	499	0	0	0
T91	0	1	0	0
T151	0	1	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0
T172	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	24	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	1	0	0
T22	0	1	0	0
T23	491	0	0	0
T24	490	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T47	12528	0	0	0
T68	499	0	0	0
T91	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0
T172	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	24	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	1	0	0
T22	0	1	0	0
T23	491	0	0	0
T24	490	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T47	12528	0	0	0
T68	499	0	0	0
T91	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0
T172	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	24	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	1	0	0
T22	0	1	0	0
T23	491	0	0	0
T24	490	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T47	12528	0	0	0
T68	499	0	0	0
T91	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0
T172	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	5741	0	0
T9	2217	212	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	249	0	0
T22	0	63	0	0
T23	491	0	0	0
T24	490	0	0	0
T40	0	46	0	0
T42	0	137	0	0
T43	0	79	0	0
T47	12528	0	0	0
T68	499	0	0	0
T91	0	257	0	0
T151	0	22	0	0
T152	0	39	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0
T172	0	304	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	10	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	1	0	0
T23	491	0	0	0
T24	490	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	12528	0	0	0
T68	499	0	0	0
T143	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T12,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T9,T12,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T12,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T12,T22
1	0	Covered	T4,T5,T2
1	1	Covered	T9,T12,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T22
0	1	Covered	T175
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T22
0	1	Covered	T12,T22,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T22
1	-	Covered	T12,T22,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T12,T22
DetectSt	168	Covered	T9,T12,T22
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T12,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T12,T22
DebounceSt->IdleSt	163	Covered	T9,T38,T28
DetectSt->IdleSt	186	Covered	T175
DetectSt->StableSt	191	Covered	T9,T12,T22
IdleSt->DebounceSt	148	Covered	T9,T12,T22
StableSt->IdleSt	206	Covered	T12,T22,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T12,T22
0	1	Covered	T9,T12,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T22
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T12,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T12,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T38,T43
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T12,T22
DetectSt	-	-	-	-	1	-	-	Covered	T175
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T22,T38
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	98	0	0
CntIncr_A	5407980	2916	0	0
CntNoWrap_A	5407980	4942487	0	0
DetectStDropOut_A	5407980	1	0	0
DetectedOut_A	5407980	3624	0	0
DetectedPulseOut_A	5407980	44	0	0
DisabledIdleSt_A	5407980	4929498	0	0
DisabledNoDetection_A	5407980	4931384	0	0
EnterDebounceSt_A	5407980	53	0	0
EnterDetectSt_A	5407980	45	0	0
EnterStableSt_A	5407980	44	0	0
PulseIsPulse_A	5407980	44	0	0
StayInStableSt	5407980	3563	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5407980	1835	0	0
gen_low_level_sva.LowLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	98	0	0
T9	2217	3	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	4	0	0
T22	0	2	0	0
T23	491	0	0	0
T24	490	0	0	0
T28	0	1	0	0
T38	0	3	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	4	0	0
T43	0	3	0	0
T47	12528	0	0	0
T68	499	0	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	2916	0	0
T9	2217	180	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	184	0	0
T22	0	15	0	0
T23	491	0	0	0
T24	490	0	0	0
T28	0	37	0	0
T38	0	124	0	0
T39	0	64	0	0
T40	0	46	0	0
T41	0	26	0	0
T42	0	100	0	0
T43	0	68	0	0
T47	12528	0	0	0
T68	499	0	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4942487	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1	0	0
T108	21982	0	0	0
T175	518	1	0	0
T176	19053	0	0	0
T177	522	0	0	0
T178	423	0	0	0
T179	19478	0	0	0
T180	493	0	0	0
T181	738	0	0	0
T182	2244	0	0	0
T183	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	3624	0	0
T9	2217	43	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	166	0	0
T22	0	136	0	0
T23	491	0	0	0
T24	490	0	0	0
T38	0	50	0	0
T39	0	80	0	0
T40	0	38	0	0
T41	0	91	0	0
T42	0	86	0	0
T43	0	83	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	171	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	44	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	2	0	0
T22	0	1	0	0
T23	491	0	0	0
T24	490	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	1	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4929498	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4931384	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	53	0	0
T9	2217	2	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	2	0	0
T22	0	1	0	0
T23	491	0	0	0
T24	490	0	0	0
T28	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T47	12528	0	0	0
T68	499	0	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	45	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	2	0	0
T22	0	1	0	0
T23	491	0	0	0
T24	490	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	1	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	44	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	2	0	0
T22	0	1	0	0
T23	491	0	0	0
T24	490	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	1	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	44	0	0
T9	2217	1	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	2	0	0
T22	0	1	0	0
T23	491	0	0	0
T24	490	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	1	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	3563	0	0
T9	2217	41	0	0
T10	41181	0	0	0
T11	518	0	0	0
T12	0	163	0	0
T22	0	135	0	0
T23	491	0	0	0
T24	490	0	0	0
T38	0	49	0	0
T39	0	78	0	0
T40	0	37	0	0
T41	0	89	0	0
T42	0	84	0	0
T43	0	82	0	0
T47	12528	0	0	0
T68	499	0	0	0
T81	0	169	0	0
T160	409	0	0	0
T161	406	0	0	0
T162	402	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1835	0	0
T1	1691	0	0	0
T2	13374	0	0	0
T3	21335	0	0	0
T4	502	6	0	0
T5	24510	2	0	0
T6	4608	9	0	0
T9	0	8	0	0
T13	814	7	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T23	0	5	0	0
T25	0	7	0	0
T26	0	6	0	0
T73	0	5	0	0
T74	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	27	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T122	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T12,T22,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T12,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T12,T22,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T4,T1,T2
1	1	Covered	T6,T12,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T38
0	1	Covered	T12,T22,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T22,T38
1	-	Covered	T12,T22,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T12,T22
DetectSt	168	Covered	T12,T22,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T12,T22,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T22,T38
DebounceSt->IdleSt	163	Covered	T6,T28,T184
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T22,T38
IdleSt->DebounceSt	148	Covered	T6,T12,T22
StableSt->IdleSt	206	Covered	T12,T22,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T22,T38
0	1	Covered	T6,T12,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T22,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T12,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T22,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T184,T185
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T12,T22
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T22,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T22,T39
StableSt	-	-	-	-	-	-	0	Covered	T12,T22,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	90	0	0
CntIncr_A	5407980	4020	0	0
CntNoWrap_A	5407980	4942495	0	0
DetectStDropOut_A	5407980	0	0	0
DetectedOut_A	5407980	4627	0	0
DetectedPulseOut_A	5407980	43	0	0
DisabledIdleSt_A	5407980	4924488	0	0
DisabledNoDetection_A	5407980	4926372	0	0
EnterDebounceSt_A	5407980	48	0	0
EnterDetectSt_A	5407980	43	0	0
EnterStableSt_A	5407980	43	0	0
PulseIsPulse_A	5407980	43	0	0
StayInStableSt	5407980	4566	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	90	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T22	0	2	0	0
T28	0	1	0	0
T32	12260	0	0	0
T35	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T42	0	2	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	2	0	0
T122	0	4	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T186	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4020	0	0
T6	4608	79	0	0
T7	19290	0	0	0
T8	14289	0	0	0
T12	0	92	0	0
T16	5220	0	0	0
T17	434	0	0	0
T22	0	15	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	37	0	0
T35	0	52	0	0
T38	0	62	0	0
T39	0	32	0	0
T42	0	50	0	0
T45	8443	0	0	0
T55	402	0	0	0
T72	1267	0	0	0
T81	0	32	0	0
T122	0	102	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4942495	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4627	0	0
T12	1104	470	0	0
T21	7045	0	0	0
T22	0	9	0	0
T32	12260	0	0	0
T35	0	153	0	0
T38	0	270	0	0
T39	0	134	0	0
T42	0	94	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	10	0	0
T122	0	86	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	7	0	0
T186	0	33	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	43	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T122	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	1	0	0
T186	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4924488	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	240	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4926372	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	254	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	48	0	0
T6	4608	1	0	0
T7	19290	0	0	0
T8	14289	0	0	0
T12	0	1	0	0
T16	5220	0	0	0
T17	434	0	0	0
T22	0	1	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T45	8443	0	0	0
T55	402	0	0	0
T72	1267	0	0	0
T81	0	1	0	0
T122	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	43	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T122	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	1	0	0
T186	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	43	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T122	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	1	0	0
T186	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	43	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T122	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	1	0	0
T186	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4566	0	0
T12	1104	469	0	0
T21	7045	0	0	0
T22	0	8	0	0
T32	12260	0	0	0
T35	0	152	0	0
T38	0	268	0	0
T39	0	133	0	0
T42	0	93	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	9	0	0
T122	0	83	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	6	0	0
T186	0	32	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	25	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T122	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	1	0	0
T184	0	1	0	0
T186	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T12,T22,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T12,T22,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T12,T22,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T38
1	0	Covered	T4,T1,T2
1	1	Covered	T12,T22,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T43
0	1	Covered	T174
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T43
0	1	Covered	T122,T185,T187
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T22,T43
1	-	Covered	T122,T185,T187

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T22,T28
DetectSt	168	Covered	T12,T22,T43
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T12,T22,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T22,T43
DebounceSt->IdleSt	163	Covered	T28,T81,T172
DetectSt->IdleSt	186	Covered	T174
DetectSt->StableSt	191	Covered	T12,T22,T43
IdleSt->DebounceSt	148	Covered	T12,T22,T28
StableSt->IdleSt	206	Covered	T22,T81,T120

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T22,T28
0	1	Covered	T12,T22,T28
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T22,T43
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T22,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T22,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T81,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T22,T28
DetectSt	-	-	-	-	1	-	-	Covered	T174
DetectSt	-	-	-	-	0	1	-	Covered	T12,T22,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T122,T185,T187
StableSt	-	-	-	-	-	-	0	Covered	T12,T22,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	44	0	0
CntIncr_A	5407980	1236	0	0
CntNoWrap_A	5407980	4942541	0	0
DetectStDropOut_A	5407980	1	0	0
DetectedOut_A	5407980	1230	0	0
DetectedPulseOut_A	5407980	19	0	0
DisabledIdleSt_A	5407980	4932202	0	0
DisabledNoDetection_A	5407980	4934092	0	0
EnterDebounceSt_A	5407980	24	0	0
EnterDetectSt_A	5407980	20	0	0
EnterStableSt_A	5407980	19	0	0
PulseIsPulse_A	5407980	19	0	0
StayInStableSt	5407980	1198	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5407980	5211	0	0
gen_low_level_sva.LowLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	6	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	44	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T22	0	2	0	0
T28	0	1	0	0
T32	12260	0	0	0
T43	0	2	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	3	0	0
T120	0	2	0	0
T122	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	2	0	0
T172	0	1	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1236	0	0
T12	1104	92	0	0
T21	7045	0	0	0
T22	0	15	0	0
T28	0	37	0	0
T32	12260	0	0	0
T43	0	34	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	120	0	0
T120	0	15	0	0
T122	0	51	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	72	0	0
T172	0	91	0	0
T188	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4942541	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1	0	0
T174	30553	1	0	0
T189	494	0	0	0
T190	422	0	0	0
T191	422	0	0	0
T192	562	0	0	0
T193	497	0	0	0
T194	8923	0	0	0
T195	423	0	0	0
T196	537	0	0	0
T197	757	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1230	0	0
T12	1104	39	0	0
T21	7045	0	0	0
T22	0	39	0	0
T32	12260	0	0	0
T43	0	41	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	52	0	0
T120	0	16	0	0
T122	0	50	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	169	0	0
T157	0	46	0	0
T185	0	95	0	0
T188	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	19	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T122	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T185	0	2	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4932202	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4934092	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	24	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T32	12260	0	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	2	0	0
T120	0	1	0	0
T122	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	1	0	0
T172	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	20	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T122	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T185	0	2	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	19	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T122	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T185	0	2	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	19	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T122	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T185	0	2	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1198	0	0
T12	1104	37	0	0
T21	7045	0	0	0
T22	0	37	0	0
T32	12260	0	0	0
T43	0	39	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	50	0	0
T120	0	14	0	0
T122	0	49	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	167	0	0
T157	0	44	0	0
T185	0	92	0	0
T188	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	5211	0	0
T1	1691	12	0	0
T2	13374	16	0	0
T3	21335	20	0	0
T4	502	4	0	0
T5	24510	0	0	0
T6	4608	11	0	0
T7	0	37	0	0
T8	0	27	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	16	0	0
T26	0	4	0	0
T45	0	39	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	6	0	0
T35	707	0	0	0
T82	1048	0	0	0
T95	677	0	0	0
T122	798	1	0	0
T123	502	0	0	0
T133	422	0	0	0
T134	414	0	0	0
T185	0	1	0	0
T187	0	1	0	0
T198	0	2	0	0
T199	0	1	0	0
T200	413	0	0	0
T201	422	0	0	0
T202	667	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T2,T3
1	1	Covered	T4,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T12,T22,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T12,T22,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T12,T22,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T38
1	0	Covered	T4,T2,T3
1	1	Covered	T12,T22,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T38
0	1	Covered	T43,T175,T203
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T38
0	1	Covered	T12,T22,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T22,T38
1	-	Covered	T12,T22,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T22,T38
DetectSt	168	Covered	T12,T22,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T12,T22,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T22,T38
DebounceSt->IdleSt	163	Covered	T22,T28,T152
DetectSt->IdleSt	186	Covered	T43,T175,T203
DetectSt->StableSt	191	Covered	T12,T22,T38
IdleSt->DebounceSt	148	Covered	T12,T22,T38
StableSt->IdleSt	206	Covered	T12,T22,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T22,T38
0	1	Covered	T12,T22,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T22,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T22,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T22,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T152,T173
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T22,T38
DetectSt	-	-	-	-	1	-	-	Covered	T43,T175,T203
DetectSt	-	-	-	-	0	1	-	Covered	T12,T22,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T22,T38
StableSt	-	-	-	-	-	-	0	Covered	T12,T22,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	101	0	0
CntIncr_A	5407980	38167	0	0
CntNoWrap_A	5407980	4942484	0	0
DetectStDropOut_A	5407980	4	0	0
DetectedOut_A	5407980	21280	0	0
DetectedPulseOut_A	5407980	44	0	0
DisabledIdleSt_A	5407980	4809202	0	0
DisabledNoDetection_A	5407980	4811086	0	0
EnterDebounceSt_A	5407980	53	0	0
EnterDetectSt_A	5407980	48	0	0
EnterStableSt_A	5407980	44	0	0
PulseIsPulse_A	5407980	44	0	0
StayInStableSt	5407980	21218	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	101	0	0
T12	1104	4	0	0
T21	7045	0	0	0
T22	0	3	0	0
T28	0	1	0	0
T32	12260	0	0	0
T38	0	4	0	0
T40	0	2	0	0
T41	0	4	0	0
T43	0	4	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	2	0	0
T120	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	38167	0	0
T12	1104	184	0	0
T21	7045	0	0	0
T22	0	30	0	0
T28	0	37	0	0
T32	12260	0	0	0
T38	0	124	0	0
T40	0	46	0	0
T41	0	52	0	0
T43	0	68	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	88	0	0
T120	0	15	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4942484	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4	0	0
T43	713	1	0	0
T54	747	0	0	0
T81	81271	0	0	0
T117	436	0	0	0
T118	493	0	0	0
T119	442	0	0	0
T159	0	1	0	0
T175	0	1	0	0
T203	0	1	0	0
T204	503	0	0	0
T205	34512	0	0	0
T206	714	0	0	0
T207	521	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	21280	0	0
T12	1104	165	0	0
T21	7045	0	0	0
T22	0	10	0	0
T32	12260	0	0	0
T38	0	77	0	0
T40	0	132	0	0
T41	0	122	0	0
T43	0	84	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	235	0	0
T120	0	8	0	0
T122	0	94	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	44	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T122	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4809202	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4811086	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	53	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T22	0	2	0	0
T28	0	1	0	0
T32	12260	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	2	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	48	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	2	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T122	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	44	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T122	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	44	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T122	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	21218	0	0
T12	1104	162	0	0
T21	7045	0	0	0
T22	0	9	0	0
T32	12260	0	0	0
T38	0	74	0	0
T40	0	130	0	0
T41	0	119	0	0
T43	0	83	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	234	0	0
T120	0	7	0	0
T122	0	92	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	26	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T22	0	1	0	0
T32	12260	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T122	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T12,T28,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T12,T28,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T12,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T28,T41
1	0	Covered	T4,T2,T3
1	1	Covered	T12,T28,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T41,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T41,T42
0	1	Covered	T12,T41,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T41,T42
1	-	Covered	T12,T41,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T28,T41
DetectSt	168	Covered	T12,T41,T42
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T12,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T41,T42
DebounceSt->IdleSt	163	Covered	T28,T172,T155
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T41,T42
IdleSt->DebounceSt	148	Covered	T12,T28,T41
StableSt->IdleSt	206	Covered	T12,T41,T81

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T28,T41
0	1	Covered	T12,T28,T41
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T41,T42
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T28,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T172,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T28,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T41,T35
StableSt	-	-	-	-	-	-	0	Covered	T12,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	58	0	0
CntIncr_A	5407980	20429	0	0
CntNoWrap_A	5407980	4942527	0	0
DetectStDropOut_A	5407980	0	0	0
DetectedOut_A	5407980	55640	0	0
DetectedPulseOut_A	5407980	27	0	0
DisabledIdleSt_A	5407980	4803905	0	0
DisabledNoDetection_A	5407980	4805793	0	0
EnterDebounceSt_A	5407980	31	0	0
EnterDetectSt_A	5407980	27	0	0
EnterStableSt_A	5407980	27	0	0
PulseIsPulse_A	5407980	27	0	0
StayInStableSt	5407980	55597	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5407980	5024	0	0
gen_low_level_sva.LowLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	58	0	0
T12	1104	2	0	0
T21	7045	0	0	0
T28	0	1	0	0
T32	12260	0	0	0
T35	0	2	0	0
T37	0	4	0	0
T41	0	2	0	0
T42	0	2	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	2	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	4	0	0
T172	0	3	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	20429	0	0
T12	1104	92	0	0
T21	7045	0	0	0
T28	0	37	0	0
T32	12260	0	0	0
T35	0	52	0	0
T37	0	178	0	0
T41	0	26	0	0
T42	0	50	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	88	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	144	0	0
T172	0	182	0	0
T188	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4942527	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	55640	0	0
T12	1104	252	0	0
T21	7045	0	0	0
T32	12260	0	0	0
T35	0	52	0	0
T37	0	341	0	0
T41	0	23	0	0
T42	0	234	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	103	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	81	0	0
T153	0	83	0	0
T172	0	189	0	0
T188	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	27	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T32	12260	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	2	0	0
T153	0	2	0	0
T172	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4803905	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4805793	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	31	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T28	0	1	0	0
T32	12260	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	2	0	0
T172	0	2	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	27	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T32	12260	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	2	0	0
T153	0	2	0	0
T172	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	27	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T32	12260	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	2	0	0
T153	0	2	0	0
T172	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	27	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T32	12260	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	1	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	2	0	0
T153	0	2	0	0
T172	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	55597	0	0
T12	1104	251	0	0
T21	7045	0	0	0
T32	12260	0	0	0
T35	0	51	0	0
T37	0	338	0	0
T41	0	22	0	0
T42	0	232	0	0
T63	21009	0	0	0
T69	490	0	0	0
T81	0	101	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	78	0	0
T153	0	80	0	0
T172	0	188	0	0
T188	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	5024	0	0
T1	1691	0	0	0
T2	13374	10	0	0
T3	21335	30	0	0
T4	502	3	0	0
T5	24510	0	0	0
T6	4608	11	0	0
T7	0	25	0	0
T8	0	33	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	1	0	0
T16	5220	25	0	0
T26	0	5	0	0
T45	0	21	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	11	0	0
T12	1104	1	0	0
T21	7045	0	0	0
T32	12260	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T63	21009	0	0	0
T69	490	0	0	0
T135	524	0	0	0
T136	411	0	0	0
T137	407	0	0	0
T138	406	0	0	0
T139	421	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T158	0	1	0	0
T172	0	1	0	0
T185	0	1	0	0
T208	0	1	0	0