Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T16,T7
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T16,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T16,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T16,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T7
1	0	Covered	T3,T7,T45
1	1	Covered	T3,T16,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T16,T7
0	1	Covered	T3,T16,T28
1	0	Covered	T3,T8,T28

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T46
0	1	Covered	T7,T45,T46
1	0	Covered	T28,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T45,T46
1	-	Covered	T7,T45,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T16,T7
DetectSt	168	Covered	T3,T16,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T45,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T16,T7
DebounceSt->IdleSt	163	Covered	T28,T236,T86
DetectSt->IdleSt	186	Covered	T3,T16,T8
DetectSt->StableSt	191	Covered	T7,T45,T46
IdleSt->DebounceSt	148	Covered	T3,T16,T7
StableSt->IdleSt	206	Covered	T7,T45,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T16,T7
0	1	Covered	T3,T16,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T16,T7
IdleSt	0	-	-	-	-	-	-	Covered	T3,T16,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T16,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T236,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T16,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T16,T8
DetectSt	-	-	-	-	0	1	-	Covered	T7,T45,T46
DetectSt	-	-	-	-	0	0	-	Covered	T3,T16,T7
StableSt	-	-	-	-	-	-	1	Covered	T7,T45,T46
StableSt	-	-	-	-	-	-	0	Covered	T7,T45,T46
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	3079	0	0
CntIncr_A	5407980	104011	0	0
CntNoWrap_A	5407980	4939506	0	0
DetectStDropOut_A	5407980	446	0	0
DetectedOut_A	5407980	75956	0	0
DetectedPulseOut_A	5407980	828	0	0
DisabledIdleSt_A	5407980	4487910	0	0
DisabledNoDetection_A	5407980	4489619	0	0
EnterDebounceSt_A	5407980	1546	0	0
EnterDetectSt_A	5407980	1533	0	0
EnterStableSt_A	5407980	828	0	0
PulseIsPulse_A	5407980	828	0	0
StayInStableSt	5407980	75004	0	0
gen_high_event_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	702	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	3079	0	0
T3	21335	22	0	0
T6	4608	0	0	0
T7	19290	18	0	0
T8	14289	30	0	0
T15	448	0	0	0
T16	5220	24	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	54	0	0
T45	8443	42	0	0
T46	0	46	0	0
T47	0	50	0	0
T55	402	0	0	0
T59	0	54	0	0
T60	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	104011	0	0
T3	21335	704	0	0
T6	4608	0	0	0
T7	19290	576	0	0
T8	14289	1752	0	0
T15	448	0	0	0
T16	5220	619	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	2052	0	0
T45	8443	966	0	0
T46	0	1495	0	0
T47	0	1900	0	0
T55	402	0	0	0
T59	0	1458	0	0
T60	0	1403	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4939506	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20898	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4795	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	446	0	0
T3	21335	7	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T8	14289	0	0	0
T15	448	0	0	0
T16	5220	12	0	0
T17	434	0	0	0
T26	503	0	0	0
T28	0	1	0	0
T45	8443	0	0	0
T55	402	0	0	0
T88	0	4	0	0
T96	0	29	0	0
T97	0	2	0	0
T100	0	9	0	0
T102	0	31	0	0
T103	0	15	0	0
T106	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	75956	0	0
T7	19290	647	0	0
T8	14289	0	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	471	0	0
T32	0	1743	0	0
T45	8443	1386	0	0
T46	10309	865	0	0
T47	0	1969	0	0
T55	402	0	0	0
T59	0	2322	0	0
T60	0	1372	0	0
T72	1267	0	0	0
T73	526	0	0	0
T218	0	88	0	0
T237	0	646	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	828	0	0
T7	19290	9	0	0
T8	14289	0	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T32	0	27	0	0
T45	8443	21	0	0
T46	10309	23	0	0
T47	0	25	0	0
T55	402	0	0	0
T59	0	27	0	0
T60	0	23	0	0
T72	1267	0	0	0
T73	526	0	0	0
T218	0	1	0	0
T237	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4487910	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	17495	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	2014	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4489619	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	17502	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	2014	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1546	0	0
T3	21335	11	0	0
T6	4608	0	0	0
T7	19290	9	0	0
T8	14289	15	0	0
T15	448	0	0	0
T16	5220	12	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	27	0	0
T45	8443	21	0	0
T46	0	23	0	0
T47	0	25	0	0
T55	402	0	0	0
T59	0	27	0	0
T60	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1533	0	0
T3	21335	11	0	0
T6	4608	0	0	0
T7	19290	9	0	0
T8	14289	15	0	0
T15	448	0	0	0
T16	5220	12	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	27	0	0
T45	8443	21	0	0
T46	0	23	0	0
T47	0	25	0	0
T55	402	0	0	0
T59	0	27	0	0
T60	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	828	0	0
T7	19290	9	0	0
T8	14289	0	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T32	0	27	0	0
T45	8443	21	0	0
T46	10309	23	0	0
T47	0	25	0	0
T55	402	0	0	0
T59	0	27	0	0
T60	0	23	0	0
T72	1267	0	0	0
T73	526	0	0	0
T218	0	1	0	0
T237	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	828	0	0
T7	19290	9	0	0
T8	14289	0	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T32	0	27	0	0
T45	8443	21	0	0
T46	10309	23	0	0
T47	0	25	0	0
T55	402	0	0	0
T59	0	27	0	0
T60	0	23	0	0
T72	1267	0	0	0
T73	526	0	0	0
T218	0	1	0	0
T237	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	75004	0	0
T7	19290	637	0	0
T8	14289	0	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	466	0	0
T32	0	1714	0	0
T45	8443	1364	0	0
T46	10309	841	0	0
T47	0	1943	0	0
T55	402	0	0	0
T59	0	2291	0	0
T60	0	1344	0	0
T72	1267	0	0	0
T73	526	0	0	0
T218	0	86	0	0
T237	0	632	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	702	0	0
T7	19290	8	0	0
T8	14289	0	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	4	0	0
T32	0	25	0	0
T45	8443	20	0	0
T46	10309	22	0	0
T47	0	24	0	0
T55	402	0	0	0
T59	0	23	0	0
T60	0	18	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	12	0	0
T238	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T15,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T15,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T15,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T85,T98,T104
1	0	Covered	T28,T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T45
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T7
1	-	Covered	T2,T6,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T15,T6
DetectSt	168	Covered	T2,T6,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T7
DebounceSt->IdleSt	163	Covered	T2,T15,T25
DetectSt->IdleSt	186	Covered	T28,T85,T98
DetectSt->StableSt	191	Covered	T2,T6,T7
IdleSt->DebounceSt	148	Covered	T2,T15,T6
StableSt->IdleSt	206	Covered	T2,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T15,T6
0	1	Covered	T2,T15,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T15,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T15,T25
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T15,T6
DetectSt	-	-	-	-	1	-	-	Covered	T28,T85,T98
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T45
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	815	0	0
CntIncr_A	5407980	48302	0	0
CntNoWrap_A	5407980	4941770	0	0
DetectStDropOut_A	5407980	26	0	0
DetectedOut_A	5407980	14856	0	0
DetectedPulseOut_A	5407980	344	0	0
DisabledIdleSt_A	5407980	4601387	0	0
DisabledNoDetection_A	5407980	4602679	0	0
EnterDebounceSt_A	5407980	442	0	0
EnterDetectSt_A	5407980	374	0	0
EnterStableSt_A	5407980	344	0	0
PulseIsPulse_A	5407980	344	0	0
StayInStableSt	5407980	14468	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	299	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	815	0	0
T2	13374	9	0	0
T3	21335	0	0	0
T6	4608	2	0	0
T7	19290	2	0	0
T10	0	11	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	1	0	0
T16	5220	0	0	0
T17	434	0	0	0
T25	0	1	0	0
T45	8443	8	0	0
T46	0	2	0	0
T47	0	6	0	0
T63	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	48302	0	0
T2	13374	451	0	0
T3	21335	0	0	0
T6	4608	25	0	0
T7	19290	82	0	0
T10	0	967	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	20	0	0
T16	5220	0	0	0
T17	434	0	0	0
T25	0	20	0	0
T45	8443	224	0	0
T46	0	81	0	0
T47	0	210	0	0
T63	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4941770	0	0
T1	1691	1290	0	0
T2	13374	12956	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	403	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	46	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	26	0	0
T52	95206	0	0	0
T85	10415	3	0	0
T98	15382	2	0	0
T104	0	5	0	0
T108	0	6	0	0
T109	0	10	0	0
T110	402	0	0	0
T111	26534	0	0	0
T112	422	0	0	0
T113	422	0	0	0
T114	14416	0	0	0
T115	502	0	0	0
T116	11716	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	14856	0	0
T2	13374	24	0	0
T3	21335	0	0	0
T6	4608	3	0	0
T7	19290	52	0	0
T10	0	362	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	3	0	0
T32	0	156	0	0
T45	8443	326	0	0
T46	0	44	0	0
T47	0	263	0	0
T59	0	102	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	344	0	0
T2	13374	4	0	0
T3	21335	0	0	0
T6	4608	1	0	0
T7	19290	1	0	0
T10	0	5	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	1	0	0
T32	0	2	0	0
T45	8443	4	0	0
T46	0	1	0	0
T47	0	3	0	0
T59	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4601387	0	0
T1	1691	1290	0	0
T2	13374	10074	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	328	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	4	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4602679	0	0
T1	1691	1291	0	0
T2	13374	10074	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	342	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	4	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	442	0	0
T2	13374	5	0	0
T3	21335	0	0	0
T6	4608	1	0	0
T7	19290	1	0	0
T10	0	6	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	1	0	0
T16	5220	0	0	0
T17	434	0	0	0
T25	0	1	0	0
T45	8443	4	0	0
T46	0	1	0	0
T47	0	3	0	0
T63	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	374	0	0
T2	13374	4	0	0
T3	21335	0	0	0
T6	4608	1	0	0
T7	19290	1	0	0
T10	0	5	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	1	0	0
T32	0	2	0	0
T45	8443	4	0	0
T46	0	1	0	0
T47	0	3	0	0
T59	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	344	0	0
T2	13374	4	0	0
T3	21335	0	0	0
T6	4608	1	0	0
T7	19290	1	0	0
T10	0	5	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	1	0	0
T32	0	2	0	0
T45	8443	4	0	0
T46	0	1	0	0
T47	0	3	0	0
T59	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	344	0	0
T2	13374	4	0	0
T3	21335	0	0	0
T6	4608	1	0	0
T7	19290	1	0	0
T10	0	5	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	1	0	0
T32	0	2	0	0
T45	8443	4	0	0
T46	0	1	0	0
T47	0	3	0	0
T59	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	14468	0	0
T2	13374	20	0	0
T3	21335	0	0	0
T6	4608	2	0	0
T7	19290	50	0	0
T10	0	357	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	2	0	0
T32	0	154	0	0
T45	8443	322	0	0
T46	0	42	0	0
T47	0	259	0	0
T59	0	98	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	299	0	0
T2	13374	4	0	0
T3	21335	0	0	0
T6	4608	1	0	0
T7	19290	0	0	0
T10	0	5	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T21	0	1	0	0
T28	0	1	0	0
T32	0	2	0	0
T33	0	6	0	0
T45	8443	4	0	0
T47	0	2	0	0
T126	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T16,T7
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T16,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T16,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T16,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T7
1	0	Covered	T3,T7,T45
1	1	Covered	T3,T16,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T16,T7
0	1	Covered	T3,T16,T32
1	0	Covered	T3,T45,T32

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T46
0	1	Covered	T7,T8,T46
1	0	Covered	T88,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T46
1	-	Covered	T7,T8,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T16,T7
DetectSt	168	Covered	T3,T16,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T8,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T16,T7
DebounceSt->IdleSt	163	Covered	T28,T236,T86
DetectSt->IdleSt	186	Covered	T3,T16,T45
DetectSt->StableSt	191	Covered	T7,T8,T46
IdleSt->DebounceSt	148	Covered	T3,T16,T7
StableSt->IdleSt	206	Covered	T7,T8,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T16,T7
0	1	Covered	T3,T16,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T16,T7
IdleSt	0	-	-	-	-	-	-	Covered	T3,T16,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T16,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T236,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T16,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T16,T45
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T46
DetectSt	-	-	-	-	0	0	-	Covered	T3,T16,T7
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T46
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T46
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	2765	0	0
CntIncr_A	5407980	91328	0	0
CntNoWrap_A	5407980	4939820	0	0
DetectStDropOut_A	5407980	343	0	0
DetectedOut_A	5407980	75867	0	0
DetectedPulseOut_A	5407980	900	0	0
DisabledIdleSt_A	5407980	4483851	0	0
DisabledNoDetection_A	5407980	4485579	0	0
EnterDebounceSt_A	5407980	1390	0	0
EnterDetectSt_A	5407980	1375	0	0
EnterStableSt_A	5407980	900	0	0
PulseIsPulse_A	5407980	900	0	0
StayInStableSt	5407980	74863	0	0
gen_high_event_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	792	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	2765	0	0
T3	21335	12	0	0
T6	4608	0	0	0
T7	19290	26	0	0
T8	14289	50	0	0
T15	448	0	0	0
T16	5220	24	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	38	0	0
T45	8443	22	0	0
T46	0	18	0	0
T47	0	54	0	0
T55	402	0	0	0
T59	0	46	0	0
T60	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	91328	0	0
T3	21335	385	0	0
T6	4608	0	0	0
T7	19290	949	0	0
T8	14289	2100	0	0
T15	448	0	0	0
T16	5220	619	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	1479	0	0
T45	8443	558	0	0
T46	0	621	0	0
T47	0	2646	0	0
T55	402	0	0	0
T59	0	1426	0	0
T60	0	1771	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4939820	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20908	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4795	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	343	0	0
T3	21335	3	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T8	14289	0	0	0
T15	448	0	0	0
T16	5220	12	0	0
T17	434	0	0	0
T26	503	0	0	0
T28	0	1	0	0
T32	0	4	0	0
T45	8443	0	0	0
T55	402	0	0	0
T88	0	18	0	0
T96	0	7	0	0
T97	0	23	0	0
T100	0	22	0	0
T102	0	31	0	0
T103	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	75867	0	0
T7	19290	638	0	0
T8	14289	1997	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	366	0	0
T45	8443	0	0	0
T46	10309	149	0	0
T47	0	2428	0	0
T55	402	0	0	0
T59	0	2011	0	0
T60	0	791	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	2154	0	0
T238	0	638	0	0
T239	0	1138	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	900	0	0
T7	19290	13	0	0
T8	14289	25	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T45	8443	0	0	0
T46	10309	9	0	0
T47	0	27	0	0
T55	402	0	0	0
T59	0	23	0	0
T60	0	23	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	29	0	0
T238	0	15	0	0
T239	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4483851	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	17495	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	2014	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4485579	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	17502	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	2014	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1390	0	0
T3	21335	6	0	0
T6	4608	0	0	0
T7	19290	13	0	0
T8	14289	25	0	0
T15	448	0	0	0
T16	5220	12	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	19	0	0
T45	8443	11	0	0
T46	0	9	0	0
T47	0	27	0	0
T55	402	0	0	0
T59	0	23	0	0
T60	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1375	0	0
T3	21335	6	0	0
T6	4608	0	0	0
T7	19290	13	0	0
T8	14289	25	0	0
T15	448	0	0	0
T16	5220	12	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	19	0	0
T45	8443	11	0	0
T46	0	9	0	0
T47	0	27	0	0
T55	402	0	0	0
T59	0	23	0	0
T60	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	900	0	0
T7	19290	13	0	0
T8	14289	25	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T45	8443	0	0	0
T46	10309	9	0	0
T47	0	27	0	0
T55	402	0	0	0
T59	0	23	0	0
T60	0	23	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	29	0	0
T238	0	15	0	0
T239	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	900	0	0
T7	19290	13	0	0
T8	14289	25	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T45	8443	0	0	0
T46	10309	9	0	0
T47	0	27	0	0
T55	402	0	0	0
T59	0	23	0	0
T60	0	23	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	29	0	0
T238	0	15	0	0
T239	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	74863	0	0
T7	19290	624	0	0
T8	14289	1970	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	361	0	0
T45	8443	0	0	0
T46	10309	140	0	0
T47	0	2400	0	0
T55	402	0	0	0
T59	0	1982	0	0
T60	0	766	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	2121	0	0
T238	0	621	0	0
T239	0	1126	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	792	0	0
T7	19290	12	0	0
T8	14289	23	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T45	8443	0	0	0
T46	10309	9	0	0
T47	0	26	0	0
T55	402	0	0	0
T59	0	17	0	0
T60	0	21	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	25	0	0
T238	0	13	0	0
T239	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T8,T47

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T3,T6
1	1	Covered	T7,T8,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T47
0	1	Covered	T84,T99,T101
1	0	Covered	T28,T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T47
0	1	Covered	T10,T63,T233
1	0	Covered	T28,T86,T87

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T47
1	-	Covered	T10,T63,T233

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T47
DetectSt	168	Covered	T7,T8,T47
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T8,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T47
DebounceSt->IdleSt	163	Covered	T63,T28,T237
DetectSt->IdleSt	186	Covered	T28,T84,T99
DetectSt->StableSt	191	Covered	T7,T8,T47
IdleSt->DebounceSt	148	Covered	T7,T8,T47
StableSt->IdleSt	206	Covered	T7,T8,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T47
0	1	Covered	T7,T8,T47
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T47
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T63,T237,T84
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T47
DetectSt	-	-	-	-	1	-	-	Covered	T28,T84,T99
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T47
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T47
StableSt	-	-	-	-	-	-	1	Covered	T10,T63,T28
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	697	0	0
CntIncr_A	5407980	39261	0	0
CntNoWrap_A	5407980	4941888	0	0
DetectStDropOut_A	5407980	37	0	0
DetectedOut_A	5407980	14135	0	0
DetectedPulseOut_A	5407980	286	0	0
DisabledIdleSt_A	5407980	4600283	0	0
DisabledNoDetection_A	5407980	4601620	0	0
EnterDebounceSt_A	5407980	370	0	0
EnterDetectSt_A	5407980	327	0	0
EnterStableSt_A	5407980	286	0	0
PulseIsPulse_A	5407980	286	0	0
StayInStableSt	5407980	13809	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	240	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	697	0	0
T7	19290	2	0	0
T8	14289	4	0	0
T10	0	24	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	8	0	0
T33	0	4	0	0
T45	8443	0	0	0
T46	10309	0	0	0
T47	0	2	0	0
T55	402	0	0	0
T59	0	10	0	0
T60	0	4	0	0
T63	0	10	0	0
T72	1267	0	0	0
T73	526	0	0	0
T233	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	39261	0	0
T7	19290	51	0	0
T8	14289	156	0	0
T10	0	1836	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	197	0	0
T33	0	648	0	0
T45	8443	0	0	0
T46	10309	0	0	0
T47	0	107	0	0
T55	402	0	0	0
T59	0	280	0	0
T60	0	148	0	0
T63	0	574	0	0
T72	1267	0	0	0
T73	526	0	0	0
T233	0	668	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4941888	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	37	0	0
T34	20937	0	0	0
T39	748	0	0	0
T65	1169	0	0	0
T84	19371	5	0	0
T99	0	1	0	0
T101	0	1	0	0
T176	0	1	0	0
T179	0	3	0	0
T218	513	0	0	0
T240	0	1	0	0
T241	0	4	0	0
T242	0	7	0	0
T243	0	3	0	0
T244	0	2	0	0
T245	425	0	0	0
T246	522	0	0	0
T247	406	0	0	0
T248	515	0	0	0
T249	408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	14135	0	0
T7	19290	83	0	0
T8	14289	119	0	0
T10	0	1133	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	102	0	0
T33	0	142	0	0
T45	8443	0	0	0
T46	10309	0	0	0
T47	0	50	0	0
T55	402	0	0	0
T59	0	368	0	0
T60	0	56	0	0
T63	0	222	0	0
T72	1267	0	0	0
T73	526	0	0	0
T233	0	121	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	286	0	0
T7	19290	1	0	0
T8	14289	2	0	0
T10	0	12	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	1	0	0
T33	0	2	0	0
T45	8443	0	0	0
T46	10309	0	0	0
T47	0	1	0	0
T55	402	0	0	0
T59	0	5	0	0
T60	0	2	0	0
T63	0	4	0	0
T72	1267	0	0	0
T73	526	0	0	0
T233	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4600283	0	0
T1	1691	1290	0	0
T2	13374	10074	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4601620	0	0
T1	1691	1291	0	0
T2	13374	10074	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	370	0	0
T7	19290	1	0	0
T8	14289	2	0	0
T10	0	12	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T33	0	2	0	0
T45	8443	0	0	0
T46	10309	0	0	0
T47	0	1	0	0
T55	402	0	0	0
T59	0	5	0	0
T60	0	2	0	0
T63	0	6	0	0
T72	1267	0	0	0
T73	526	0	0	0
T233	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	327	0	0
T7	19290	1	0	0
T8	14289	2	0	0
T10	0	12	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	3	0	0
T33	0	2	0	0
T45	8443	0	0	0
T46	10309	0	0	0
T47	0	1	0	0
T55	402	0	0	0
T59	0	5	0	0
T60	0	2	0	0
T63	0	4	0	0
T72	1267	0	0	0
T73	526	0	0	0
T233	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	286	0	0
T7	19290	1	0	0
T8	14289	2	0	0
T10	0	12	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	1	0	0
T33	0	2	0	0
T45	8443	0	0	0
T46	10309	0	0	0
T47	0	1	0	0
T55	402	0	0	0
T59	0	5	0	0
T60	0	2	0	0
T63	0	4	0	0
T72	1267	0	0	0
T73	526	0	0	0
T233	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	286	0	0
T7	19290	1	0	0
T8	14289	2	0	0
T10	0	12	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	1	0	0
T33	0	2	0	0
T45	8443	0	0	0
T46	10309	0	0	0
T47	0	1	0	0
T55	402	0	0	0
T59	0	5	0	0
T60	0	2	0	0
T63	0	4	0	0
T72	1267	0	0	0
T73	526	0	0	0
T233	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	13809	0	0
T7	19290	81	0	0
T8	14289	115	0	0
T10	0	1121	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	101	0	0
T33	0	140	0	0
T45	8443	0	0	0
T46	10309	0	0	0
T47	0	48	0	0
T55	402	0	0	0
T59	0	358	0	0
T60	0	52	0	0
T63	0	218	0	0
T72	1267	0	0	0
T73	526	0	0	0
T233	0	117	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	240	0	0
T10	41181	12	0	0
T11	518	0	0	0
T24	490	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T52	0	4	0	0
T63	0	4	0	0
T68	499	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	546	0	0	0
T85	0	1	0	0
T111	0	4	0	0
T114	0	4	0	0
T126	0	5	0	0
T162	402	0	0	0
T224	402	0	0	0
T225	426	0	0	0
T233	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T16,T7
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T16,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T16,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T16,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T7
1	0	Covered	T3,T7,T45
1	1	Covered	T3,T16,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T16,T7
0	1	Covered	T16,T28,T96
1	0	Covered	T28,T250,T251

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T45
0	1	Covered	T3,T7,T45
1	0	Covered	T28,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T45
1	-	Covered	T3,T7,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T16,T7
DetectSt	168	Covered	T3,T16,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T7,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T16,T7
DebounceSt->IdleSt	163	Covered	T28,T236,T86
DetectSt->IdleSt	186	Covered	T16,T28,T96
DetectSt->StableSt	191	Covered	T3,T7,T45
IdleSt->DebounceSt	148	Covered	T3,T16,T7
StableSt->IdleSt	206	Covered	T3,T7,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T16,T7
0	1	Covered	T3,T16,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T16,T7
IdleSt	0	-	-	-	-	-	-	Covered	T3,T16,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T16,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T236,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T16,T7
DetectSt	-	-	-	-	1	-	-	Covered	T16,T28,T96
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T45
DetectSt	-	-	-	-	0	0	-	Covered	T3,T16,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T45
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	2760	0	0
CntIncr_A	5407980	99036	0	0
CntNoWrap_A	5407980	4939825	0	0
DetectStDropOut_A	5407980	408	0	0
DetectedOut_A	5407980	72536	0	0
DetectedPulseOut_A	5407980	807	0	0
DisabledIdleSt_A	5407980	4489643	0	0
DisabledNoDetection_A	5407980	4491361	0	0
EnterDebounceSt_A	5407980	1386	0	0
EnterDetectSt_A	5407980	1374	0	0
EnterStableSt_A	5407980	807	0	0
PulseIsPulse_A	5407980	807	0	0
StayInStableSt	5407980	71615	0	0
gen_high_event_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	689	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	2760	0	0
T3	21335	18	0	0
T6	4608	0	0	0
T7	19290	50	0	0
T8	14289	40	0	0
T15	448	0	0	0
T16	5220	30	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	20	0	0
T45	8443	10	0	0
T46	0	34	0	0
T47	0	42	0	0
T55	402	0	0	0
T59	0	54	0	0
T60	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	99036	0	0
T3	21335	477	0	0
T6	4608	0	0	0
T7	19290	1575	0	0
T8	14289	1440	0	0
T15	448	0	0	0
T16	5220	768	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	600	0	0
T45	8443	165	0	0
T46	0	1309	0	0
T47	0	1617	0	0
T55	402	0	0	0
T59	0	1188	0	0
T60	0	1449	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4939825	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20902	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4789	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	408	0	0
T7	19290	0	0	0
T8	14289	0	0	0
T16	5220	15	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	1	0	0
T45	8443	0	0	0
T46	10309	0	0	0
T55	402	0	0	0
T72	1267	0	0	0
T96	0	1	0	0
T97	0	28	0	0
T100	0	25	0	0
T102	0	25	0	0
T103	0	4	0	0
T250	0	4	0	0
T251	0	7	0	0
T252	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	72536	0	0
T3	21335	1490	0	0
T6	4608	0	0	0
T7	19290	2789	0	0
T8	14289	1945	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T26	503	0	0	0
T28	0	396	0	0
T32	0	192	0	0
T45	8443	430	0	0
T46	0	1175	0	0
T47	0	972	0	0
T55	402	0	0	0
T59	0	2055	0	0
T60	0	1326	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	807	0	0
T3	21335	9	0	0
T6	4608	0	0	0
T7	19290	25	0	0
T8	14289	20	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T32	0	10	0	0
T45	8443	5	0	0
T46	0	17	0	0
T47	0	21	0	0
T55	402	0	0	0
T59	0	27	0	0
T60	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4489643	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	16114	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	2014	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4491361	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	16114	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	2014	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1386	0	0
T3	21335	9	0	0
T6	4608	0	0	0
T7	19290	25	0	0
T8	14289	20	0	0
T15	448	0	0	0
T16	5220	15	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	10	0	0
T45	8443	5	0	0
T46	0	17	0	0
T47	0	21	0	0
T55	402	0	0	0
T59	0	27	0	0
T60	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1374	0	0
T3	21335	9	0	0
T6	4608	0	0	0
T7	19290	25	0	0
T8	14289	20	0	0
T15	448	0	0	0
T16	5220	15	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	10	0	0
T45	8443	5	0	0
T46	0	17	0	0
T47	0	21	0	0
T55	402	0	0	0
T59	0	27	0	0
T60	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	807	0	0
T3	21335	9	0	0
T6	4608	0	0	0
T7	19290	25	0	0
T8	14289	20	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T32	0	10	0	0
T45	8443	5	0	0
T46	0	17	0	0
T47	0	21	0	0
T55	402	0	0	0
T59	0	27	0	0
T60	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	807	0	0
T3	21335	9	0	0
T6	4608	0	0	0
T7	19290	25	0	0
T8	14289	20	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T32	0	10	0	0
T45	8443	5	0	0
T46	0	17	0	0
T47	0	21	0	0
T55	402	0	0	0
T59	0	27	0	0
T60	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	71615	0	0
T3	21335	1474	0	0
T6	4608	0	0	0
T7	19290	2759	0	0
T8	14289	1924	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T26	503	0	0	0
T28	0	391	0	0
T32	0	182	0	0
T45	8443	424	0	0
T46	0	1158	0	0
T47	0	951	0	0
T55	402	0	0	0
T59	0	2023	0	0
T60	0	1298	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	689	0	0
T3	21335	2	0	0
T6	4608	0	0	0
T7	19290	20	0	0
T8	14289	19	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T26	503	0	0	0
T28	0	4	0	0
T32	0	10	0	0
T45	8443	4	0	0
T46	0	17	0	0
T47	0	21	0	0
T55	402	0	0	0
T59	0	22	0	0
T60	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T28,T85,T111
1	0	Covered	T28,T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
1	0	Covered	T28,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T7
1	-	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T2,T63,T28
DetectSt->IdleSt	186	Covered	T28,T85,T111
DetectSt->StableSt	191	Covered	T2,T3,T7
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T63,T84
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T28,T85,T111
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	730	0	0
CntIncr_A	5407980	41788	0	0
CntNoWrap_A	5407980	4941855	0	0
DetectStDropOut_A	5407980	20	0	0
DetectedOut_A	5407980	14053	0	0
DetectedPulseOut_A	5407980	324	0	0
DisabledIdleSt_A	5407980	4595226	0	0
DisabledNoDetection_A	5407980	4596540	0	0
EnterDebounceSt_A	5407980	383	0	0
EnterDetectSt_A	5407980	347	0	0
EnterStableSt_A	5407980	324	0	0
PulseIsPulse_A	5407980	324	0	0
StayInStableSt	5407980	13694	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	287	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	730	0	0
T2	13374	5	0	0
T3	21335	14	0	0
T6	4608	0	0	0
T7	19290	8	0	0
T8	0	4	0	0
T10	0	20	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	8	0	0
T45	8443	2	0	0
T59	0	10	0	0
T60	0	4	0	0
T63	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	41788	0	0
T2	13374	201	0	0
T3	21335	357	0	0
T6	4608	0	0	0
T7	19290	236	0	0
T8	0	98	0	0
T10	0	2420	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	221	0	0
T45	8443	32	0	0
T59	0	310	0	0
T60	0	120	0	0
T63	0	651	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4941855	0	0
T1	1691	1290	0	0
T2	13374	12960	0	0
T3	21335	20906	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	20	0	0
T28	7577	1	0	0
T33	33613	0	0	0
T41	117943	0	0	0
T44	611	0	0	0
T64	1711	0	0	0
T71	492	0	0	0
T85	0	1	0	0
T111	0	3	0	0
T216	423	0	0	0
T233	21818	0	0	0
T234	433	0	0	0
T235	980	0	0	0
T240	0	4	0	0
T244	0	1	0	0
T253	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	14053	0	0
T2	13374	58	0	0
T3	21335	165	0	0
T6	4608	0	0	0
T7	19290	300	0	0
T8	0	181	0	0
T10	0	43	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	102	0	0
T45	8443	77	0	0
T59	0	339	0	0
T60	0	85	0	0
T63	0	240	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	324	0	0
T2	13374	2	0	0
T3	21335	7	0	0
T6	4608	0	0	0
T7	19290	4	0	0
T8	0	2	0	0
T10	0	10	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	1	0	0
T45	8443	1	0	0
T59	0	5	0	0
T60	0	2	0	0
T63	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4595226	0	0
T1	1691	1290	0	0
T2	13374	10074	0	0
T3	21335	19437	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4596540	0	0
T1	1691	1291	0	0
T2	13374	10074	0	0
T3	21335	19438	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	383	0	0
T2	13374	3	0	0
T3	21335	7	0	0
T6	4608	0	0	0
T7	19290	4	0	0
T8	0	2	0	0
T10	0	10	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	5	0	0
T45	8443	1	0	0
T59	0	5	0	0
T60	0	2	0	0
T63	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	347	0	0
T2	13374	2	0	0
T3	21335	7	0	0
T6	4608	0	0	0
T7	19290	4	0	0
T8	0	2	0	0
T10	0	10	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	3	0	0
T45	8443	1	0	0
T59	0	5	0	0
T60	0	2	0	0
T63	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	324	0	0
T2	13374	2	0	0
T3	21335	7	0	0
T6	4608	0	0	0
T7	19290	4	0	0
T8	0	2	0	0
T10	0	10	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	1	0	0
T45	8443	1	0	0
T59	0	5	0	0
T60	0	2	0	0
T63	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	324	0	0
T2	13374	2	0	0
T3	21335	7	0	0
T6	4608	0	0	0
T7	19290	4	0	0
T8	0	2	0	0
T10	0	10	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	1	0	0
T45	8443	1	0	0
T59	0	5	0	0
T60	0	2	0	0
T63	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	13694	0	0
T2	13374	56	0	0
T3	21335	158	0	0
T6	4608	0	0	0
T7	19290	294	0	0
T8	0	179	0	0
T10	0	33	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	101	0	0
T45	8443	75	0	0
T59	0	329	0	0
T60	0	81	0	0
T63	0	235	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	287	0	0
T2	13374	2	0	0
T3	21335	7	0	0
T6	4608	0	0	0
T7	19290	2	0	0
T8	0	2	0	0
T10	0	10	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T33	0	1	0	0
T45	8443	0	0	0
T63	0	5	0	0
T84	0	3	0	0
T126	0	8	0	0
T233	0	4	0	0