Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T16,T7
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T16,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T16,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T16,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T7
1	0	Covered	T3,T7,T45
1	1	Covered	T3,T16,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T16,T7
0	1	Covered	T3,T16,T32
1	0	Covered	T32,T28,T239

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T8
0	1	Covered	T7,T45,T8
1	0	Covered	T254,T255

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T45,T8
1	-	Covered	T7,T45,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T16,T7
DetectSt	168	Covered	T3,T16,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T45,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T16,T7
DebounceSt->IdleSt	163	Covered	T28,T236,T86
DetectSt->IdleSt	186	Covered	T3,T16,T32
DetectSt->StableSt	191	Covered	T7,T45,T8
IdleSt->DebounceSt	148	Covered	T3,T16,T7
StableSt->IdleSt	206	Covered	T7,T45,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T16,T7
0	1	Covered	T3,T16,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T16,T7
IdleSt	0	-	-	-	-	-	-	Covered	T3,T16,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T16,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T236,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T16,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T16,T32
DetectSt	-	-	-	-	0	1	-	Covered	T7,T45,T8
DetectSt	-	-	-	-	0	0	-	Covered	T3,T16,T7
StableSt	-	-	-	-	-	-	1	Covered	T7,T45,T8
StableSt	-	-	-	-	-	-	0	Covered	T7,T45,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	2937	0	0
CntIncr_A	5407980	102287	0	0
CntNoWrap_A	5407980	4939648	0	0
DetectStDropOut_A	5407980	402	0	0
DetectedOut_A	5407980	79241	0	0
DetectedPulseOut_A	5407980	870	0	0
DisabledIdleSt_A	5407980	4486422	0	0
DisabledNoDetection_A	5407980	4488144	0	0
EnterDebounceSt_A	5407980	1477	0	0
EnterDetectSt_A	5407980	1461	0	0
EnterStableSt_A	5407980	870	0	0
PulseIsPulse_A	5407980	870	0	0
StayInStableSt	5407980	78261	0	0
gen_high_event_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	751	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	2937	0	0
T3	21335	18	0	0
T6	4608	0	0	0
T7	19290	34	0	0
T8	14289	50	0	0
T15	448	0	0	0
T16	5220	66	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	52	0	0
T45	8443	22	0	0
T46	0	18	0	0
T47	0	20	0	0
T55	402	0	0	0
T59	0	16	0	0
T60	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	102287	0	0
T3	21335	572	0	0
T6	4608	0	0	0
T7	19290	1292	0	0
T8	14289	1500	0	0
T15	448	0	0	0
T16	5220	1712	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	2029	0	0
T45	8443	319	0	0
T46	0	522	0	0
T47	0	730	0	0
T55	402	0	0	0
T59	0	384	0	0
T60	0	1430	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4939648	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	20902	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4753	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	402	0	0
T3	21335	9	0	0
T6	4608	0	0	0
T7	19290	0	0	0
T8	14289	0	0	0
T15	448	0	0	0
T16	5220	33	0	0
T17	434	0	0	0
T26	503	0	0	0
T28	0	1	0	0
T32	0	5	0	0
T45	8443	0	0	0
T55	402	0	0	0
T96	0	28	0	0
T97	0	11	0	0
T100	0	25	0	0
T102	0	8	0	0
T251	0	15	0	0
T256	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	79241	0	0
T7	19290	1661	0	0
T8	14289	2597	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	431	0	0
T45	8443	1157	0	0
T46	10309	248	0	0
T47	0	493	0	0
T55	402	0	0	0
T59	0	693	0	0
T60	0	2341	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	2096	0	0
T238	0	603	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	870	0	0
T7	19290	17	0	0
T8	14289	25	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T45	8443	11	0	0
T46	10309	9	0	0
T47	0	10	0	0
T55	402	0	0	0
T59	0	8	0	0
T60	0	26	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	29	0	0
T238	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4486422	0	0
T1	1691	1290	0	0
T2	13374	12965	0	0
T3	21335	17495	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	2014	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4488144	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	17502	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	2014	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1477	0	0
T3	21335	9	0	0
T6	4608	0	0	0
T7	19290	17	0	0
T8	14289	25	0	0
T15	448	0	0	0
T16	5220	33	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	26	0	0
T45	8443	11	0	0
T46	0	9	0	0
T47	0	10	0	0
T55	402	0	0	0
T59	0	8	0	0
T60	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	1461	0	0
T3	21335	9	0	0
T6	4608	0	0	0
T7	19290	17	0	0
T8	14289	25	0	0
T15	448	0	0	0
T16	5220	33	0	0
T17	434	0	0	0
T26	503	0	0	0
T32	0	26	0	0
T45	8443	11	0	0
T46	0	9	0	0
T47	0	10	0	0
T55	402	0	0	0
T59	0	8	0	0
T60	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	870	0	0
T7	19290	17	0	0
T8	14289	25	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T45	8443	11	0	0
T46	10309	9	0	0
T47	0	10	0	0
T55	402	0	0	0
T59	0	8	0	0
T60	0	26	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	29	0	0
T238	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	870	0	0
T7	19290	17	0	0
T8	14289	25	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T45	8443	11	0	0
T46	10309	9	0	0
T47	0	10	0	0
T55	402	0	0	0
T59	0	8	0	0
T60	0	26	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	29	0	0
T238	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	78261	0	0
T7	19290	1642	0	0
T8	14289	2570	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	426	0	0
T45	8443	1145	0	0
T46	10309	239	0	0
T47	0	483	0	0
T55	402	0	0	0
T59	0	683	0	0
T60	0	2309	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	2063	0	0
T238	0	598	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	751	0	0
T7	19290	15	0	0
T8	14289	23	0	0
T17	434	0	0	0
T25	1776	0	0	0
T26	503	0	0	0
T28	0	5	0	0
T45	8443	10	0	0
T46	10309	9	0	0
T47	0	10	0	0
T55	402	0	0	0
T59	0	6	0	0
T60	0	20	0	0
T72	1267	0	0	0
T73	526	0	0	0
T237	0	25	0	0
T238	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T7,T45

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T45
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T7,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T45
0	1	Covered	T85,T116,T99
1	0	Covered	T28,T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T45
0	1	Covered	T2,T7,T8
1	0	Covered	T257

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T45
1	-	Covered	T2,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T45
DetectSt	168	Covered	T2,T7,T45
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T7,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T45
DebounceSt->IdleSt	163	Covered	T2,T45,T10
DetectSt->IdleSt	186	Covered	T28,T85,T116
DetectSt->StableSt	191	Covered	T2,T7,T45
IdleSt->DebounceSt	148	Covered	T2,T7,T45
StableSt->IdleSt	206	Covered	T2,T7,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T45
0	1	Covered	T2,T7,T45
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T45
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T45,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T45
DetectSt	-	-	-	-	1	-	-	Covered	T28,T85,T116
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T45
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T45
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5407980	844	0	0
CntIncr_A	5407980	50194	0	0
CntNoWrap_A	5407980	4941741	0	0
DetectStDropOut_A	5407980	78	0	0
DetectedOut_A	5407980	17403	0	0
DetectedPulseOut_A	5407980	320	0	0
DisabledIdleSt_A	5407980	4591674	0	0
DisabledNoDetection_A	5407980	4593005	0	0
EnterDebounceSt_A	5407980	442	0	0
EnterDetectSt_A	5407980	402	0	0
EnterStableSt_A	5407980	320	0	0
PulseIsPulse_A	5407980	320	0	0
StayInStableSt	5407980	17042	0	0
gen_high_level_sva.HighLevelEvent_A	5407980	4944508	0	0
gen_not_sticky_sva.StableStDropOut_A	5407980	276	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	844	0	0
T2	13374	10	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	10	0	0
T8	0	2	0	0
T10	0	11	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	8	0	0
T45	8443	3	0	0
T59	0	2	0	0
T60	0	12	0	0
T63	0	5	0	0
T233	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	50194	0	0
T2	13374	450	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	225	0	0
T8	0	68	0	0
T10	0	997	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	260	0	0
T45	8443	53	0	0
T59	0	43	0	0
T60	0	366	0	0
T63	0	333	0	0
T233	0	1560	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4941741	0	0
T1	1691	1290	0	0
T2	13374	12955	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	78	0	0
T52	95206	0	0	0
T85	10415	6	0	0
T98	15382	0	0	0
T99	0	3	0	0
T110	402	0	0	0
T111	26534	0	0	0
T112	422	0	0	0
T113	422	0	0	0
T114	14416	0	0	0
T115	502	0	0	0
T116	11716	8	0	0
T174	0	10	0	0
T258	0	8	0	0
T259	0	2	0	0
T260	0	8	0	0
T261	0	7	0	0
T262	0	13	0	0
T263	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	17403	0	0
T2	13374	70	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	451	0	0
T8	0	70	0	0
T10	0	337	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	102	0	0
T45	8443	69	0	0
T59	0	87	0	0
T60	0	247	0	0
T63	0	65	0	0
T233	0	418	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	320	0	0
T2	13374	4	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	5	0	0
T8	0	1	0	0
T10	0	5	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	1	0	0
T45	8443	1	0	0
T59	0	1	0	0
T60	0	6	0	0
T63	0	2	0	0
T233	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4591674	0	0
T1	1691	1290	0	0
T2	13374	10074	0	0
T3	21335	20920	0	0
T4	502	101	0	0
T5	24510	24109	0	0
T6	4608	405	0	0
T13	814	413	0	0
T14	403	2	0	0
T15	448	47	0	0
T16	5220	4819	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4593005	0	0
T1	1691	1291	0	0
T2	13374	10074	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	442	0	0
T2	13374	6	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	5	0	0
T8	0	1	0	0
T10	0	6	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	5	0	0
T45	8443	2	0	0
T59	0	1	0	0
T60	0	6	0	0
T63	0	3	0	0
T233	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	402	0	0
T2	13374	4	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	5	0	0
T8	0	1	0	0
T10	0	5	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	3	0	0
T45	8443	1	0	0
T59	0	1	0	0
T60	0	6	0	0
T63	0	2	0	0
T233	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	320	0	0
T2	13374	4	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	5	0	0
T8	0	1	0	0
T10	0	5	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	1	0	0
T45	8443	1	0	0
T59	0	1	0	0
T60	0	6	0	0
T63	0	2	0	0
T233	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	320	0	0
T2	13374	4	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	5	0	0
T8	0	1	0	0
T10	0	5	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	1	0	0
T45	8443	1	0	0
T59	0	1	0	0
T60	0	6	0	0
T63	0	2	0	0
T233	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	17042	0	0
T2	13374	66	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	446	0	0
T8	0	69	0	0
T10	0	332	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T28	0	101	0	0
T45	8443	67	0	0
T59	0	85	0	0
T60	0	235	0	0
T63	0	63	0	0
T233	0	408	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	4944508	0	0
T1	1691	1291	0	0
T2	13374	12970	0	0
T3	21335	20928	0	0
T4	502	102	0	0
T5	24510	24110	0	0
T6	4608	420	0	0
T13	814	414	0	0
T14	403	3	0	0
T15	448	48	0	0
T16	5220	4820	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407980	276	0	0
T2	13374	4	0	0
T3	21335	0	0	0
T6	4608	0	0	0
T7	19290	5	0	0
T8	0	1	0	0
T10	0	5	0	0
T13	814	0	0	0
T14	403	0	0	0
T15	448	0	0	0
T16	5220	0	0	0
T17	434	0	0	0
T33	0	10	0	0
T45	8443	0	0	0
T63	0	2	0	0
T84	0	3	0	0
T126	0	4	0	0
T233	0	10	0	0
T237	0	2	0	0