Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1144834408	11381	0	0
auto_block_debounce_ctl_rd_A	1144834408	1436	0	0
auto_block_out_ctl_rd_A	1144834408	1811	0	0
com_det_ctl_0_rd_A	1144834408	3292	0	0
com_det_ctl_1_rd_A	1144834408	3275	0	0
com_det_ctl_2_rd_A	1144834408	3466	0	0
com_det_ctl_3_rd_A	1144834408	3393	0	0
com_out_ctl_0_rd_A	1144834408	3928	0	0
com_out_ctl_1_rd_A	1144834408	3883	0	0
com_out_ctl_2_rd_A	1144834408	3655	0	0
com_out_ctl_3_rd_A	1144834408	3775	0	0
com_pre_det_ctl_0_rd_A	1144834408	1139	0	0
com_pre_det_ctl_1_rd_A	1144834408	1134	0	0
com_pre_det_ctl_2_rd_A	1144834408	1130	0	0
com_pre_det_ctl_3_rd_A	1144834408	1157	0	0
com_pre_sel_ctl_0_rd_A	1144834408	3907	0	0
com_pre_sel_ctl_1_rd_A	1144834408	3833	0	0
com_pre_sel_ctl_2_rd_A	1144834408	3880	0	0
com_pre_sel_ctl_3_rd_A	1144834408	3974	0	0
com_sel_ctl_0_rd_A	1144834408	3982	0	0
com_sel_ctl_1_rd_A	1144834408	3783	0	0
com_sel_ctl_2_rd_A	1144834408	3785	0	0
com_sel_ctl_3_rd_A	1144834408	3679	0	0
ec_rst_ctl_rd_A	1144834408	1938	0	0
intr_enable_rd_A	1144834408	1506	0	0
key_intr_ctl_rd_A	1144834408	2645	0	0
key_intr_debounce_ctl_rd_A	1144834408	1202	0	0
key_invert_ctl_rd_A	1144834408	3536	0	0
pin_allowed_ctl_rd_A	1144834408	4065	0	0
pin_out_ctl_rd_A	1144834408	2440	0	0
pin_out_value_rd_A	1144834408	2869	0	0
regwen_rd_A	1144834408	1212	0	0
ulp_ac_debounce_ctl_rd_A	1144834408	1320	0	0
ulp_ctl_rd_A	1144834408	1210	0	0
ulp_lid_debounce_ctl_rd_A	1144834408	1267	0	0
ulp_pwrb_debounce_ctl_rd_A	1144834408	1258	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	11381	0	0
T6	529953	8	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	9	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T67	0	19	0	0
T72	126682	4	0	0
T81	0	10	0	0
T120	0	13	0	0
T206	0	7	0	0
T235	0	11	0	0
T294	0	6	0	0
T295	0	7	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1436	0	0
T6	529953	46	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	38	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T54	0	17	0	0
T55	197450	0	0	0
T72	126682	21	0	0
T81	0	38	0	0
T296	0	16	0	0
T297	0	26	0	0
T298	0	12	0	0
T299	0	42	0	0
T300	0	17	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1811	0	0
T6	529953	45	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	8	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T54	0	18	0	0
T55	197450	0	0	0
T72	126682	30	0	0
T81	0	35	0	0
T296	0	2	0	0
T297	0	38	0	0
T298	0	18	0	0
T299	0	38	0	0
T300	0	7	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3292	0	0
T6	529953	34	0	0
T7	472608	54	0	0
T8	664429	48	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	28	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	22	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	28	0	0
T85	0	35	0	0
T88	0	62	0	0
T239	0	74	0	0
T301	0	52	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3275	0	0
T6	529953	24	0	0
T7	472608	52	0	0
T8	664429	36	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	28	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	40	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	16	0	0
T85	0	34	0	0
T88	0	55	0	0
T239	0	64	0	0
T301	0	57	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3466	0	0
T6	529953	40	0	0
T7	472608	62	0	0
T8	664429	43	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	31	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	54	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	16	0	0
T85	0	53	0	0
T88	0	44	0	0
T239	0	81	0	0
T301	0	54	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3393	0	0
T6	529953	30	0	0
T7	472608	61	0	0
T8	664429	51	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	26	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	17	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	17	0	0
T85	0	55	0	0
T88	0	54	0	0
T239	0	54	0	0
T301	0	62	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3928	0	0
T6	529953	45	0	0
T7	472608	59	0	0
T8	664429	43	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	40	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	18	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	27	0	0
T85	0	53	0	0
T88	0	55	0	0
T239	0	94	0	0
T301	0	70	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3883	0	0
T6	529953	34	0	0
T7	472608	59	0	0
T8	664429	39	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	31	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	36	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	18	0	0
T85	0	39	0	0
T88	0	35	0	0
T239	0	68	0	0
T301	0	71	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3655	0	0
T6	529953	42	0	0
T7	472608	61	0	0
T8	664429	37	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	35	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	37	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	4	0	0
T85	0	42	0	0
T88	0	48	0	0
T239	0	67	0	0
T301	0	42	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3775	0	0
T6	529953	29	0	0
T7	472608	52	0	0
T8	664429	26	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	34	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	14	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	23	0	0
T85	0	51	0	0
T88	0	59	0	0
T239	0	88	0	0
T301	0	34	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1139	0	0
T6	529953	22	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	20	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	8	0	0
T81	0	27	0	0
T297	0	35	0	0
T299	0	40	0	0
T300	0	24	0	0
T302	0	7	0	0
T303	0	18	0	0
T304	0	19	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1134	0	0
T6	529953	37	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	18	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	14	0	0
T81	0	28	0	0
T297	0	53	0	0
T299	0	43	0	0
T300	0	18	0	0
T303	0	9	0	0
T304	0	14	0	0
T305	0	11	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1130	0	0
T6	529953	44	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	30	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	23	0	0
T81	0	35	0	0
T297	0	50	0	0
T299	0	25	0	0
T300	0	10	0	0
T303	0	11	0	0
T304	0	34	0	0
T305	0	16	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1157	0	0
T6	529953	48	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	32	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	26	0	0
T81	0	52	0	0
T297	0	26	0	0
T299	0	48	0	0
T300	0	22	0	0
T303	0	16	0	0
T304	0	8	0	0
T305	0	5	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3907	0	0
T6	529953	34	0	0
T7	472608	60	0	0
T8	664429	38	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	39	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	22	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	16	0	0
T85	0	26	0	0
T88	0	43	0	0
T239	0	72	0	0
T301	0	64	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3833	0	0
T6	529953	53	0	0
T7	472608	60	0	0
T8	664429	42	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	32	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	23	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	19	0	0
T85	0	34	0	0
T88	0	53	0	0
T239	0	83	0	0
T301	0	77	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3880	0	0
T6	529953	40	0	0
T7	472608	61	0	0
T8	664429	48	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	30	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	18	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	16	0	0
T85	0	50	0	0
T88	0	57	0	0
T239	0	67	0	0
T301	0	52	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3974	0	0
T6	529953	43	0	0
T7	472608	65	0	0
T8	664429	38	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	36	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	8	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	8	0	0
T85	0	26	0	0
T88	0	65	0	0
T239	0	80	0	0
T301	0	52	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3982	0	0
T6	529953	19	0	0
T7	472608	49	0	0
T8	664429	36	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	40	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	7	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	30	0	0
T85	0	17	0	0
T88	0	54	0	0
T239	0	75	0	0
T301	0	75	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3783	0	0
T6	529953	38	0	0
T7	472608	67	0	0
T8	664429	49	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	31	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	26	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	17	0	0
T85	0	35	0	0
T88	0	45	0	0
T239	0	72	0	0
T301	0	58	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3785	0	0
T6	529953	44	0	0
T7	472608	60	0	0
T8	664429	36	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	43	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	42	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	17	0	0
T85	0	37	0	0
T88	0	50	0	0
T239	0	67	0	0
T301	0	32	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3679	0	0
T6	529953	30	0	0
T7	472608	63	0	0
T8	664429	40	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	33	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	27	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	33	0	0
T85	0	27	0	0
T88	0	45	0	0
T239	0	56	0	0
T301	0	68	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1938	0	0
T6	529953	41	0	0
T7	472608	15	0	0
T8	664429	6	0	0
T9	0	3	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	41	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T32	0	13	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	19	0	0
T88	0	10	0	0
T239	0	27	0	0
T301	0	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1506	0	0
T6	529953	58	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	18	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	26	0	0
T81	0	36	0	0
T297	0	48	0	0
T299	0	31	0	0
T300	0	27	0	0
T302	0	8	0	0
T303	0	20	0	0
T304	0	20	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	2645	0	0
T6	529953	47	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T9	0	10	0	0
T11	0	8	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	24	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T38	0	3	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	21	0	0
T81	0	47	0	0
T122	0	3	0	0
T151	0	6	0	0
T207	0	1	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1202	0	0
T6	529953	48	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	27	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	16	0	0
T81	0	36	0	0
T297	0	43	0	0
T299	0	48	0	0
T300	0	23	0	0
T302	0	3	0	0
T303	0	10	0	0
T304	0	12	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	3536	0	0
T6	529953	105	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	110	0	0
T23	0	41	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T70	0	36	0	0
T72	126682	25	0	0
T81	0	34	0	0
T118	0	62	0	0
T297	0	46	0	0
T306	0	65	0	0
T307	0	62	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	4065	0	0
T6	529953	29	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	42	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T57	0	96	0	0
T72	126682	23	0	0
T81	0	33	0	0
T297	0	31	0	0
T308	0	42	0	0
T309	0	84	0	0
T310	0	25	0	0
T311	0	42	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	2440	0	0
T6	529953	37	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	39	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T57	0	43	0	0
T72	126682	7	0	0
T81	0	26	0	0
T297	0	47	0	0
T308	0	52	0	0
T309	0	76	0	0
T310	0	40	0	0
T311	0	65	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	2869	0	0
T6	529953	42	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	24	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T57	0	84	0	0
T72	126682	27	0	0
T81	0	50	0	0
T297	0	44	0	0
T308	0	40	0	0
T309	0	72	0	0
T310	0	61	0	0
T311	0	80	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1212	0	0
T6	529953	45	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	42	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T72	126682	19	0	0
T81	0	39	0	0
T297	0	32	0	0
T299	0	40	0	0
T300	0	11	0	0
T302	0	9	0	0
T303	0	26	0	0
T304	0	11	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1320	0	0
T6	529953	46	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	35	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T64	0	9	0	0
T72	126682	18	0	0
T81	0	52	0	0
T89	0	1	0	0
T129	0	5	0	0
T297	0	43	0	0
T312	0	4	0	0
T313	0	12	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1210	0	0
T6	529953	35	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	64	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T64	0	7	0	0
T72	126682	15	0	0
T81	0	25	0	0
T89	0	1	0	0
T129	0	9	0	0
T297	0	51	0	0
T312	0	10	0	0
T313	0	7	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1267	0	0
T6	529953	37	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	34	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T64	0	14	0	0
T72	126682	21	0	0
T81	0	49	0	0
T89	0	3	0	0
T129	0	3	0	0
T297	0	47	0	0
T312	0	1	0	0
T313	0	7	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144834408	1258	0	0
T6	529953	25	0	0
T7	472608	0	0	0
T8	664429	0	0	0
T16	600410	0	0	0
T17	10849	0	0	0
T21	0	37	0	0
T25	213173	0	0	0
T26	120875	0	0	0
T45	405264	0	0	0
T55	197450	0	0	0
T64	0	14	0	0
T72	126682	24	0	0
T81	0	56	0	0
T89	0	8	0	0
T130	0	12	0	0
T297	0	37	0	0
T312	0	3	0	0
T313	0	1	0	0