Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.27	96.41	100.00	96.79	98.67	99.52	93.86

Total tests in report: 921

---

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
51.39	51.39	72.68	72.68	56.70	56.70	63.70	63.70	11.54	11.54	74.23	74.23	62.52	62.52	18.36	18.36	/workspace/coverage/default/40.sysrst_ctrl_combo_detect.2888536329
67.70	16.31	87.42	14.74	76.04	19.34	67.12	3.42	53.21	41.67	87.65	13.42	80.83	18.30	21.61	3.25	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.63759340
74.82	7.12	91.06	3.64	82.41	6.37	95.21	28.08	53.21	0.00	91.16	3.51	82.37	1.54	28.34	6.73	/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1075670789
81.57	6.75	94.31	3.25	85.44	3.03	95.43	0.23	77.56	24.36	93.31	2.14	90.46	8.09	34.47	6.14	/workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.4292611265
84.12	2.55	94.98	0.67	85.84	0.40	95.43	0.00	83.33	5.77	93.86	0.55	92.49	2.02	42.92	8.44	/workspace/coverage/default/17.sysrst_ctrl_stress_all.1361906555
85.88	1.76	96.66	1.68	89.41	3.56	95.89	0.46	83.33	0.00	95.49	1.63	93.06	0.58	47.34	4.43	/workspace/coverage/default/39.sysrst_ctrl_stress_all.3091994060
87.33	1.45	97.57	0.91	91.23	1.82	96.58	0.68	87.18	3.85	96.93	1.44	94.12	1.06	47.70	0.35	/workspace/coverage/default/34.sysrst_ctrl_stress_all.3047723607
88.65	1.32	97.59	0.02	92.34	1.11	97.26	0.68	87.18	0.00	96.97	0.04	94.12	0.00	55.08	7.38	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.203962787
89.43	0.78	97.91	0.32	92.85	0.51	97.26	0.00	89.10	1.92	97.26	0.30	94.80	0.67	56.85	1.77	/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3818137527
90.21	0.78	97.91	0.00	92.85	0.00	97.26	0.00	89.10	0.00	97.26	0.00	94.80	0.00	62.28	5.43	/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3535963594
90.93	0.72	97.97	0.06	93.12	0.28	97.26	0.00	89.10	0.00	97.26	0.00	94.89	0.10	66.88	4.60	/workspace/coverage/default/29.sysrst_ctrl_combo_detect.3223734273
91.50	0.58	98.13	0.17	93.23	0.10	97.26	0.00	89.10	0.00	97.30	0.04	94.89	0.00	70.60	3.72	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2670026173
92.00	0.50	98.13	0.00	93.48	0.25	98.17	0.91	89.10	0.00	97.34	0.04	95.38	0.48	72.43	1.83	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3722278596
92.47	0.47	98.17	0.04	93.50	0.03	98.17	0.00	89.74	0.64	97.38	0.04	95.47	0.10	74.85	2.42	/workspace/coverage/default/10.sysrst_ctrl_stress_all.867985868
92.88	0.41	98.21	0.04	93.58	0.08	98.17	0.00	89.74	0.00	97.38	0.00	95.47	0.00	77.63	2.77	/workspace/coverage/default/25.sysrst_ctrl_combo_detect.4102920999
93.24	0.36	98.21	0.00	93.63	0.05	98.17	0.00	89.74	0.00	97.38	0.00	95.76	0.29	79.81	2.18	/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2242152581
93.56	0.31	98.36	0.15	93.78	0.15	98.17	0.00	91.03	1.28	97.60	0.22	96.15	0.39	79.81	0.00	/workspace/coverage/default/13.sysrst_ctrl_edge_detect.1845736949
93.84	0.29	98.36	0.00	93.81	0.03	99.77	1.60	91.03	0.00	97.60	0.00	96.24	0.10	80.11	0.30	/workspace/coverage/default/4.sysrst_ctrl_sec_cm.713887696
94.09	0.25	98.43	0.07	93.86	0.05	99.77	0.00	92.31	1.28	97.67	0.07	96.44	0.19	80.17	0.06	/workspace/coverage/default/15.sysrst_ctrl_edge_detect.3750727318
94.33	0.24	98.43	0.00	93.86	0.00	99.77	0.00	92.31	0.00	97.67	0.00	96.44	0.00	81.82	1.65	/workspace/coverage/default/39.sysrst_ctrl_combo_detect.1986850172
94.54	0.21	98.49	0.06	94.19	0.33	99.77	0.00	92.95	0.64	97.74	0.07	96.82	0.39	81.82	0.00	/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.624892749
94.74	0.20	98.51	0.02	94.19	0.00	99.77	0.00	92.95	0.00	97.74	0.00	96.82	0.00	83.18	1.36	/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1400207137
94.90	0.17	98.51	0.00	94.26	0.08	99.77	0.00	92.95	0.00	97.78	0.04	96.82	0.00	84.24	1.06	/workspace/coverage/default/11.sysrst_ctrl_pin_override_test.3080032920
95.07	0.16	98.51	0.00	94.36	0.10	99.77	0.00	92.95	0.00	97.78	0.00	97.50	0.67	84.59	0.35	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3385189929
95.22	0.16	98.58	0.07	94.44	0.08	99.77	0.00	93.59	0.64	97.89	0.11	97.69	0.19	84.59	0.00	/workspace/coverage/default/30.sysrst_ctrl_edge_detect.2985242652
95.37	0.15	98.64	0.06	94.51	0.08	99.77	0.00	94.23	0.64	97.97	0.07	97.88	0.19	84.59	0.00	/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3387300948
95.52	0.14	98.68	0.04	94.54	0.03	99.77	0.00	94.87	0.64	98.00	0.04	97.98	0.10	84.77	0.18	/workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2267815452
95.66	0.14	98.68	0.00	94.57	0.03	99.77	0.00	94.87	0.00	98.00	0.00	98.07	0.10	85.66	0.89	/workspace/coverage/default/27.sysrst_ctrl_stress_all.1566045685
95.80	0.14	98.68	0.00	94.57	0.00	99.77	0.00	94.87	0.00	98.00	0.00	98.07	0.00	86.66	1.00	/workspace/coverage/default/12.sysrst_ctrl_pin_access_test.3778506337
95.94	0.13	98.71	0.04	95.35	0.78	99.77	0.00	94.87	0.00	98.00	0.00	98.07	0.00	86.78	0.12	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.88666435
96.07	0.13	98.75	0.04	95.35	0.00	99.77	0.00	94.87	0.00	98.00	0.00	98.07	0.00	87.66	0.89	/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.753582024
96.20	0.13	98.79	0.04	95.40	0.05	99.77	0.00	95.51	0.64	98.04	0.04	98.17	0.10	87.72	0.06	/workspace/coverage/default/45.sysrst_ctrl_stress_all.3054796113
96.32	0.12	98.79	0.00	95.40	0.00	99.77	0.00	95.51	0.00	98.04	0.00	99.04	0.87	87.72	0.00	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3935187963
96.44	0.12	98.82	0.04	95.42	0.03	99.77	0.00	96.15	0.64	98.08	0.04	99.13	0.10	87.72	0.00	/workspace/coverage/default/16.sysrst_ctrl_edge_detect.4023896184
96.56	0.12	98.86	0.04	95.45	0.03	99.77	0.00	96.79	0.64	98.11	0.04	99.23	0.10	87.72	0.00	/workspace/coverage/default/26.sysrst_ctrl_edge_detect.2406825712
96.67	0.10	98.92	0.06	95.48	0.03	99.77	0.00	96.79	0.00	98.11	0.00	99.23	0.00	88.37	0.65	/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1219760295
96.76	0.09	98.92	0.00	95.48	0.00	99.77	0.00	96.79	0.00	98.11	0.00	99.23	0.00	89.02	0.65	/workspace/coverage/default/43.sysrst_ctrl_combo_detect.1907467082
96.85	0.09	98.97	0.06	95.78	0.30	99.77	0.00	96.79	0.00	98.26	0.15	99.33	0.10	89.02	0.00	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1473544562
96.91	0.07	98.97	0.00	95.78	0.00	99.77	0.00	96.79	0.00	98.26	0.00	99.33	0.00	89.49	0.47	/workspace/coverage/default/21.sysrst_ctrl_pin_override_test.2509777690
96.98	0.07	98.97	0.00	95.78	0.00	99.77	0.00	96.79	0.00	98.26	0.00	99.33	0.00	89.96	0.47	/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1731967403
97.04	0.06	99.01	0.04	95.88	0.10	99.77	0.00	96.79	0.00	98.34	0.07	99.52	0.19	89.96	0.00	/workspace/coverage/default/0.sysrst_ctrl_stress_all.3725927739
97.09	0.05	99.07	0.06	95.96	0.08	100.00	0.23	96.79	0.00	98.34	0.00	99.52	0.00	89.96	0.00	/workspace/coverage/default/1.sysrst_ctrl_alert_test.1171932375
97.14	0.05	99.07	0.00	95.96	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	90.32	0.35	/workspace/coverage/default/0.sysrst_ctrl_combo_detect.2990071894
97.18	0.04	99.07	0.00	95.96	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	90.61	0.30	/workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2818562233
97.23	0.04	99.07	0.00	95.96	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	90.91	0.30	/workspace/coverage/default/26.sysrst_ctrl_combo_detect.2695598353
97.27	0.04	99.07	0.00	95.96	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	91.20	0.30	/workspace/coverage/default/46.sysrst_ctrl_stress_all.1926996983
97.31	0.04	99.07	0.00	95.96	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	91.50	0.30	/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3162891065
97.34	0.03	99.07	0.00	95.96	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	91.74	0.24	/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1518627533
97.37	0.03	99.09	0.02	95.96	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	91.91	0.18	/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.84013075
97.40	0.03	99.09	0.00	95.96	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	92.09	0.18	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1299057092
97.42	0.03	99.09	0.00	96.13	0.18	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	92.09	0.00	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2245532746
97.44	0.02	99.09	0.00	96.16	0.03	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	92.21	0.12	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2377303528
97.46	0.02	99.09	0.00	96.18	0.03	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	92.33	0.12	/workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2901551412
97.48	0.02	99.09	0.00	96.21	0.03	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	92.44	0.12	/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1362021282
97.50	0.02	99.09	0.00	96.21	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	92.56	0.12	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.442885944
97.52	0.02	99.09	0.00	96.21	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	92.68	0.12	/workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1535110281
97.53	0.02	99.09	0.00	96.21	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	92.80	0.12	/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1953612929
97.55	0.02	99.09	0.00	96.21	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	92.92	0.12	/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3820752753
97.57	0.02	99.09	0.00	96.21	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	93.03	0.12	/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3636122492
97.59	0.02	99.09	0.00	96.21	0.00	100.00	0.00	96.79	0.00	98.34	0.00	99.52	0.00	93.15	0.12	/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1704218500
97.60	0.02	99.10	0.02	96.21	0.00	100.00	0.00	96.79	0.00	98.37	0.04	99.52	0.00	93.21	0.06	/workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1200067588
97.62	0.02	99.12	0.02	96.21	0.00	100.00	0.00	96.79	0.00	98.41	0.04	99.52	0.00	93.27	0.06	/workspace/coverage/default/20.sysrst_ctrl_stress_all.3053774828
97.63	0.02	99.16	0.04	96.21	0.00	100.00	0.00	96.79	0.00	98.48	0.07	99.52	0.00	93.27	0.00	/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1771858283
97.65	0.01	99.16	0.00	96.31	0.10	100.00	0.00	96.79	0.00	98.48	0.00	99.52	0.00	93.27	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.4037470731
97.66	0.01	99.20	0.04	96.33	0.03	100.00	0.00	96.79	0.00	98.52	0.04	99.52	0.00	93.27	0.00	/workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1506268866
97.67	0.01	99.20	0.00	96.36	0.03	100.00	0.00	96.79	0.00	98.52	0.00	99.52	0.00	93.33	0.06	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1696646792
97.68	0.01	99.20	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.52	0.00	99.52	0.00	93.39	0.06	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1214785225
97.69	0.01	99.20	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.52	0.00	99.52	0.00	93.45	0.06	/workspace/coverage/default/15.sysrst_ctrl_combo_detect.1918543821
97.70	0.01	99.20	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.52	0.00	99.52	0.00	93.51	0.06	/workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3010623991
97.71	0.01	99.20	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.52	0.00	99.52	0.00	93.57	0.06	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1040268183
97.72	0.01	99.20	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.52	0.00	99.52	0.00	93.62	0.06	/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1408322357
97.73	0.01	99.20	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.52	0.00	99.52	0.00	93.68	0.06	/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2828509609
97.73	0.01	99.20	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.52	0.00	99.52	0.00	93.74	0.06	/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.4119631652
97.74	0.01	99.20	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.52	0.00	99.52	0.00	93.80	0.06	/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3256241305
97.75	0.01	99.20	0.00	96.36	0.00	100.00	0.00	96.79	0.00	98.52	0.00	99.52	0.00	93.86	0.06	/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.4044779960
97.76	0.01	99.22	0.02	96.36	0.00	100.00	0.00	96.79	0.00	98.56	0.04	99.52	0.00	93.86	0.00	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.711976168
97.77	0.01	99.23	0.02	96.36	0.00	100.00	0.00	96.79	0.00	98.60	0.04	99.52	0.00	93.86	0.00	/workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3679492587
97.77	0.01	99.25	0.02	96.36	0.00	100.00	0.00	96.79	0.00	98.63	0.04	99.52	0.00	93.86	0.00	/workspace/coverage/default/11.sysrst_ctrl_edge_detect.2636024225
97.78	0.01	99.27	0.02	96.36	0.00	100.00	0.00	96.79	0.00	98.67	0.04	99.52	0.00	93.86	0.00	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.2147608413
97.79	0.01	99.27	0.00	96.39	0.03	100.00	0.00	96.79	0.00	98.67	0.00	99.52	0.00	93.86	0.00	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1453682422

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1472609458
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2371222444
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1620540395
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1265707352
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2442092151
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3759899511
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.4115642481
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3251999444
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1550386765
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3490939523
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1589742469
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2328170206
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1351270094
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.939731106
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/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3683701076
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3124042348
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.4219549889
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.952427150
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2637796238

---

Total test records in report: 921

---

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

---

TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.4098045220			Aug 17 04:39:05 PM PDT 24	Aug 17 04:39:07 PM PDT 24	2632648639 ps
T5	/workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.123208001			Aug 17 04:40:00 PM PDT 24	Aug 17 04:40:03 PM PDT 24	3139072700 ps
T6	/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3373491087			Aug 17 04:40:38 PM PDT 24	Aug 17 04:40:40 PM PDT 24	4440270166 ps
T22	/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1142604432			Aug 17 04:40:47 PM PDT 24	Aug 17 04:40:55 PM PDT 24	5944638022 ps
T1	/workspace/coverage/default/40.sysrst_ctrl_combo_detect.2888536329			Aug 17 04:40:29 PM PDT 24	Aug 17 04:41:32 PM PDT 24	168311199580 ps
T2	/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1976069950			Aug 17 04:40:55 PM PDT 24	Aug 17 04:41:02 PM PDT 24	9456060312 ps
T14	/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1075670789			Aug 17 04:38:57 PM PDT 24	Aug 17 04:38:59 PM PDT 24	2488879041 ps
T15	/workspace/coverage/default/49.sysrst_ctrl_smoke.1297085393			Aug 17 04:40:54 PM PDT 24	Aug 17 04:40:55 PM PDT 24	2152459767 ps
T16	/workspace/coverage/default/25.sysrst_ctrl_pin_access_test.3509364780			Aug 17 04:39:56 PM PDT 24	Aug 17 04:40:02 PM PDT 24	2210335669 ps
T17	/workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3703627910			Aug 17 04:40:13 PM PDT 24	Aug 17 04:40:16 PM PDT 24	2622445944 ps
T18	/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.556404259			Aug 17 04:40:04 PM PDT 24	Aug 17 04:40:10 PM PDT 24	2076323828 ps
T19	/workspace/coverage/default/33.sysrst_ctrl_combo_detect.2381724688			Aug 17 04:40:13 PM PDT 24	Aug 17 04:46:36 PM PDT 24	151807985718 ps
T20	/workspace/coverage/default/45.sysrst_ctrl_smoke.2656041950			Aug 17 04:40:39 PM PDT 24	Aug 17 04:40:41 PM PDT 24	2138056069 ps
T21	/workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.922499619			Aug 17 04:38:46 PM PDT 24	Aug 17 04:38:54 PM PDT 24	2461120236 ps
T3	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2670026173			Aug 17 04:38:52 PM PDT 24	Aug 17 04:43:12 PM PDT 24	95077835910 ps
T7	/workspace/coverage/default/36.sysrst_ctrl_edge_detect.2621195053			Aug 17 04:40:19 PM PDT 24	Aug 17 04:40:26 PM PDT 24	3483500620 ps
T8	/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.105021517			Aug 17 04:40:52 PM PDT 24	Aug 17 04:44:04 PM PDT 24	69121819540 ps
T60	/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2530384873			Aug 17 04:39:11 PM PDT 24	Aug 17 04:39:14 PM PDT 24	2078999101 ps
T30	/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.152532886			Aug 17 04:39:06 PM PDT 24	Aug 17 04:39:22 PM PDT 24	25097978315 ps
T9	/workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1506268866			Aug 17 04:38:46 PM PDT 24	Aug 17 04:38:49 PM PDT 24	4291717131 ps
T28	/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3157476128			Aug 17 04:39:12 PM PDT 24	Aug 17 04:39:14 PM PDT 24	2523068908 ps
T26	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.63759340			Aug 17 04:38:31 PM PDT 24	Aug 17 04:39:46 PM PDT 24	30925556189 ps
T29	/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3846221696			Aug 17 04:39:04 PM PDT 24	Aug 17 04:39:13 PM PDT 24	3084061639 ps
T73	/workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.546858182			Aug 17 04:39:42 PM PDT 24	Aug 17 04:39:47 PM PDT 24	2618880519 ps
T10	/workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.621294833			Aug 17 04:40:14 PM PDT 24	Aug 17 04:40:17 PM PDT 24	7978989895 ps
T11	/workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.745392846			Aug 17 04:39:44 PM PDT 24	Aug 17 04:40:29 PM PDT 24	60498735298 ps
T51	/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2799106840			Aug 17 04:40:53 PM PDT 24	Aug 17 04:41:10 PM PDT 24	26361698526 ps
T129	/workspace/coverage/default/24.sysrst_ctrl_alert_test.3066614908			Aug 17 04:39:50 PM PDT 24	Aug 17 04:39:52 PM PDT 24	2041280473 ps
T12	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.2147608413			Aug 17 04:39:39 PM PDT 24	Aug 17 04:39:45 PM PDT 24	4320698389 ps
T130	/workspace/coverage/default/1.sysrst_ctrl_alert_test.1171932375			Aug 17 04:38:48 PM PDT 24	Aug 17 04:38:54 PM PDT 24	2009452024 ps
T74	/workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3682589226			Aug 17 04:39:38 PM PDT 24	Aug 17 04:39:45 PM PDT 24	2510889925 ps
T75	/workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.328934535			Aug 17 04:39:25 PM PDT 24	Aug 17 04:39:30 PM PDT 24	2615227579 ps
T62	/workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1579505940			Aug 17 04:39:41 PM PDT 24	Aug 17 04:39:47 PM PDT 24	4407240594 ps
T76	/workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2317642215			Aug 17 04:39:42 PM PDT 24	Aug 17 04:39:49 PM PDT 24	2610721093 ps
T13	/workspace/coverage/default/39.sysrst_ctrl_stress_all.3091994060			Aug 17 04:40:28 PM PDT 24	Aug 17 04:42:30 PM PDT 24	49782523257 ps
T77	/workspace/coverage/default/11.sysrst_ctrl_pin_override_test.3080032920			Aug 17 04:39:17 PM PDT 24	Aug 17 04:39:20 PM PDT 24	2523864590 ps
T181	/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1926885038			Aug 17 04:40:51 PM PDT 24	Aug 17 04:40:54 PM PDT 24	4346247137 ps
T27	/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.229746087			Aug 17 04:40:49 PM PDT 24	Aug 17 04:40:56 PM PDT 24	2458551874 ps
T35	/workspace/coverage/default/20.sysrst_ctrl_combo_detect.4150057825			Aug 17 04:39:39 PM PDT 24	Aug 17 04:41:01 PM PDT 24	125155376024 ps
T109	/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2690686664			Aug 17 04:40:46 PM PDT 24	Aug 17 04:40:56 PM PDT 24	3585865441 ps
T34	/workspace/coverage/default/14.sysrst_ctrl_stress_all.3666646965			Aug 17 04:39:28 PM PDT 24	Aug 17 04:39:36 PM PDT 24	11568617025 ps
T110	/workspace/coverage/default/41.sysrst_ctrl_stress_all.688537423			Aug 17 04:40:32 PM PDT 24	Aug 17 04:40:35 PM PDT 24	8968163436 ps
T52	/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2527938080			Aug 17 04:40:44 PM PDT 24	Aug 17 04:42:46 PM PDT 24	182879478299 ps
T111	/workspace/coverage/default/30.sysrst_ctrl_alert_test.2275939575			Aug 17 04:40:06 PM PDT 24	Aug 17 04:40:08 PM PDT 24	2061445779 ps
T112	/workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1834554671			Aug 17 04:40:22 PM PDT 24	Aug 17 04:40:30 PM PDT 24	2611257275 ps
T67	/workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.1685640317			Aug 17 04:40:14 PM PDT 24	Aug 17 04:40:16 PM PDT 24	2494961211 ps
T113	/workspace/coverage/default/12.sysrst_ctrl_pin_access_test.3778506337			Aug 17 04:39:19 PM PDT 24	Aug 17 04:39:22 PM PDT 24	2193440404 ps
T114	/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2242152581			Aug 17 04:40:50 PM PDT 24	Aug 17 04:40:52 PM PDT 24	2548920549 ps
T53	/workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3099287275			Aug 17 04:39:26 PM PDT 24	Aug 17 04:39:35 PM PDT 24	3495743492 ps
T294	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1880326193			Aug 17 04:39:31 PM PDT 24	Aug 17 04:39:40 PM PDT 24	3090513958 ps
T54	/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.167517608			Aug 17 04:41:03 PM PDT 24	Aug 17 04:41:48 PM PDT 24	107871340804 ps
T36	/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1219760295			Aug 17 04:40:51 PM PDT 24	Aug 17 04:41:01 PM PDT 24	41776483610 ps
T41	/workspace/coverage/default/34.sysrst_ctrl_stress_all.3047723607			Aug 17 04:40:12 PM PDT 24	Aug 17 04:40:15 PM PDT 24	11036173205 ps
T37	/workspace/coverage/default/5.sysrst_ctrl_combo_detect.3750325814			Aug 17 04:38:52 PM PDT 24	Aug 17 04:42:18 PM PDT 24	157472755550 ps
T55	/workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1294483497			Aug 17 04:39:55 PM PDT 24	Aug 17 04:40:05 PM PDT 24	3461969661 ps
T78	/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3636122492			Aug 17 04:40:50 PM PDT 24	Aug 17 04:43:10 PM PDT 24	114754897928 ps
T133	/workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4274717714			Aug 17 04:38:33 PM PDT 24	Aug 17 04:38:45 PM PDT 24	3938707018 ps
T79	/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.753582024			Aug 17 04:40:52 PM PDT 24	Aug 17 04:41:26 PM PDT 24	80136929936 ps
T63	/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.1464608777			Aug 17 04:40:28 PM PDT 24	Aug 17 04:40:30 PM PDT 24	6026051094 ps
T64	/workspace/coverage/default/21.sysrst_ctrl_stress_all.3410207786			Aug 17 04:39:40 PM PDT 24	Aug 17 04:40:14 PM PDT 24	97973276885 ps
T134	/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.477519799			Aug 17 04:41:02 PM PDT 24	Aug 17 04:42:42 PM PDT 24	94832505871 ps
T56	/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3818137527			Aug 17 04:40:29 PM PDT 24	Aug 17 04:40:33 PM PDT 24	3089158663 ps
T255	/workspace/coverage/default/48.sysrst_ctrl_alert_test.2711451704			Aug 17 04:40:43 PM PDT 24	Aug 17 04:40:47 PM PDT 24	2018198172 ps
T256	/workspace/coverage/default/34.sysrst_ctrl_smoke.1710878571			Aug 17 04:40:11 PM PDT 24	Aug 17 04:40:16 PM PDT 24	2116402171 ps
T257	/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3672201781			Aug 17 04:38:56 PM PDT 24	Aug 17 04:39:04 PM PDT 24	3157786839 ps
T68	/workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.3304743400			Aug 17 04:40:03 PM PDT 24	Aug 17 04:40:07 PM PDT 24	2471055137 ps
T258	/workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2422859512			Aug 17 04:39:24 PM PDT 24	Aug 17 04:39:32 PM PDT 24	2614547397 ps
T65	/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3353597056			Aug 17 04:39:05 PM PDT 24	Aug 17 04:39:12 PM PDT 24	4409181849 ps
T43	/workspace/coverage/default/4.sysrst_ctrl_edge_detect.3502006171			Aug 17 04:38:53 PM PDT 24	Aug 17 04:38:55 PM PDT 24	2910659188 ps
T189	/workspace/coverage/default/5.sysrst_ctrl_smoke.566336670			Aug 17 04:38:56 PM PDT 24	Aug 17 04:39:02 PM PDT 24	2110386957 ps
T190	/workspace/coverage/default/36.sysrst_ctrl_alert_test.3624111958			Aug 17 04:40:21 PM PDT 24	Aug 17 04:40:23 PM PDT 24	2046045935 ps
T191	/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1265174306			Aug 17 04:40:47 PM PDT 24	Aug 17 04:40:49 PM PDT 24	2622824381 ps
T69	/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2723988727			Aug 17 04:40:28 PM PDT 24	Aug 17 04:40:36 PM PDT 24	2472505017 ps
T66	/workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.692500387			Aug 17 04:40:04 PM PDT 24	Aug 17 04:40:11 PM PDT 24	4418022257 ps
T96	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1396339129			Aug 17 04:38:54 PM PDT 24	Aug 17 04:40:07 PM PDT 24	26330735253 ps
T70	/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2654860845			Aug 17 04:39:04 PM PDT 24	Aug 17 04:39:12 PM PDT 24	2445627595 ps
T80	/workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3137820023			Aug 17 04:39:19 PM PDT 24	Aug 17 04:39:21 PM PDT 24	9345582645 ps
T97	/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3929289967			Aug 17 04:40:54 PM PDT 24	Aug 17 04:42:00 PM PDT 24	29079367515 ps
T135	/workspace/coverage/default/38.sysrst_ctrl_alert_test.3607723723			Aug 17 04:40:28 PM PDT 24	Aug 17 04:40:34 PM PDT 24	2009446062 ps
T136	/workspace/coverage/default/37.sysrst_ctrl_smoke.1254752313			Aug 17 04:40:21 PM PDT 24	Aug 17 04:40:23 PM PDT 24	2138247721 ps
T57	/workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1526856433			Aug 17 04:39:19 PM PDT 24	Aug 17 04:42:16 PM PDT 24	200726124547 ps
T137	/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.84013075			Aug 17 04:39:53 PM PDT 24	Aug 17 04:43:08 PM PDT 24	71503780502 ps
T38	/workspace/coverage/default/38.sysrst_ctrl_stress_all.4087988007			Aug 17 04:40:26 PM PDT 24	Aug 17 04:40:32 PM PDT 24	12871094385 ps
T44	/workspace/coverage/default/32.sysrst_ctrl_stress_all.180060252			Aug 17 04:40:14 PM PDT 24	Aug 17 04:40:33 PM PDT 24	7557566864 ps
T138	/workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1535110281			Aug 17 04:38:39 PM PDT 24	Aug 17 04:38:41 PM PDT 24	2635680893 ps
T139	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3971869674			Aug 17 04:38:36 PM PDT 24	Aug 17 04:38:40 PM PDT 24	2427814174 ps
T194	/workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2196789276			Aug 17 04:40:18 PM PDT 24	Aug 17 04:40:28 PM PDT 24	3278965559 ps
T195	/workspace/coverage/default/28.sysrst_ctrl_pin_override_test.4014796241			Aug 17 04:40:04 PM PDT 24	Aug 17 04:40:11 PM PDT 24	2511745726 ps
T196	/workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.2070077491			Aug 17 04:40:13 PM PDT 24	Aug 17 04:40:15 PM PDT 24	2632850396 ps
T98	/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3711332754			Aug 17 04:40:39 PM PDT 24	Aug 17 04:41:01 PM PDT 24	26348149006 ps
T197	/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3051841151			Aug 17 04:40:49 PM PDT 24	Aug 17 04:40:56 PM PDT 24	10521224812 ps
T198	/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1237745715			Aug 17 04:38:53 PM PDT 24	Aug 17 04:38:56 PM PDT 24	2537628401 ps
T81	/workspace/coverage/default/33.sysrst_ctrl_stress_all.944060176			Aug 17 04:40:17 PM PDT 24	Aug 17 04:40:31 PM PDT 24	7349783556 ps
T48	/workspace/coverage/default/20.sysrst_ctrl_edge_detect.1995167842			Aug 17 04:39:43 PM PDT 24	Aug 17 04:39:45 PM PDT 24	2970352672 ps
T310	/workspace/coverage/default/31.sysrst_ctrl_pin_override_test.1755417925			Aug 17 04:40:07 PM PDT 24	Aug 17 04:40:09 PM PDT 24	2554941481 ps
T335	/workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1404266892			Aug 17 04:39:56 PM PDT 24	Aug 17 04:40:00 PM PDT 24	2517331663 ps
T272	/workspace/coverage/default/4.sysrst_ctrl_sec_cm.713887696			Aug 17 04:38:52 PM PDT 24	Aug 17 04:39:53 PM PDT 24	22012592787 ps
T297	/workspace/coverage/default/10.sysrst_ctrl_smoke.1199860274			Aug 17 04:39:09 PM PDT 24	Aug 17 04:39:10 PM PDT 24	2139859413 ps
T58	/workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3778472303			Aug 17 04:40:10 PM PDT 24	Aug 17 04:40:19 PM PDT 24	3435677308 ps
T99	/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1306194939			Aug 17 04:40:37 PM PDT 24	Aug 17 04:40:49 PM PDT 24	40848944288 ps
T298	/workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.92564894			Aug 17 04:40:14 PM PDT 24	Aug 17 04:40:27 PM PDT 24	4879229772 ps
T82	/workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3948045193			Aug 17 04:40:04 PM PDT 24	Aug 17 04:40:07 PM PDT 24	11699450576 ps
T71	/workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1079063140			Aug 17 04:39:20 PM PDT 24	Aug 17 04:39:22 PM PDT 24	2493140576 ps
T46	/workspace/coverage/default/39.sysrst_ctrl_edge_detect.1157395163			Aug 17 04:40:27 PM PDT 24	Aug 17 04:40:43 PM PDT 24	5996536568 ps
T243	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1040268183			Aug 17 04:40:38 PM PDT 24	Aug 17 04:41:21 PM PDT 24	69570816293 ps
T100	/workspace/coverage/default/29.sysrst_ctrl_combo_detect.3223734273			Aug 17 04:40:06 PM PDT 24	Aug 17 04:40:49 PM PDT 24	65741163977 ps
T414	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1543116192			Aug 17 04:38:51 PM PDT 24	Aug 17 04:38:54 PM PDT 24	2334069327 ps
T124	/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3849048034			Aug 17 04:40:28 PM PDT 24	Aug 17 04:40:53 PM PDT 24	619067074799 ps
T415	/workspace/coverage/default/31.sysrst_ctrl_alert_test.1241291694			Aug 17 04:40:05 PM PDT 24	Aug 17 04:40:06 PM PDT 24	2034398695 ps
T59	/workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1605640630			Aug 17 04:39:30 PM PDT 24	Aug 17 04:39:40 PM PDT 24	3466919593 ps
T416	/workspace/coverage/default/1.sysrst_ctrl_smoke.1427188353			Aug 17 04:38:41 PM PDT 24	Aug 17 04:38:43 PM PDT 24	2141164394 ps
T312	/workspace/coverage/default/29.sysrst_ctrl_stress_all.1505169580			Aug 17 04:40:04 PM PDT 24	Aug 17 04:40:13 PM PDT 24	7180579096 ps
T264	/workspace/coverage/default/15.sysrst_ctrl_combo_detect.1918543821			Aug 17 04:39:23 PM PDT 24	Aug 17 04:40:23 PM PDT 24	109351151511 ps
T101	/workspace/coverage/default/34.sysrst_ctrl_combo_detect.3418421665			Aug 17 04:40:13 PM PDT 24	Aug 17 04:43:13 PM PDT 24	150959968798 ps
T265	/workspace/coverage/default/16.sysrst_ctrl_combo_detect.2302270587			Aug 17 04:39:32 PM PDT 24	Aug 17 04:40:15 PM PDT 24	101980388110 ps
T72	/workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.4001902692			Aug 17 04:39:17 PM PDT 24	Aug 17 04:39:18 PM PDT 24	2509488747 ps
T299	/workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.306610682			Aug 17 04:38:58 PM PDT 24	Aug 17 04:39:10 PM PDT 24	4345784475 ps
T417	/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2532206942			Aug 17 04:40:46 PM PDT 24	Aug 17 04:40:53 PM PDT 24	2612415377 ps
T418	/workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.4178275435			Aug 17 04:38:49 PM PDT 24	Aug 17 04:38:55 PM PDT 24	2474818696 ps
T125	/workspace/coverage/default/17.sysrst_ctrl_stress_all.1361906555			Aug 17 04:39:32 PM PDT 24	Aug 17 04:40:05 PM PDT 24	15305462934 ps
T102	/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3639509147			Aug 17 04:40:54 PM PDT 24	Aug 17 04:41:45 PM PDT 24	72575233923 ps
T39	/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3693110784			Aug 17 04:40:40 PM PDT 24	Aug 17 04:40:42 PM PDT 24	3937340456 ps
T232	/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2540875922			Aug 17 04:38:56 PM PDT 24	Aug 17 04:39:00 PM PDT 24	10297357230 ps
T233	/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3683701076			Aug 17 04:40:52 PM PDT 24	Aug 17 04:49:05 PM PDT 24	209223434778 ps
T234	/workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.1685287684			Aug 17 04:39:31 PM PDT 24	Aug 17 04:39:35 PM PDT 24	2480212189 ps
T235	/workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.4026773895			Aug 17 04:40:00 PM PDT 24	Aug 17 05:14:13 PM PDT 24	902247687747 ps
T236	/workspace/coverage/default/14.sysrst_ctrl_pin_override_test.2034814023			Aug 17 04:39:27 PM PDT 24	Aug 17 04:39:30 PM PDT 24	2537801372 ps
T237	/workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.638162676			Aug 17 04:40:13 PM PDT 24	Aug 17 04:40:17 PM PDT 24	2616685969 ps
T238	/workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.451435059			Aug 17 04:39:47 PM PDT 24	Aug 17 04:39:53 PM PDT 24	2447722524 ps
T239	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3935187963			Aug 17 04:39:24 PM PDT 24	Aug 17 04:39:35 PM PDT 24	4527468017 ps
T240	/workspace/coverage/default/35.sysrst_ctrl_smoke.1484516632			Aug 17 04:40:14 PM PDT 24	Aug 17 04:40:21 PM PDT 24	2110044642 ps
T92	/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.624892749			Aug 17 04:40:29 PM PDT 24	Aug 17 04:40:32 PM PDT 24	5608452427 ps
T84	/workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2267815452			Aug 17 04:39:50 PM PDT 24	Aug 17 04:39:53 PM PDT 24	3061458256 ps
T103	/workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1688368526			Aug 17 04:40:01 PM PDT 24	Aug 17 04:41:12 PM PDT 24	54153591487 ps
T115	/workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1887479630			Aug 17 04:40:21 PM PDT 24	Aug 17 04:40:29 PM PDT 24	2910335719 ps
T116	/workspace/coverage/default/29.sysrst_ctrl_smoke.3158410335			Aug 17 04:40:06 PM PDT 24	Aug 17 04:40:12 PM PDT 24	2114546896 ps
T117	/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.438103316			Aug 17 04:40:34 PM PDT 24	Aug 17 04:40:40 PM PDT 24	2069626768 ps
T118	/workspace/coverage/default/35.sysrst_ctrl_pin_access_test.1606371912			Aug 17 04:40:11 PM PDT 24	Aug 17 04:40:17 PM PDT 24	2147750392 ps
T119	/workspace/coverage/default/13.sysrst_ctrl_smoke.485978709			Aug 17 04:39:17 PM PDT 24	Aug 17 04:39:19 PM PDT 24	2134601552 ps
T120	/workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.758095968			Aug 17 04:39:23 PM PDT 24	Aug 17 04:39:38 PM PDT 24	38316734885 ps
T121	/workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3050103716			Aug 17 04:39:57 PM PDT 24	Aug 17 04:40:02 PM PDT 24	5452997354 ps
T122	/workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2539453870			Aug 17 04:39:57 PM PDT 24	Aug 17 04:40:04 PM PDT 24	4254758607 ps
T419	/workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.1769569102			Aug 17 04:39:51 PM PDT 24	Aug 17 04:39:54 PM PDT 24	2616266453 ps
T420	/workspace/coverage/default/29.sysrst_ctrl_pin_access_test.1221409420			Aug 17 04:40:03 PM PDT 24	Aug 17 04:40:05 PM PDT 24	2041728267 ps
T123	/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2527892117			Aug 17 04:39:31 PM PDT 24	Aug 17 04:39:34 PM PDT 24	3459471780 ps
T42	/workspace/coverage/default/11.sysrst_ctrl_edge_detect.2636024225			Aug 17 04:39:16 PM PDT 24	Aug 17 04:39:20 PM PDT 24	5433262878 ps
T185	/workspace/coverage/default/21.sysrst_ctrl_smoke.2260050909			Aug 17 04:39:40 PM PDT 24	Aug 17 04:39:43 PM PDT 24	2114094414 ps
T47	/workspace/coverage/default/22.sysrst_ctrl_edge_detect.153344796			Aug 17 04:39:51 PM PDT 24	Aug 17 04:39:53 PM PDT 24	2791116675 ps
T159	/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.4130783079			Aug 17 04:40:36 PM PDT 24	Aug 17 04:40:44 PM PDT 24	2508965388 ps
T160	/workspace/coverage/default/5.sysrst_ctrl_alert_test.988801642			Aug 17 04:38:56 PM PDT 24	Aug 17 04:38:59 PM PDT 24	2019439592 ps
T161	/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3162891065			Aug 17 04:39:11 PM PDT 24	Aug 17 04:39:44 PM PDT 24	50589620708 ps
T162	/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.931956138			Aug 17 04:40:48 PM PDT 24	Aug 17 04:40:57 PM PDT 24	3177575213 ps
T163	/workspace/coverage/default/12.sysrst_ctrl_smoke.2918839954			Aug 17 04:39:17 PM PDT 24	Aug 17 04:39:23 PM PDT 24	2114532710 ps
T131	/workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2533396874			Aug 17 04:40:12 PM PDT 24	Aug 17 04:41:17 PM PDT 24	106674774567 ps
T164	/workspace/coverage/default/21.sysrst_ctrl_pin_override_test.2509777690			Aug 17 04:39:40 PM PDT 24	Aug 17 04:39:44 PM PDT 24	2517597355 ps
T40	/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3387300948			Aug 17 04:38:52 PM PDT 24	Aug 17 04:38:54 PM PDT 24	4326786038 ps
T165	/workspace/coverage/default/23.sysrst_ctrl_alert_test.713877612			Aug 17 04:39:53 PM PDT 24	Aug 17 04:39:55 PM PDT 24	2035690176 ps
T412	/workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2611402475			Aug 17 04:40:22 PM PDT 24	Aug 17 04:40:24 PM PDT 24	2563745209 ps
T311	/workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2818562233			Aug 17 04:39:48 PM PDT 24	Aug 17 04:39:52 PM PDT 24	2520201938 ps
T421	/workspace/coverage/default/27.sysrst_ctrl_smoke.2204841341			Aug 17 04:39:55 PM PDT 24	Aug 17 04:40:01 PM PDT 24	2110052883 ps
T422	/workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.130680578			Aug 17 04:40:06 PM PDT 24	Aug 17 04:40:13 PM PDT 24	2607998595 ps
T246	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.725189992			Aug 17 04:39:39 PM PDT 24	Aug 17 04:40:12 PM PDT 24	25832623243 ps
T366	/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3724350662			Aug 17 04:40:52 PM PDT 24	Aug 17 04:41:24 PM PDT 24	40984220182 ps
T361	/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1400207137			Aug 17 04:40:28 PM PDT 24	Aug 17 04:41:32 PM PDT 24	109217236323 ps
T247	/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2603534599			Aug 17 04:40:51 PM PDT 24	Aug 17 04:41:08 PM PDT 24	27112760046 ps
T242	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2473306685			Aug 17 04:40:16 PM PDT 24	Aug 17 04:43:22 PM PDT 24	72834127816 ps
T224	/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1216942508			Aug 17 04:40:37 PM PDT 24	Aug 17 04:40:51 PM PDT 24	19584152910 ps
T318	/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1226601101			Aug 17 04:40:49 PM PDT 24	Aug 17 04:40:58 PM PDT 24	2458434416 ps
T319	/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.2763572182			Aug 17 04:40:06 PM PDT 24	Aug 17 04:40:10 PM PDT 24	2616922637 ps
T320	/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1865905108			Aug 17 04:40:27 PM PDT 24	Aug 17 04:40:35 PM PDT 24	2452067473 ps
T321	/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.60052547			Aug 17 04:40:34 PM PDT 24	Aug 17 04:40:37 PM PDT 24	3311948547 ps
T322	/workspace/coverage/default/31.sysrst_ctrl_smoke.2400542403			Aug 17 04:40:06 PM PDT 24	Aug 17 04:40:10 PM PDT 24	2120543767 ps
T323	/workspace/coverage/default/42.sysrst_ctrl_smoke.2576680388			Aug 17 04:40:29 PM PDT 24	Aug 17 04:40:31 PM PDT 24	2127379143 ps
T324	/workspace/coverage/default/36.sysrst_ctrl_pin_access_test.3198527239			Aug 17 04:40:13 PM PDT 24	Aug 17 04:40:19 PM PDT 24	2088418483 ps
T325	/workspace/coverage/default/24.sysrst_ctrl_pin_access_test.2476072082			Aug 17 04:39:50 PM PDT 24	Aug 17 04:39:57 PM PDT 24	2130282529 ps
T326	/workspace/coverage/default/32.sysrst_ctrl_pin_override_test.1569691060			Aug 17 04:40:06 PM PDT 24	Aug 17 04:40:09 PM PDT 24	2527085994 ps
T423	/workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3231837254			Aug 17 04:38:56 PM PDT 24	Aug 17 04:38:59 PM PDT 24	3336363067 ps
T424	/workspace/coverage/default/3.sysrst_ctrl_pin_access_test.1238942953			Aug 17 04:38:46 PM PDT 24	Aug 17 04:38:49 PM PDT 24	2114185821 ps
T413	/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3539170114			Aug 17 04:40:27 PM PDT 24	Aug 17 04:40:31 PM PDT 24	2519510958 ps
T425	/workspace/coverage/default/15.sysrst_ctrl_smoke.2714716127			Aug 17 04:39:24 PM PDT 24	Aug 17 04:39:30 PM PDT 24	2114320658 ps
T358	/workspace/coverage/default/25.sysrst_ctrl_combo_detect.4102920999			Aug 17 04:39:59 PM PDT 24	Aug 17 04:40:29 PM PDT 24	56082785569 ps
T426	/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2562701058			Aug 17 04:38:56 PM PDT 24	Aug 17 04:38:59 PM PDT 24	2637311392 ps
T427	/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.726650506			Aug 17 04:39:30 PM PDT 24	Aug 17 04:39:59 PM PDT 24	42362758230 ps
T45	/workspace/coverage/default/1.sysrst_ctrl_edge_detect.3220261827			Aug 17 04:38:39 PM PDT 24	Aug 17 04:38:46 PM PDT 24	4119106889 ps
T428	/workspace/coverage/default/4.sysrst_ctrl_smoke.80302143			Aug 17 04:38:56 PM PDT 24	Aug 17 04:39:00 PM PDT 24	2119643717 ps
T429	/workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3946843698			Aug 17 04:40:12 PM PDT 24	Aug 17 04:40:23 PM PDT 24	3875964830 ps
T126	/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.4271101402			Aug 17 04:39:11 PM PDT 24	Aug 17 04:39:13 PM PDT 24	9368549582 ps
T430	/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1219261499			Aug 17 04:39:09 PM PDT 24	Aug 17 04:39:14 PM PDT 24	2469779962 ps
T249	/workspace/coverage/default/8.sysrst_ctrl_combo_detect.1534724335			Aug 17 04:39:10 PM PDT 24	Aug 17 04:40:21 PM PDT 24	124773356768 ps
T431	/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.251275174			Aug 17 04:40:43 PM PDT 24	Aug 17 04:43:49 PM PDT 24	72566995596 ps
T432	/workspace/coverage/default/33.sysrst_ctrl_pin_access_test.856337533			Aug 17 04:40:12 PM PDT 24	Aug 17 04:40:15 PM PDT 24	2138562544 ps
T433	/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.976669349			Aug 17 04:40:49 PM PDT 24	Aug 17 04:40:57 PM PDT 24	3058320910 ps
T434	/workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.152734408			Aug 17 04:40:03 PM PDT 24	Aug 17 04:40:06 PM PDT 24	2619367160 ps
T300	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3722278596			Aug 17 04:39:07 PM PDT 24	Aug 17 04:39:25 PM PDT 24	7385885618 ps
T329	/workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2559472908			Aug 17 04:40:12 PM PDT 24	Aug 17 04:40:15 PM PDT 24	2500965356 ps
T248	/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1953612929			Aug 17 04:40:37 PM PDT 24	Aug 17 04:41:59 PM PDT 24	182153982212 ps
T330	/workspace/coverage/default/11.sysrst_ctrl_smoke.1339476332			Aug 17 04:39:19 PM PDT 24	Aug 17 04:39:21 PM PDT 24	2127539336 ps
T87	/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2637796238			Aug 17 04:40:58 PM PDT 24	Aug 17 04:45:40 PM PDT 24	116269501043 ps
T331	/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.4117032613			Aug 17 04:40:51 PM PDT 24	Aug 17 04:41:13 PM PDT 24	35534616039 ps
T332	/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2180927563			Aug 17 04:40:52 PM PDT 24	Aug 17 04:43:22 PM PDT 24	75052056690 ps
T333	/workspace/coverage/default/23.sysrst_ctrl_pin_override_test.602010343			Aug 17 04:39:51 PM PDT 24	Aug 17 04:39:53 PM PDT 24	2530074305 ps
T127	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1991637736			Aug 17 04:39:56 PM PDT 24	Aug 17 04:40:11 PM PDT 24	29415169764 ps
T334	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.2267258661			Aug 17 04:39:23 PM PDT 24	Aug 17 04:40:20 PM PDT 24	148489847819 ps
T435	/workspace/coverage/default/7.sysrst_ctrl_alert_test.1795373745			Aug 17 04:39:15 PM PDT 24	Aug 17 04:39:21 PM PDT 24	2011703789 ps
T49	/workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.4292611265			Aug 17 04:39:25 PM PDT 24	Aug 17 04:39:37 PM PDT 24	27078131126 ps
T397	/workspace/coverage/default/28.sysrst_ctrl_stress_all.1656300836			Aug 17 04:40:04 PM PDT 24	Aug 17 04:40:16 PM PDT 24	13477979848 ps
T301	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.719218739			Aug 17 04:39:10 PM PDT 24	Aug 17 04:39:24 PM PDT 24	4853154249 ps
T389	/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1731967403			Aug 17 04:41:01 PM PDT 24	Aug 17 04:45:06 PM PDT 24	94991597032 ps
T308	/workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.2143078506			Aug 17 04:40:04 PM PDT 24	Aug 17 04:40:08 PM PDT 24	2470798582 ps
T266	/workspace/coverage/default/24.sysrst_ctrl_stress_all.3447946635			Aug 17 04:39:48 PM PDT 24	Aug 17 04:40:53 PM PDT 24	97313629783 ps
T396	/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2909203823			Aug 17 04:40:21 PM PDT 24	Aug 17 04:40:34 PM PDT 24	18168947273 ps
T436	/workspace/coverage/default/15.sysrst_ctrl_alert_test.2942169580			Aug 17 04:39:26 PM PDT 24	Aug 17 04:39:32 PM PDT 24	2010540113 ps
T88	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1453682422			Aug 17 04:40:19 PM PDT 24	Aug 17 04:42:37 PM PDT 24	209777031399 ps
T50	/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3539639940			Aug 17 04:40:45 PM PDT 24	Aug 17 04:40:46 PM PDT 24	3239059351 ps
T302	/workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3521332630			Aug 17 04:39:56 PM PDT 24	Aug 17 04:40:06 PM PDT 24	3620081846 ps
T307	/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1991917095			Aug 17 04:39:04 PM PDT 24	Aug 17 04:39:11 PM PDT 24	2492690908 ps
T437	/workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2802353492			Aug 17 04:39:19 PM PDT 24	Aug 17 04:39:22 PM PDT 24	2472660550 ps
T438	/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1693807968			Aug 17 04:39:04 PM PDT 24	Aug 17 04:39:07 PM PDT 24	3663238525 ps
T327	/workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1763652002			Aug 17 04:38:56 PM PDT 24	Aug 17 04:39:11 PM PDT 24	4914633086 ps
T439	/workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.4079273866			Aug 17 04:40:21 PM PDT 24	Aug 17 04:40:28 PM PDT 24	7768616518 ps
T104	/workspace/coverage/default/10.sysrst_ctrl_stress_all.867985868			Aug 17 04:39:18 PM PDT 24	Aug 17 04:45:23 PM PDT 24	140036166101 ps
T309	/workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1081725448			Aug 17 04:39:09 PM PDT 24	Aug 17 04:39:11 PM PDT 24	2497814515 ps
T440	/workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3551134596			Aug 17 04:39:23 PM PDT 24	Aug 17 04:39:30 PM PDT 24	2470925011 ps
T168	/workspace/coverage/default/0.sysrst_ctrl_stress_all.3725927739			Aug 17 04:38:38 PM PDT 24	Aug 17 04:38:43 PM PDT 24	11155654084 ps
T441	/workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.648642491			Aug 17 04:39:16 PM PDT 24	Aug 17 04:39:26 PM PDT 24	3702220569 ps
T105	/workspace/coverage/default/18.sysrst_ctrl_combo_detect.1640626120			Aug 17 04:39:30 PM PDT 24	Aug 17 04:43:52 PM PDT 24	97150483924 ps
T151	/workspace/coverage/default/9.sysrst_ctrl_edge_detect.206174811			Aug 17 04:39:13 PM PDT 24	Aug 17 04:39:16 PM PDT 24	6506110476 ps
T442	/workspace/coverage/default/19.sysrst_ctrl_stress_all.1443552761			Aug 17 04:39:47 PM PDT 24	Aug 17 04:40:00 PM PDT 24	9094472796 ps
T443	/workspace/coverage/default/37.sysrst_ctrl_pin_access_test.821027596			Aug 17 04:40:20 PM PDT 24	Aug 17 04:40:23 PM PDT 24	2099868508 ps
T303	/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1585637252			Aug 17 04:40:19 PM PDT 24	Aug 17 04:40:29 PM PDT 24	3616082405 ps
T444	/workspace/coverage/default/22.sysrst_ctrl_pin_override_test.3933788960			Aug 17 04:39:49 PM PDT 24	Aug 17 04:39:52 PM PDT 24	2550676749 ps
T259	/workspace/coverage/default/2.sysrst_ctrl_stress_all.1551098784			Aug 17 04:38:47 PM PDT 24	Aug 17 04:39:03 PM PDT 24	79404848017 ps
T360	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.3695834268			Aug 17 04:39:49 PM PDT 24	Aug 17 04:41:22 PM PDT 24	115072399466 ps
T200	/workspace/coverage/default/31.sysrst_ctrl_stress_all.3416525985			Aug 17 04:40:07 PM PDT 24	Aug 17 04:45:15 PM PDT 24	113510192646 ps
T170	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.539078942			Aug 17 04:39:34 PM PDT 24	Aug 17 04:39:36 PM PDT 24	2537144313 ps
T89	/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.4119631652			Aug 17 04:40:50 PM PDT 24	Aug 17 04:47:23 PM PDT 24	147094450858 ps
T304	/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1985277876			Aug 17 04:40:40 PM PDT 24	Aug 17 04:40:45 PM PDT 24	3044015669 ps
T445	/workspace/coverage/default/26.sysrst_ctrl_stress_all.2760740691			Aug 17 04:40:01 PM PDT 24	Aug 17 04:40:16 PM PDT 24	11523901046 ps
T446	/workspace/coverage/default/45.sysrst_ctrl_alert_test.991156524			Aug 17 04:40:36 PM PDT 24	Aug 17 04:40:41 PM PDT 24	2016004413 ps
T447	/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1120107053			Aug 17 04:38:53 PM PDT 24	Aug 17 04:38:55 PM PDT 24	2160594239 ps
T128	/workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1200067588			Aug 17 04:39:19 PM PDT 24	Aug 17 04:40:55 PM PDT 24	1279609775681 ps
T448	/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1961574860			Aug 17 04:40:36 PM PDT 24	Aug 17 04:40:38 PM PDT 24	2532402698 ps
T153	/workspace/coverage/default/31.sysrst_ctrl_edge_detect.2428432551			Aug 17 04:40:05 PM PDT 24	Aug 17 04:40:10 PM PDT 24	2956165824 ps
T449	/workspace/coverage/default/35.sysrst_ctrl_stress_all.452671371			Aug 17 04:40:12 PM PDT 24	Aug 17 04:40:14 PM PDT 24	9513761213 ps
T450	/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3124042348			Aug 17 04:41:02 PM PDT 24	Aug 17 04:41:18 PM PDT 24	23101172130 ps
T385	/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3632893569			Aug 17 04:40:51 PM PDT 24	Aug 17 04:45:58 PM PDT 24	117113410547 ps
T451	/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2824233663			Aug 17 04:40:28 PM PDT 24	Aug 17 04:40:36 PM PDT 24	10502049777 ps
T186	/workspace/coverage/default/27.sysrst_ctrl_edge_detect.686898101			Aug 17 04:39:55 PM PDT 24	Aug 17 04:40:00 PM PDT 24	4070928614 ps
T452	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2116750994			Aug 17 04:40:13 PM PDT 24	Aug 17 04:40:21 PM PDT 24	2512737819 ps
T453	/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3674674521			Aug 17 04:40:37 PM PDT 24	Aug 17 04:40:41 PM PDT 24	2156605068 ps