Design Hierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb 98.44 99.27 96.41 100.00 96.79 98.67 99.52
dut 98.44 99.27 96.41 100.00 96.79 98.67 99.52
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
sysrst_ctrl_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_prim_flop_2sync_input 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_reg 99.07 99.38 97.02 100.00 98.94 100.00
subtree...
u_sysrst_ctrl_autoblock 98.89 100.00 94.44 100.00 100.00 100.00
u_sysrst_ctrl_detect 98.10 100.00 90.48 100.00 100.00 100.00
u_sysrst_ctrl_combo 99.12 100.00 97.61 100.00 98.00 100.00
gen_combo_trigger[0].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
gen_combo_trigger[1].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect_pre 99.05 100.00 100.00 100.00 95.24 100.00
gen_combo_trigger[2].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect_pre 99.05 100.00 100.00 100.00 95.24 100.00
gen_combo_trigger[3].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect_pre 99.05 100.00 100.00 100.00 95.24 100.00
u_sysrst_ctrl_intr 96.25 100.00 85.00 100.00 100.00
u_match_sync 87.50 100.00 50.00 100.00 100.00
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sysrst_ctrl_intr_o 100.00 100.00 100.00 100.00 100.00
u_sysrst_ctrl_keyintr 94.93 97.68 88.78 94.05 96.43 97.70
gen_keyfsm[0].u_sysrst_ctrl_detect_h2l 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[0].u_sysrst_ctrl_detect_l2h 89.17 93.48 85.71 83.33 90.00 93.33
gen_keyfsm[1].u_sysrst_ctrl_detect_h2l 90.69 95.65 85.71 83.33 95.00 93.75
gen_keyfsm[1].u_sysrst_ctrl_detect_l2h 90.61 95.65 85.71 83.33 95.00 93.33
gen_keyfsm[2].u_sysrst_ctrl_detect_h2l 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[2].u_sysrst_ctrl_detect_l2h 96.66 97.83 90.48 100.00 95.00 100.00
gen_keyfsm[3].u_sysrst_ctrl_detect_h2l 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[3].u_sysrst_ctrl_detect_l2h 90.61 95.65 85.71 83.33 95.00 93.33
gen_keyfsm[4].u_sysrst_ctrl_detect_h2l 89.26 93.48 85.71 83.33 90.00 93.75
gen_keyfsm[4].u_sysrst_ctrl_detect_l2h 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_h2l 96.66 97.83 90.48 100.00 95.00 100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_l2h 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[6].u_sysrst_ctrl_detect_h2l 96.66 97.83 90.48 100.00 95.00 100.00
gen_keyfsm[6].u_sysrst_ctrl_detect_l2h 98.10 100.00 90.48 100.00 100.00 100.00
u_sysrst_ctrl_pin 100.00 100.00 100.00 100.00
u_cfg_ac_present_i_pin 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sysrst_ctrl_ulp 98.98 100.00 94.92 100.00 100.00 100.00
u_sysrst_ctrl_detect_ac_present 98.67 100.00 93.33 100.00 100.00 100.00
u_sysrst_ctrl_detect_lid_open 98.89 100.00 94.44 100.00 100.00 100.00
u_sysrst_ctrl_detect_pwrb 98.89 100.00 94.44 100.00 100.00 100.00
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