Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1884

1

T1

16

T3

8

T4

2

auto[1]

588

1

T2

5

T3

3

T4

11

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1929

1

T1

12

T2

4

T3

8

auto[1]

543

1

T1

4

T2

1

T3

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1943

1

T1

14

T2

4

T3

5

auto[1]

529

1

T1

2

T2

1

T3

6

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1832

1

T1

12

T2

3

T3

5

auto[1]

640

1

T1

4

T2

2

T3

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2255

1

T1

14

T2

5

T3

11

auto[1]

217

1

T1

2

T50

2

T49

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2173

1

T1

14

T2

5

T3

11

auto[1]

299

1

T1

2

T50

4

T49

8

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2188

1

T1

14

T2

5

T3

11

auto[1]

284

1

T1

2

T232

2

T233

9

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2254

1

T1

16

T2

5

T3

11

auto[1]

218

1

T51

4

T49

9

T233

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2278

1

T1

16

T2

5

T3

11

auto[1]

194

1

T48

4

T49

6

T232

14

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1883

1

T1

12

T2

1

T3

5

auto[1]

589

1

T1

4

T2

4

T3

6

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

698

1

T2

5

T3

11

T4

13

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

74

1

T1

2

T50

2

T236

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T48

4

T232

12

T235

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

9

1

T336

3

T195

3

T337

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

36

1

T51

4

T49

5

T336

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T238

5

T112

2

-

-

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

21

1

T338

1

T339

10

T340

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T233

1

T240

3

T339

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

126

1

T1

2

T233

6

T236

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T238

5

T341

4

T342

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

24

1

T236

3

T107

4

T299

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

17

1

T236

3

T237

1

T215

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T343

1

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T332

3

T344

1

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T1

2

T50

4

T86

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

38

1

T49

2

T345

14

T329

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

11

1

T346

1

T299

4

T239

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9

1

T49

2

T347

1

T213

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T234

18

T336

2

T332

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T234

3

T213

6

T340

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T49

4

T336

1

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T299

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T233

3

T332

2

T300

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T300

2

T348

2

T349

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

10

1

T232

2

T345

8

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

112

1

T52

10

T10

8

T50

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

118

1

T10

11

T233

3

T234

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

87

1

T2

2

T52

6

T51

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

103

1

T3

5

T49

2

T233

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

103

1

T4

5

T101

9

T232

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T110

2

T197

6

T345

14

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T2

2

T241

1

T300

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

72

1

T1

2

T49

2

T233

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

43

1

T49

5

T141

6

T319

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

49

1

T10

4

T350

3

T332

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T3

3

T105

2

T351

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

52

1

T11

4

T48

4

T105

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T4

3

T52

2

T101

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

35

1

T11

3

T350

1

T251

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T248

2

T352

1

T154

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

91

1

T52

10

T89

10

T104

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T141

5

T299

3

T195

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T13

3

T320

9

T353

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

49

1

T136

6

T246

4

T327

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T105

3

T350

9

T238

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T236

3

T209

1

T214

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

31

1

T1

4

T105

1

T236

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T252

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T232

6

T240

7

T324

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T2

1

T4

3

T232

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

19

1

T3

2

T50

2

T89

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T104

1

T251

1

T327

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

37

1

T101

3

T136

2

T319

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T246

1

T354

1

T207

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

16

1

T3

1

T4

2

T104

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T319

4

T355

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded