Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

637

1

T17

11

T29

10

T79

9

auto[1]

663

1

T17

9

T29

10

T79

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

297

1

T17

4

T29

4

T79

2

from_0to1

297

1

T17

3

T29

3

T79

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

625

1

T17

9

T29

7

T79

9

auto[1]

675

1

T17

11

T29

13

T79

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

657

1

T17

9

T29

11

T79

13

auto[1]

643

1

T17

11

T29

9

T79

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T17

1

T80

1

T54

4

auto[0]

from_1to0

auto[0]

auto[1]

39

1

T83

2

T366

3

T142

1

auto[0]

from_1to0

auto[1]

auto[0]

43

1

T29

2

T79

2

T80

1

auto[0]

from_1to0

auto[1]

auto[1]

36

1

T17

2

T80

1

T366

2

auto[0]

from_0to1

auto[0]

auto[0]

28

1

T79

1

T367

1

T142

1

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T29

3

T80

2

T54

2

auto[0]

from_0to1

auto[1]

auto[0]

40

1

T17

2

T54

1

T366

3

auto[0]

from_0to1

auto[1]

auto[1]

28

1

T17

1

T79

1

T80

1

auto[1]

from_1to0

auto[0]

auto[0]

32

1

T368

2

T367

1

T369

1

auto[1]

from_1to0

auto[0]

auto[1]

37

1

T17

1

T80

1

T54

1

auto[1]

from_1to0

auto[1]

auto[0]

33

1

T29

1

T366

1

T369

1

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T29

1

T80

1

T368

1

auto[1]

from_0to1

auto[0]

auto[0]

34

1

T80

2

T83

1

T366

3

auto[1]

from_0to1

auto[0]

auto[1]

46

1

T366

2

T368

1

T367

1

auto[1]

from_0to1

auto[1]

auto[0]

41

1

T366

1

T368

1

T369

1

auto[1]

from_0to1

auto[1]

auto[1]

36

1

T54

2

T369

2

T142

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

643

1

T17

9

T29

7

T79

12

auto[1]

657

1

T17

11

T29

13

T79

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

290

1

T17

4

T29

5

T79

4

from_0to1

296

1

T17

4

T29

4

T79

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

670

1

T17

11

T29

11

T79

10

auto[1]

630

1

T17

9

T29

9

T79

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

626

1

T17

10

T29

13

T79

11

auto[1]

674

1

T17

10

T29

7

T79

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

30

1

T17

1

T29

1

T79

1

auto[0]

from_1to0

auto[0]

auto[1]

32

1

T17

1

T79

1

T54

1

auto[0]

from_1to0

auto[1]

auto[0]

38

1

T17

1

T29

1

T366

4

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T54

1

T367

1

T369

1

auto[0]

from_0to1

auto[0]

auto[0]

44

1

T29

1

T79

2

T366

2

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T79

1

T80

2

T54

1

auto[0]

from_0to1

auto[1]

auto[0]

38

1

T79

1

T80

1

T83

1

auto[0]

from_0to1

auto[1]

auto[1]

29

1

T29

1

T54

1

T366

2

auto[1]

from_1to0

auto[0]

auto[0]

43

1

T29

2

T80

1

T54

1

auto[1]

from_1to0

auto[0]

auto[1]

37

1

T79

1

T80

1

T54

1

auto[1]

from_1to0

auto[1]

auto[0]

26

1

T80

1

T366

1

T368

2

auto[1]

from_1to0

auto[1]

auto[1]

41

1

T17

1

T29

1

T79

1

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T17

2

T29

1

T80

1

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T17

1

T80

1

T54

2

auto[1]

from_0to1

auto[1]

auto[0]

32

1

T54

1

T366

2

T368

1

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T17

1

T29

1

T79

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

685

1

T17

11

T29

11

T79

11

auto[1]

615

1

T17

9

T29

9

T79

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

293

1

T17

4

T29

5

T79

4

from_0to1

299

1

T17

4

T29

5

T79

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

617

1

T17

9

T29

16

T79

10

auto[1]

683

1

T17

11

T29

4

T79

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

646

1

T17

11

T29

9

T79

4

auto[1]

654

1

T17

9

T29

11

T79

16

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

36

1

T29

1

T54

1

T83

1

auto[0]

from_1to0

auto[0]

auto[1]

40

1

T17

1

T29

2

T54

1

auto[0]

from_1to0

auto[1]

auto[0]

36

1

T17

1

T80

1

T366

1

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T79

2

T80

1

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

41

1

T79

1

T80

1

T54

1

auto[0]

from_0to1

auto[0]

auto[1]

38

1

T79

1

T366

2

T368

1

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T17

1

T29

1

T79

1

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T80

1

T54

1

T83

2

auto[1]

from_1to0

auto[0]

auto[0]

29

1

T29

1

T80

1

T83

1

auto[1]

from_1to0

auto[0]

auto[1]

34

1

T17

1

T29

1

T79

1

auto[1]

from_1to0

auto[1]

auto[0]

35

1

T80

1

T54

2

T366

1

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T17

1

T79

1

T54

1

auto[1]

from_0to1

auto[0]

auto[0]

30

1

T17

2

T29

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

31

1

T29

3

T83

1

T366

1

auto[1]

from_0to1

auto[1]

auto[0]

39

1

T17

1

T80

1

T366

2

auto[1]

from_0to1

auto[1]

auto[1]

33

1

T79

2

T54

1

T142

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

663

1

T17

10

T29

13

T79

6

auto[1]

637

1

T17

10

T29

7

T79

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

314

1

T17

5

T29

4

T79

5

from_0to1

312

1

T17

6

T29

5

T79

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

674

1

T17

14

T29

11

T79

10

auto[1]

626

1

T17

6

T29

9

T79

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

670

1

T17

9

T29

10

T79

11

auto[1]

630

1

T17

11

T29

10

T79

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

25

1

T17

1

T79

1

T80

1

auto[0]

from_1to0

auto[0]

auto[1]

31

1

T370

2

T371

1

T372

2

auto[0]

from_1to0

auto[1]

auto[0]

45

1

T17

2

T29

1

T54

2

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T29

1

T54

1

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

37

1

T29

1

T80

2

T366

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T17

3

T83

2

T366

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T79

1

T83

1

T366

2

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T17

1

T29

1

T54

2

auto[1]

from_1to0

auto[0]

auto[0]

44

1

T29

2

T79

1

T80

1

auto[1]

from_1to0

auto[0]

auto[1]

45

1

T17

1

T79

2

T366

2

auto[1]

from_1to0

auto[1]

auto[0]

49

1

T79

1

T80

1

T54

1

auto[1]

from_1to0

auto[1]

auto[1]

32

1

T17

1

T83

2

T367

1

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T17

2

T29

2

T79

2

auto[1]

from_0to1

auto[0]

auto[1]

37

1

T79

1

T54

1

T366

3

auto[1]

from_0to1

auto[1]

auto[0]

35

1

T369

2

T142

1

T370

3

auto[1]

from_0to1

auto[1]

auto[1]

32

1

T29

1

T79

2

T54

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

667

1

T17

14

T29

8

T79

12

auto[1]

633

1

T17

6

T29

12

T79

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

296

1

T17

4

T29

5

T79

4

from_0to1

297

1

T17

5

T29

4

T79

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

635

1

T17

9

T29

9

T79

10

auto[1]

665

1

T17

11

T29

11

T79

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

660

1

T17

8

T29

9

T79

11

auto[1]

640

1

T17

12

T29

11

T79

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T17

2

T29

1

T80

1

auto[0]

from_1to0

auto[0]

auto[1]

38

1

T17

1

T79

1

T80

1

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T79

2

T366

3

T367

2

auto[0]

from_1to0

auto[1]

auto[1]

36

1

T17

1

T29

2

T366

1

auto[0]

from_0to1

auto[0]

auto[0]

33

1

T80

2

T366

1

T367

1

auto[0]

from_0to1

auto[0]

auto[1]

38

1

T29

1

T79

1

T54

1

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T17

2

T79

1

T80

1

auto[0]

from_0to1

auto[1]

auto[1]

31

1

T17

2

T79

1

T83

1

auto[1]

from_1to0

auto[0]

auto[0]

26

1

T79

1

T369

2

T142

3

auto[1]

from_1to0

auto[0]

auto[1]

30

1

T366

1

T367

1

T373

2

auto[1]

from_1to0

auto[1]

auto[0]

37

1

T29

2

T83

1

T366

3

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T80

2

T54

1

T83

1

auto[1]

from_0to1

auto[0]

auto[0]

30

1

T29

1

T366

1

T367

2

auto[1]

from_0to1

auto[0]

auto[1]

36

1

T17

1

T79

1

T366

1

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T29

1

T79

1

T80

1

auto[1]

from_0to1

auto[1]

auto[1]

34

1

T29

1

T54

1

T366

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

629

1

T17

11

T29

8

T79

11

auto[1]

671

1

T17

9

T29

12

T79

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

317

1

T17

4

T29

5

T79

5

from_0to1

321

1

T17

4

T29

5

T79

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T17

12

T29

12

T79

9

auto[1]

652

1

T17

8

T29

8

T79

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

629

1

T17

10

T29

9

T79

13

auto[1]

671

1

T17

10

T29

11

T79

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

39

1

T80

1

T54

1

T83

1

auto[0]

from_1to0

auto[0]

auto[1]

42

1

T17

2

T29

2

T54

1

auto[0]

from_1to0

auto[1]

auto[0]

45

1

T29

1

T79

1

T80

1

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T79

1

T80

1

T54

2

auto[0]

from_0to1

auto[0]

auto[0]

41

1

T79

1

T80

1

T368

1

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T17

1

T29

1

T79

1

auto[0]

from_0to1

auto[1]

auto[0]

36

1

T79

1

T54

2

T366

2

auto[0]

from_0to1

auto[1]

auto[1]

37

1

T17

1

T80

1

T54

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T17

1

T79

1

T80

1

auto[1]

from_1to0

auto[0]

auto[1]

42

1

T79

2

T368

1

T367

1

auto[1]

from_1to0

auto[1]

auto[0]

34

1

T366

1

T369

1

T370

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T17

1

T29

2

T80

1

auto[1]

from_0to1

auto[0]

auto[0]

41

1

T29

1

T79

1

T54

2

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T29

2

T83

1

T366

4

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T17

1

T29

1

T80

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T17

1

T80

1

T83

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

673

1

T17

9

T29

11

T79

10

auto[1]

627

1

T17

11

T29

9

T79

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

311

1

T17

5

T29

5

T79

3

from_0to1

310

1

T17

5

T29

5

T79

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

645

1

T17

12

T29

10

T79

14

auto[1]

655

1

T17

8

T29

10

T79

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

650

1

T17

9

T29

13

T79

8

auto[1]

650

1

T17

11

T29

7

T79

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T17

1

T80

1

T54

2

auto[0]

from_1to0

auto[0]

auto[1]

36

1

T29

2

T79

2

T80

2

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T29

1

T80

1

T83

1

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T17

2

T54

1

T83

3

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T17

2

T29

1

T83

1

auto[0]

from_0to1

auto[0]

auto[1]

38

1

T80

1

T54

1

T83

1

auto[0]

from_0to1

auto[1]

auto[0]

31

1

T17

1

T29

1

T54

2

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T54

1

T83

1

T366

2

auto[1]

from_1to0

auto[0]

auto[0]

37

1

T366

1

T370

1

T373

1

auto[1]

from_1to0

auto[0]

auto[1]

32

1

T17

2

T29

1

T367

1

auto[1]

from_1to0

auto[1]

auto[0]

43

1

T29

1

T79

1

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T54

2

T83

1

T366

2

auto[1]

from_0to1

auto[0]

auto[0]

38

1

T29

1

T80

1

T83

2

auto[1]

from_0to1

auto[0]

auto[1]

32

1

T29

1

T79

1

T80

2

auto[1]

from_0to1

auto[1]

auto[0]

28

1

T29

1

T80

1

T83

1

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T17

2

T79

1

T54

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

652

1

T17

9

T29

13

T79

12

auto[1]

648

1

T17

11

T29

7

T79

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

307

1

T17

4

T29

6

T79

3

from_0to1

313

1

T17

5

T29

6

T79

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

645

1

T17

10

T29

8

T79

10

auto[1]

655

1

T17

10

T29

12

T79

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

639

1

T17

12

T29

7

T79

12

auto[1]

661

1

T17

8

T29

13

T79

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

36

1

T79

1

T80

1

T369

2

auto[0]

from_1to0

auto[0]

auto[1]

33

1

T17

1

T80

1

T54

2

auto[0]

from_1to0

auto[1]

auto[0]

30

1

T29

1

T54

1

T83

1

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T29

2

T79

1

T366

3

auto[0]

from_0to1

auto[0]

auto[0]

37

1

T17

1

T29

1

T79

2

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T29

2

T54

2

T367

2

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T17

1

T80

2

T54

2

auto[0]

from_0to1

auto[1]

auto[1]

34

1

T29

2

T80

1

T366

1

auto[1]

from_1to0

auto[0]

auto[0]

36

1

T17

1

T366

2

T368

1

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T17

1

T83

2

T366

3

auto[1]

from_1to0

auto[1]

auto[0]

43

1

T17

1

T29

1

T79

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T29

2

T80

1

T54

2

auto[1]

from_0to1

auto[0]

auto[0]

38

1

T29

1

T366

2

T368

1

auto[1]

from_0to1

auto[0]

auto[1]

36

1

T17

1

T79

1

T366

2

auto[1]

from_0to1

auto[1]

auto[0]

32

1

T17

2

T79

1

T54

2

auto[1]

from_0to1

auto[1]

auto[1]

38

1

T80

1

T83

2

T366

3