Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148514	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113190

1

T5

110

T6

5

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	140324	1			T5	3		T6	2		T7	2
values[0x0]	60047	1			T5	223		T6	8		T1	346
values[0x1]	61333	1			T5	201		T6	8		T1	311

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	119542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

142162

1

T5

143

T6

7

T7

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	809	1			T5	7		T14	2		T15	2
valid_sources[0x01]	793	1			T5	2		T14	3		T15	5
valid_sources[0x02]	819	1			T14	3		T16	4		T3	2
valid_sources[0x03]	1128	1			T5	1		T14	1		T2	3
valid_sources[0x04]	765	1			T14	2		T15	1		T16	3
valid_sources[0x05]	1218	1			T5	2		T14	1		T15	2
valid_sources[0x06]	1687	1			T14	2		T3	1		T10	2
valid_sources[0x07]	1055	1			T5	2		T14	4		T15	3
valid_sources[0x08]	1653	1			T14	1		T2	2		T3	3
valid_sources[0x09]	883	1			T5	8		T15	1		T3	1
valid_sources[0x0a]	1016	1			T5	2		T14	1		T15	1
valid_sources[0x0b]	1068	1			T5	2		T14	2		T15	2
valid_sources[0x0c]	902	1			T5	2		T14	2		T15	1
valid_sources[0x0d]	841	1			T5	1		T14	1		T15	2
valid_sources[0x0e]	993	1			T14	1		T2	1		T3	1
valid_sources[0x0f]	681	1			T14	2		T2	1		T3	4
valid_sources[0x10]	1062	1			T14	1		T15	1		T2	1
valid_sources[0x11]	1503	1			T5	2		T15	1		T3	2
valid_sources[0x12]	1206	1			T14	2		T15	2		T16	2
valid_sources[0x13]	1296	1			T5	2		T14	1		T15	2
valid_sources[0x14]	835	1			T14	2		T15	2		T3	6
valid_sources[0x15]	1011	1			T5	3		T14	1		T2	2
valid_sources[0x16]	783	1			T5	4		T14	4		T2	2
valid_sources[0x17]	1501	1			T5	3		T14	1		T15	1
valid_sources[0x18]	1614	1			T5	5		T2	4		T3	4
valid_sources[0x19]	858	1			T14	2		T15	3		T17	3
valid_sources[0x1a]	1002	1			T5	3		T15	2		T2	1
valid_sources[0x1b]	865	1			T5	6		T14	1		T15	1
valid_sources[0x1c]	867	1			T5	2		T14	1		T15	1
valid_sources[0x1d]	875	1			T5	3		T14	1		T15	1
valid_sources[0x1e]	1941	1			T5	1		T14	3		T15	6
valid_sources[0x1f]	775	1			T15	1		T3	1		T81	1
valid_sources[0x20]	3037	1			T1	876		T14	1		T15	1
valid_sources[0x21]	1018	1			T5	4		T2	1		T4	3
valid_sources[0x22]	1370	1			T5	8		T7	1		T14	1
valid_sources[0x23]	909	1			T14	1		T15	3		T17	1
valid_sources[0x24]	903	1			T5	2		T14	3		T15	3
valid_sources[0x25]	1268	1			T5	1		T15	2		T2	1
valid_sources[0x26]	883	1			T5	2		T14	2		T15	3
valid_sources[0x27]	1063	1			T5	4		T14	2		T2	4
valid_sources[0x28]	1009	1			T5	8		T14	2		T15	1
valid_sources[0x29]	879	1			T5	1		T15	1		T2	3
valid_sources[0x2a]	1055	1			T14	1		T17	1		T2	4
valid_sources[0x2b]	921	1			T14	4		T15	3		T2	1
valid_sources[0x2c]	773	1			T5	7		T15	4		T3	4
valid_sources[0x2d]	990	1			T15	1		T2	3		T3	4
valid_sources[0x2e]	938	1			T5	1		T14	1		T15	1
valid_sources[0x2f]	903	1			T15	2		T17	2		T2	2
valid_sources[0x30]	1045	1			T5	3		T15	2		T17	1
valid_sources[0x31]	1262	1			T5	2		T14	3		T17	12
valid_sources[0x32]	788	1			T5	1		T14	1		T15	1
valid_sources[0x33]	882	1			T5	2		T14	1		T15	1
valid_sources[0x34]	789	1			T5	4		T14	3		T2	2
valid_sources[0x35]	1079	1			T5	1		T2	1		T3	1
valid_sources[0x36]	861	1			T14	2		T15	1		T2	2
valid_sources[0x37]	972	1			T5	2		T14	4		T15	1
valid_sources[0x38]	2288	1			T5	1		T15	1		T2	2
valid_sources[0x39]	980	1			T5	1		T14	4		T15	2
valid_sources[0x3a]	1079	1			T14	5		T15	2		T2	2
valid_sources[0x3b]	1202	1			T5	1		T15	1		T2	1
valid_sources[0x3c]	904	1			T15	4		T2	1		T3	1
valid_sources[0x3d]	1067	1			T5	3		T14	2		T15	1
valid_sources[0x3e]	950	1			T5	4		T15	1		T16	2
valid_sources[0x3f]	1175	1			T5	1		T14	1		T15	2
valid_sources[0x40]	1108	1			T5	2		T15	2		T3	6
valid_sources[0x41]	1021	1			T5	1		T14	3		T15	1
valid_sources[0x42]	745	1			T2	1		T3	2		T81	2
valid_sources[0x43]	933	1			T5	2		T15	2		T2	2
valid_sources[0x44]	868	1			T5	2		T14	1		T15	3
valid_sources[0x45]	937	1			T5	3		T14	9		T15	2
valid_sources[0x46]	959	1			T15	2		T3	5		T4	2
valid_sources[0x47]	801	1			T5	3		T15	4		T16	1
valid_sources[0x48]	703	1			T5	1		T14	2		T15	3
valid_sources[0x49]	773	1			T5	2		T14	2		T15	3
valid_sources[0x4a]	838	1			T5	4		T15	1		T2	1
valid_sources[0x4b]	781	1			T5	2		T14	1		T15	1
valid_sources[0x4c]	990	1			T14	1		T15	1		T17	7
valid_sources[0x4d]	1106	1			T5	1		T14	1		T15	2
valid_sources[0x4e]	984	1			T5	4		T14	1		T15	2
valid_sources[0x4f]	1066	1			T5	3		T14	2		T15	2
valid_sources[0x50]	1233	1			T14	1		T15	1		T17	7
valid_sources[0x51]	1232	1			T14	3		T15	2		T81	2
valid_sources[0x52]	916	1			T5	4		T14	3		T15	1
valid_sources[0x53]	956	1			T14	4		T15	2		T2	1
valid_sources[0x54]	1060	1			T5	2		T15	1		T2	3
valid_sources[0x55]	849	1			T5	2		T14	4		T15	2
valid_sources[0x56]	956	1			T5	2		T14	1		T2	2
valid_sources[0x57]	911	1			T14	2		T15	1		T2	5
valid_sources[0x58]	888	1			T5	3		T14	2		T15	4
valid_sources[0x59]	1212	1			T5	5		T14	1		T15	3
valid_sources[0x5a]	934	1			T14	2		T2	3		T3	3
valid_sources[0x5b]	843	1			T5	6		T14	4		T15	2
valid_sources[0x5c]	870	1			T14	2		T15	1		T3	3
valid_sources[0x5d]	865	1			T5	2		T15	2		T2	2
valid_sources[0x5e]	839	1			T5	3		T15	2		T2	5
valid_sources[0x5f]	881	1			T5	4		T14	3		T15	3
valid_sources[0x60]	788	1			T16	1		T17	5		T2	3
valid_sources[0x61]	809	1			T5	1		T14	2		T2	2
valid_sources[0x62]	848	1			T5	4		T14	2		T2	2
valid_sources[0x63]	852	1			T14	2		T15	1		T2	3
valid_sources[0x64]	924	1			T14	5		T15	1		T3	2
valid_sources[0x65]	1188	1			T15	3		T16	1		T2	3
valid_sources[0x66]	1004	1			T14	4		T15	1		T2	5
valid_sources[0x67]	996	1			T5	1		T2	6		T81	3
valid_sources[0x68]	1092	1			T5	2		T14	4		T15	1
valid_sources[0x69]	954	1			T5	1		T14	5		T15	4
valid_sources[0x6a]	888	1			T5	6		T14	1		T15	1
valid_sources[0x6b]	1231	1			T5	1		T14	4		T2	2
valid_sources[0x6c]	845	1			T14	1		T15	1		T3	5
valid_sources[0x6d]	946	1			T15	1		T16	3		T2	4
valid_sources[0x6e]	764	1			T5	2		T15	1		T17	1
valid_sources[0x6f]	1539	1			T5	7		T14	2		T15	3
valid_sources[0x70]	974	1			T15	1		T2	1		T3	3
valid_sources[0x71]	785	1			T5	2		T15	4		T2	1
valid_sources[0x72]	861	1			T14	2		T15	1		T2	1
valid_sources[0x73]	807	1			T5	4		T14	1		T2	1
valid_sources[0x74]	926	1			T5	1		T14	1		T15	1
valid_sources[0x75]	998	1			T15	1		T2	3		T3	2
valid_sources[0x76]	1724	1			T5	4		T15	3		T16	2
valid_sources[0x77]	1027	1			T5	1		T15	5		T2	2
valid_sources[0x78]	1021	1			T14	2		T15	3		T2	2
valid_sources[0x79]	878	1			T7	1		T14	2		T15	4
valid_sources[0x7a]	995	1			T5	3		T14	3		T15	2
valid_sources[0x7b]	858	1			T14	2		T2	1		T3	4
valid_sources[0x7c]	762	1			T5	1		T14	1		T15	3
valid_sources[0x7d]	837	1			T5	2		T14	2		T15	1
valid_sources[0x7e]	2154	1			T14	1		T15	2		T16	4
valid_sources[0x7f]	826	1			T2	2		T3	4		T4	5
valid_sources[0x80]	855	1			T14	1		T15	1		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62066

1

T5

2

T6

1

T7

1

values[0x0]

all_enables

biggest_size

29672

1

T5

71

T6

2

T1

126

values[0x1]

all_enables

biggest_size

21452

1

T5

37

T6

2

T1

58