Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T31,T32,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T31,T32,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T31,T32,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T27
1	0	Covered	T5,T7,T1
1	1	Covered	T31,T32,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T27
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T27
0	1	Covered	T31,T32,T27
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T32,T27
1	-	Covered	T31,T32,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T31,T32,T27
DetectSt	168	Covered	T31,T32,T27
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T31,T32,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T32,T27
DebounceSt->IdleSt	163	Covered	T102,T122,T123
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T31,T32,T27
IdleSt->DebounceSt	148	Covered	T31,T32,T27
StableSt->IdleSt	206	Covered	T31,T32,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T31,T32,T27
0	1	Covered	T31,T32,T27
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T27
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T32,T27
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T32,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T102,T122,T123
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T32,T27
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T31,T32,T27
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T32,T27
StableSt	-	-	-	-	-	-	0	Covered	T31,T32,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	185	0	0
CntIncr_A	4968661	132638	0	0
CntNoWrap_A	4968661	4511849	0	0
DetectStDropOut_A	4968661	0	0	0
DetectedOut_A	4968661	584	0	0
DetectedPulseOut_A	4968661	85	0	0
DisabledIdleSt_A	4968661	4375131	0	0
DisabledNoDetection_A	4968661	4376874	0	0
EnterDebounceSt_A	4968661	101	0	0
EnterDetectSt_A	4968661	85	0	0
EnterStableSt_A	4968661	85	0	0
PulseIsPulse_A	4968661	85	0	0
StayInStableSt	4968661	499	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	4968661	5379	0	0
gen_low_level_sva.LowLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	85	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	185	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T27	0	4	0	0
T31	769	2	0	0
T32	779	2	0	0
T53	0	6	0	0
T54	0	2	0	0
T55	0	4	0	0
T56	0	2	0	0
T58	0	4	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T102	0	5	0	0
T103	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	132638	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T27	0	65	0	0
T31	769	79	0	0
T32	779	91	0	0
T53	0	213	0	0
T54	0	93	0	0
T55	0	73	0	0
T56	0	48	0	0
T58	0	178	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T102	0	120	0	0
T103	0	59	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511849	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	584	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T27	0	18	0	0
T31	769	7	0	0
T32	779	2	0	0
T53	0	28	0	0
T54	0	10	0	0
T55	0	5	0	0
T56	0	3	0	0
T58	0	18	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T102	0	14	0	0
T103	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	85	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T27	0	2	0	0
T31	769	1	0	0
T32	779	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T58	0	2	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T102	0	2	0	0
T103	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4375131	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4376874	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	101	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T27	0	2	0	0
T31	769	1	0	0
T32	779	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T58	0	2	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T102	0	3	0	0
T103	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	85	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T27	0	2	0	0
T31	769	1	0	0
T32	779	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T58	0	2	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T102	0	2	0	0
T103	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	85	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T27	0	2	0	0
T31	769	1	0	0
T32	779	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T58	0	2	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T102	0	2	0	0
T103	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	85	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T27	0	2	0	0
T31	769	1	0	0
T32	779	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T58	0	2	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T102	0	2	0	0
T103	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	499	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T27	0	16	0	0
T31	769	6	0	0
T32	779	1	0	0
T53	0	25	0	0
T54	0	9	0	0
T55	0	3	0	0
T56	0	2	0	0
T58	0	16	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T102	0	12	0	0
T103	0	2	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	5379	0	0
T1	14193	26	0	0
T2	10710	10	0	0
T3	0	10	0	0
T4	0	10	0	0
T5	5416	28	0	0
T6	405	0	0	0
T7	4404	0	0	0
T8	0	1	0	0
T14	5270	22	0	0
T15	2369	0	0	0
T16	3046	10	0	0
T17	502	5	0	0
T18	403	0	0	0
T52	0	11	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	85	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T27	0	2	0	0
T31	769	1	0	0
T32	779	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T58	0	2	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T102	0	2	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T12,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T12,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T23,T27,T64

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T23,T24
1	0	Covered	T5,T7,T1
1	1	Covered	T12,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T27,T64
0	1	Covered	T96,T97
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T27,T64
0	1	Unreachable
1	0	Covered	T23,T27,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T23,T24
DetectSt	168	Covered	T23,T27,T64
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T23,T27,T64

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T27,T64
DebounceSt->IdleSt	163	Covered	T12,T24,T119
DetectSt->IdleSt	186	Covered	T96,T97
DetectSt->StableSt	191	Covered	T23,T27,T64
IdleSt->DebounceSt	148	Covered	T12,T23,T24
StableSt->IdleSt	206	Covered	T23,T27,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T23,T24
0	1	Covered	T12,T23,T24
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T27,T64
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T27,T64
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T24,T119
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T96,T97
DetectSt	-	-	-	-	0	1	-	Covered	T23,T27,T64
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T27,T64
StableSt	-	-	-	-	-	-	0	Covered	T23,T27,T64
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	96	0	0
CntIncr_A	4968661	79606	0	0
CntNoWrap_A	4968661	4511938	0	0
DetectStDropOut_A	4968661	2	0	0
DetectedOut_A	4968661	444103	0	0
DetectedPulseOut_A	4968661	32	0	0
DisabledIdleSt_A	4968661	3477170	0	0
DisabledNoDetection_A	4968661	3478940	0	0
EnterDebounceSt_A	4968661	64	0	0
EnterDetectSt_A	4968661	34	0	0
EnterStableSt_A	4968661	32	0	0
PulseIsPulse_A	4968661	32	0	0
StayInStableSt	4968661	444071	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	4968661	5379	0	0
gen_low_level_sva.LowLevelEvent_A	4968661	4513807	0	0
gen_sticky_sva.StableStDropOut_A	4968661	508108	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	96	0	0
T12	1232	1	0	0
T13	10564	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T27	0	2	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	4	0	0
T65	0	2	0	0
T66	0	4	0	0
T68	0	2	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T88	0	2	0	0
T119	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	79606	0	0
T12	1232	35	0	0
T13	10564	0	0	0
T23	0	21	0	0
T24	0	36	0	0
T27	0	32557	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	142	0	0
T65	0	16631	0	0
T66	0	122	0	0
T68	0	10	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T88	0	77	0	0
T119	0	164	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511938	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2	0	0
T96	773	1	0	0
T97	0	1	0	0
T124	427	0	0	0
T125	1952	0	0	0
T126	402	0	0	0
T127	448	0	0	0
T128	402	0	0	0
T129	708	0	0	0
T130	492	0	0	0
T131	1103	0	0	0
T132	747	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	444103	0	0
T23	538	12	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	0	162551	0	0
T28	3195	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T42	724	0	0	0
T64	0	628	0	0
T65	0	98899	0	0
T66	0	144	0	0
T68	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T88	0	94	0	0
T119	0	32	0	0
T120	0	1	0	0
T121	0	242	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	32	0	0
T23	538	1	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	0	1	0	0
T28	3195	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T42	724	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T88	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3477170	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3478940	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	64	0	0
T12	1232	1	0	0
T13	10564	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T88	0	1	0	0
T119	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	34	0	0
T23	538	1	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	0	1	0	0
T28	3195	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T42	724	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T88	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	32	0	0
T23	538	1	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	0	1	0	0
T28	3195	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T42	724	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T88	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	32	0	0
T23	538	1	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	0	1	0	0
T28	3195	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T42	724	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T88	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	444071	0	0
T23	538	11	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	0	162550	0	0
T28	3195	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T42	724	0	0	0
T64	0	626	0	0
T65	0	98898	0	0
T66	0	142	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T88	0	93	0	0
T119	0	31	0	0
T121	0	241	0	0
T133	0	98	0	0
T134	0	575	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	5379	0	0
T1	14193	26	0	0
T2	10710	10	0	0
T3	0	10	0	0
T4	0	10	0	0
T5	5416	28	0	0
T6	405	0	0	0
T7	4404	0	0	0
T8	0	1	0	0
T14	5270	22	0	0
T15	2369	0	0	0
T16	3046	10	0	0
T17	502	5	0	0
T18	403	0	0	0
T52	0	11	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	508108	0	0
T23	538	59	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	0	75	0	0
T28	3195	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T42	724	0	0	0
T64	0	435	0	0
T65	0	94	0	0
T66	0	210	0	0
T68	0	102	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T88	0	65	0	0
T119	0	179	0	0
T120	0	203	0	0
T121	0	75	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T16,T17,T8

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T16,T17,T8
1	1	Covered	T16,T17,T8

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T12,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T12,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T12,T23,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T23,T24
1	0	Covered	T16,T17,T8
1	1	Covered	T12,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T23,T27
0	1	Covered	T68,T87,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T23,T27
0	1	Unreachable
1	0	Covered	T12,T23,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T23,T24
DetectSt	168	Covered	T12,T23,T27
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T12,T23,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T23,T27
DebounceSt->IdleSt	163	Covered	T24,T64,T119
DetectSt->IdleSt	186	Covered	T68,T87,T95
DetectSt->StableSt	191	Covered	T12,T23,T27
IdleSt->DebounceSt	148	Covered	T12,T23,T24
StableSt->IdleSt	206	Covered	T12,T23,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T23,T24
0	1	Covered	T12,T23,T24
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T23,T27
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T23,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T64,T119
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T68,T87,T95
DetectSt	-	-	-	-	0	1	-	Covered	T12,T23,T27
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T23,T27
StableSt	-	-	-	-	-	-	0	Covered	T12,T23,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	103	0	0
CntIncr_A	4968661	64218	0	0
CntNoWrap_A	4968661	4511931	0	0
DetectStDropOut_A	4968661	7	0	0
DetectedOut_A	4968661	447390	0	0
DetectedPulseOut_A	4968661	29	0	0
DisabledIdleSt_A	4968661	3477170	0	0
DisabledNoDetection_A	4968661	3478940	0	0
EnterDebounceSt_A	4968661	69	0	0
EnterDetectSt_A	4968661	36	0	0
EnterStableSt_A	4968661	29	0	0
PulseIsPulse_A	4968661	29	0	0
StayInStableSt	4968661	447361	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_sticky_sva.StableStDropOut_A	4968661	517980	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	103	0	0
T12	1232	2	0	0
T13	10564	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T27	0	2	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	7	0	0
T65	0	2	0	0
T66	0	4	0	0
T68	0	2	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	2	0	0
T88	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	64218	0	0
T12	1232	76	0	0
T13	10564	0	0	0
T23	0	43	0	0
T24	0	73	0	0
T27	0	24	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	476	0	0
T65	0	73	0	0
T66	0	184	0	0
T68	0	82	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	20	0	0
T88	0	77	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511931	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	7	0	0
T68	1119	1	0	0
T87	569	1	0	0
T95	0	4	0	0
T105	39121	0	0	0
T135	0	1	0	0
T136	17999	0	0	0
T137	403	0	0	0
T138	1184	0	0	0
T139	973	0	0	0
T140	2094	0	0	0
T141	23213	0	0	0
T142	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	447390	0	0
T12	1232	30	0	0
T13	10564	0	0	0
T23	0	25	0	0
T27	0	56	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T65	0	488	0	0
T66	0	204	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T88	0	131	0	0
T99	0	281	0	0
T119	0	60	0	0
T120	0	85	0	0
T121	0	245	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	29	0	0
T12	1232	1	0	0
T13	10564	0	0	0
T23	0	1	0	0
T27	0	1	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T88	0	1	0	0
T99	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3477170	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3478940	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	69	0	0
T12	1232	1	0	0
T13	10564	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	7	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	1	0	0
T88	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	36	0	0
T12	1232	1	0	0
T13	10564	0	0	0
T23	0	1	0	0
T27	0	1	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	1	0	0
T88	0	1	0	0
T99	0	1	0	0
T119	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	29	0	0
T12	1232	1	0	0
T13	10564	0	0	0
T23	0	1	0	0
T27	0	1	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T88	0	1	0	0
T99	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	29	0	0
T12	1232	1	0	0
T13	10564	0	0	0
T23	0	1	0	0
T27	0	1	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T88	0	1	0	0
T99	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	447361	0	0
T12	1232	29	0	0
T13	10564	0	0	0
T23	0	24	0	0
T27	0	55	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T65	0	487	0	0
T66	0	202	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T88	0	130	0	0
T99	0	280	0	0
T119	0	59	0	0
T120	0	84	0	0
T121	0	244	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	517980	0	0
T12	1232	53	0	0
T13	10564	0	0	0
T23	0	26	0	0
T27	0	195111	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T65	0	115077	0	0
T66	0	89	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T88	0	46	0	0
T99	0	119	0	0
T119	0	153	0	0
T120	0	30	0	0
T121	0	91	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T12,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T12,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T12,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T23,T24
1	0	Covered	T5,T1,T14
1	1	Covered	T12,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T23,T24
0	1	Covered	T27,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T23,T24
0	1	Unreachable
1	0	Covered	T12,T23,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T23,T24
DetectSt	168	Covered	T12,T23,T24
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T12,T23,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T23,T24
DebounceSt->IdleSt	163	Covered	T99,T100,T63
DetectSt->IdleSt	186	Covered	T27,T94
DetectSt->StableSt	191	Covered	T12,T23,T24
IdleSt->DebounceSt	148	Covered	T12,T23,T24
StableSt->IdleSt	206	Covered	T12,T23,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T23,T24
0	1	Covered	T12,T23,T24
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T23,T24
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T99,T100,T143
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T27,T94
DetectSt	-	-	-	-	0	1	-	Covered	T12,T23,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T23,T24
StableSt	-	-	-	-	-	-	0	Covered	T12,T23,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	97	0	0
CntIncr_A	4968661	3233	0	0
CntNoWrap_A	4968661	4511937	0	0
DetectStDropOut_A	4968661	2	0	0
DetectedOut_A	4968661	7860	0	0
DetectedPulseOut_A	4968661	41	0	0
DisabledIdleSt_A	4968661	3477170	0	0
DisabledNoDetection_A	4968661	3478940	0	0
EnterDebounceSt_A	4968661	56	0	0
EnterDetectSt_A	4968661	43	0	0
EnterStableSt_A	4968661	41	0	0
PulseIsPulse_A	4968661	41	0	0
StayInStableSt	4968661	7819	0	0
gen_high_event_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_sticky_sva.StableStDropOut_A	4968661	957365	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	97	0	0
T12	1232	2	0	0
T13	10564	0	0	0
T23	0	2	0	0
T24	0	2	0	0
T27	0	4	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	4	0	0
T65	0	2	0	0
T66	0	4	0	0
T68	0	2	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	2	0	0
T88	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3233	0	0
T12	1232	72	0	0
T13	10564	0	0	0
T23	0	38	0	0
T24	0	69	0	0
T27	0	118	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	130	0	0
T65	0	67	0	0
T66	0	70	0	0
T68	0	11	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	92	0	0
T88	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511937	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2	0	0
T27	197659	1	0	0
T37	1908	0	0	0
T53	766	0	0	0
T54	2601	0	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T85	5569	0	0	0
T94	0	1	0	0
T144	591	0	0	0
T145	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	7860	0	0
T12	1232	52	0	0
T13	10564	0	0	0
T23	0	24	0	0
T24	0	23	0	0
T27	0	61	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	737	0	0
T65	0	288	0	0
T66	0	89	0	0
T68	0	3	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	17	0	0
T88	0	23	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	41	0	0
T12	1232	1	0	0
T13	10564	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	1	0	0
T88	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3477170	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3478940	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	56	0	0
T12	1232	1	0	0
T13	10564	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	1	0	0
T88	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	43	0	0
T12	1232	1	0	0
T13	10564	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	1	0	0
T88	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	41	0	0
T12	1232	1	0	0
T13	10564	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	1	0	0
T88	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	41	0	0
T12	1232	1	0	0
T13	10564	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	1	0	0
T88	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	7819	0	0
T12	1232	51	0	0
T13	10564	0	0	0
T23	0	23	0	0
T24	0	22	0	0
T27	0	60	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	735	0	0
T65	0	287	0	0
T66	0	87	0	0
T68	0	2	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	16	0	0
T88	0	22	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	957365	0	0
T12	1232	50	0	0
T13	10564	0	0	0
T23	0	39	0	0
T24	0	69	0	0
T27	0	130023	0	0
T32	779	0	0	0
T48	15560	0	0	0
T50	12242	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T64	0	365	0	0
T65	0	115289	0	0
T66	0	350	0	0
T68	0	101	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T87	0	23	0	0
T88	0	220	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T42,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T8,T42,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T42,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T42,T37
1	0	Covered	T5,T6,T7
1	1	Covered	T8,T42,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T42,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T40,T39
0	1	Covered	T8,T41,T43
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T40,T39
1	-	Covered	T8,T41,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T42,T40
DetectSt	168	Covered	T8,T42,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T8,T42,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T42,T40
DebounceSt->IdleSt	163	Covered	T44,T146,T90
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T42,T40
IdleSt->DebounceSt	148	Covered	T8,T42,T40
StableSt->IdleSt	206	Covered	T8,T41,T147

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T42,T40
0	1	Covered	T8,T42,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T42,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T42,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T42,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T42,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T42,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T41,T43
StableSt	-	-	-	-	-	-	0	Covered	T42,T40,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	55	0	0
CntIncr_A	4968661	1524	0	0
CntNoWrap_A	4968661	4511979	0	0
DetectStDropOut_A	4968661	0	0	0
DetectedOut_A	4968661	2057	0	0
DetectedPulseOut_A	4968661	26	0	0
DisabledIdleSt_A	4968661	4499258	0	0
DisabledNoDetection_A	4968661	4500991	0	0
EnterDebounceSt_A	4968661	30	0	0
EnterDetectSt_A	4968661	26	0	0
EnterStableSt_A	4968661	26	0	0
PulseIsPulse_A	4968661	26	0	0
StayInStableSt	4968661	2013	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	7	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	55	0	0
T8	598	2	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	4	0	0
T44	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	2	0	0
T147	0	2	0	0
T148	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1524	0	0
T8	598	26	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T39	0	80	0	0
T40	0	80	0	0
T41	0	46	0	0
T42	0	57	0	0
T43	0	42	0	0
T44	0	22	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	87	0	0
T147	0	33	0	0
T148	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511979	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2057	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T39	0	191	0	0
T40	0	41	0	0
T41	0	1	0	0
T42	0	39	0	0
T43	0	118	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	97	0	0
T147	0	40	0	0
T148	0	155	0	0
T149	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	26	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4499258	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4500991	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	30	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	26	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	26	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	26	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2013	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T39	0	189	0	0
T40	0	39	0	0
T42	724	37	0	0
T43	0	115	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T91	0	95	0	0
T144	591	0	0	0
T145	423	0	0	0
T147	0	38	0	0
T148	0	153	0	0
T149	0	40	0	0
T150	0	86	0	0
T151	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	7	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T42,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T42,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T44,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T42,T37
1	0	Covered	T7,T1,T15
1	1	Covered	T9,T42,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T44,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T44,T45
0	1	Covered	T9,T44,T41
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T44,T45
1	-	Covered	T9,T44,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T42,T44
DetectSt	168	Covered	T9,T44,T45
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T9,T44,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T44,T45
DebounceSt->IdleSt	163	Covered	T42,T90,T155
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T44,T45
IdleSt->DebounceSt	148	Covered	T9,T42,T44
StableSt->IdleSt	206	Covered	T9,T44,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T42,T44
0	1	Covered	T9,T42,T44
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T44,T45
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T42,T44
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T44,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T155,T156
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T42,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T44,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T44,T41
StableSt	-	-	-	-	-	-	0	Covered	T9,T44,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	92	0	0
CntIncr_A	4968661	34582	0	0
CntNoWrap_A	4968661	4511942	0	0
DetectStDropOut_A	4968661	0	0	0
DetectedOut_A	4968661	2594	0	0
DetectedPulseOut_A	4968661	44	0	0
DisabledIdleSt_A	4968661	4435183	0	0
DisabledNoDetection_A	4968661	4436915	0	0
EnterDebounceSt_A	4968661	48	0	0
EnterDetectSt_A	4968661	44	0	0
EnterStableSt_A	4968661	44	0	0
PulseIsPulse_A	4968661	44	0	0
StayInStableSt	4968661	2531	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	4968661	1582	0	0
gen_low_level_sva.LowLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	92	0	0
T9	963	4	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T41	0	4	0	0
T42	0	1	0	0
T44	0	4	0	0
T45	0	2	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T138	0	4	0	0
T147	0	2	0	0
T157	0	4	0	0
T158	0	2	0	0
T159	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	34582	0	0
T9	963	154	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T41	0	92	0	0
T42	0	57	0	0
T44	0	44	0	0
T45	0	58	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T138	0	166	0	0
T147	0	33	0	0
T157	0	136	0	0
T158	0	73	0	0
T159	0	200	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511942	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2594	0	0
T9	963	88	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T41	0	83	0	0
T44	0	84	0	0
T45	0	42	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T138	0	193	0	0
T147	0	48	0	0
T149	0	5	0	0
T157	0	218	0	0
T158	0	42	0	0
T159	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	44	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T149	0	1	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4435183	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4436915	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	48	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	44	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T149	0	1	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	44	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T149	0	1	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	44	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T149	0	1	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2531	0	0
T9	963	85	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T41	0	80	0	0
T44	0	81	0	0
T45	0	40	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T138	0	191	0	0
T147	0	47	0	0
T149	0	4	0	0
T157	0	215	0	0
T158	0	40	0	0
T159	0	76	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1582	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	2	0	0
T9	0	2	0	0
T16	3046	4	0	0
T17	502	4	0	0
T18	403	0	0	0
T25	0	6	0	0
T52	19637	0	0	0
T62	0	2	0	0
T69	0	5	0	0
T71	0	4	0	0
T81	1774	0	0	0
T82	423	1	0	0
T118	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	24	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0