Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T42,T37,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T42,T37,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T42,T37,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T37,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T42,T37,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T40,T38
0	1	Covered	T42,T40
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T40,T38
0	1	Covered	T37,T40,T38
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T40,T38
1	-	Covered	T37,T40,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T42,T37,T40
DetectSt	168	Covered	T42,T37,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T37,T40,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T42,T37,T40
DebounceSt->IdleSt	163	Covered	T161,T90
DetectSt->IdleSt	186	Covered	T42,T40
DetectSt->StableSt	191	Covered	T37,T40,T38
IdleSt->DebounceSt	148	Covered	T42,T37,T40
StableSt->IdleSt	206	Covered	T37,T40,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T37,T40
0	1	Covered	T42,T37,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T37,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T37,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T37,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T161
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T37,T40
DetectSt	-	-	-	-	1	-	-	Covered	T42,T40
DetectSt	-	-	-	-	0	1	-	Covered	T37,T40,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T40,T38
StableSt	-	-	-	-	-	-	0	Covered	T37,T40,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	76	0	0
CntIncr_A	4968661	2462	0	0
CntNoWrap_A	4968661	4511958	0	0
DetectStDropOut_A	4968661	2	0	0
DetectedOut_A	4968661	2280	0	0
DetectedPulseOut_A	4968661	35	0	0
DisabledIdleSt_A	4968661	4498099	0	0
DisabledNoDetection_A	4968661	4499835	0	0
EnterDebounceSt_A	4968661	39	0	0
EnterDetectSt_A	4968661	37	0	0
EnterStableSt_A	4968661	35	0	0
PulseIsPulse_A	4968661	35	0	0
StayInStableSt	4968661	2226	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	76	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	2	0	0
T38	0	4	0	0
T40	0	4	0	0
T42	724	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	2	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	4	0	0
T157	0	2	0	0
T162	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2462	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	19	0	0
T38	0	190	0	0
T40	0	160	0	0
T42	724	57	0	0
T44	0	22	0	0
T45	0	58	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	74	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	40	0	0
T157	0	68	0	0
T162	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511958	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T40	0	1	0	0
T42	724	1	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T144	591	0	0	0
T145	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2280	0	0
T37	1908	18	0	0
T38	0	86	0	0
T40	2945	40	0	0
T44	0	118	0	0
T45	0	42	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T122	0	44	0	0
T148	0	175	0	0
T157	0	41	0	0
T162	0	73	0	0
T163	0	46	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	35	0	0
T37	1908	1	0	0
T38	0	2	0	0
T40	2945	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T122	0	1	0	0
T148	0	2	0	0
T157	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4498099	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4499835	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	39	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T40	0	2	0	0
T42	724	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	1	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	2	0	0
T157	0	1	0	0
T162	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	37	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T40	0	2	0	0
T42	724	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	1	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	2	0	0
T157	0	1	0	0
T162	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	35	0	0
T37	1908	1	0	0
T38	0	2	0	0
T40	2945	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T122	0	1	0	0
T148	0	2	0	0
T157	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	35	0	0
T37	1908	1	0	0
T38	0	2	0	0
T40	2945	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T122	0	1	0	0
T148	0	2	0	0
T157	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2226	0	0
T37	1908	17	0	0
T38	0	83	0	0
T40	2945	39	0	0
T44	0	116	0	0
T45	0	40	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T122	0	42	0	0
T148	0	172	0	0
T157	0	40	0	0
T162	0	71	0	0
T163	0	44	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	15	0	0
T37	1908	1	0	0
T38	0	1	0	0
T40	2945	1	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T91	0	1	0	0
T101	32404	0	0	0
T148	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0
T167	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T28,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T28,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T28,T42
1	0	Covered	T7,T1,T15
1	1	Covered	T9,T28,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T42,T43
0	1	Covered	T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T42,T43
0	1	Covered	T9,T42,T168
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T42,T43
1	-	Covered	T9,T42,T168

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T28,T42
DetectSt	168	Covered	T9,T42,T43
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T9,T42,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T42,T43
DebounceSt->IdleSt	163	Covered	T28,T169,T147
DetectSt->IdleSt	186	Covered	T91
DetectSt->StableSt	191	Covered	T9,T42,T43
IdleSt->DebounceSt	148	Covered	T9,T28,T42
StableSt->IdleSt	206	Covered	T9,T42,T168

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T28,T42
0	1	Covered	T9,T28,T42
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T42,T43
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T28,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T42,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T169,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T28,T42
DetectSt	-	-	-	-	1	-	-	Covered	T91
DetectSt	-	-	-	-	0	1	-	Covered	T9,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T42,T168
StableSt	-	-	-	-	-	-	0	Covered	T9,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	79	0	0
CntIncr_A	4968661	34157	0	0
CntNoWrap_A	4968661	4511955	0	0
DetectStDropOut_A	4968661	1	0	0
DetectedOut_A	4968661	2837	0	0
DetectedPulseOut_A	4968661	36	0	0
DisabledIdleSt_A	4968661	4438657	0	0
DisabledNoDetection_A	4968661	4440400	0	0
EnterDebounceSt_A	4968661	42	0	0
EnterDetectSt_A	4968661	37	0	0
EnterStableSt_A	4968661	36	0	0
PulseIsPulse_A	4968661	36	0	0
StayInStableSt	4968661	2786	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	4968661	1816	0	0
gen_low_level_sva.LowLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	79	0	0
T9	963	4	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T28	0	1	0	0
T31	769	0	0	0
T32	779	0	0	0
T42	0	4	0	0
T43	0	3	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T91	0	4	0	0
T132	0	2	0	0
T147	0	1	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	34157	0	0
T9	963	154	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T28	0	80	0	0
T31	769	0	0	0
T32	779	0	0	0
T42	0	114	0	0
T43	0	42	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T91	0	174	0	0
T132	0	64	0	0
T147	0	33	0	0
T168	0	83	0	0
T169	0	46	0	0
T170	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511955	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1	0	0
T91	1031	1	0	0
T96	773	0	0	0
T124	427	0	0	0
T125	1952	0	0	0
T126	402	0	0	0
T127	448	0	0	0
T128	402	0	0	0
T129	708	0	0	0
T130	492	0	0	0
T131	1103	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2837	0	0
T9	963	273	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T42	0	81	0	0
T43	0	95	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	1	0	0
T91	0	43	0	0
T132	0	39	0	0
T150	0	81	0	0
T161	0	273	0	0
T168	0	213	0	0
T170	0	169	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	36	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	1	0	0
T91	0	1	0	0
T132	0	1	0	0
T150	0	2	0	0
T161	0	3	0	0
T168	0	1	0	0
T170	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4438657	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4440400	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	42	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T28	0	1	0	0
T31	769	0	0	0
T32	779	0	0	0
T42	0	2	0	0
T43	0	2	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T91	0	2	0	0
T132	0	1	0	0
T147	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	37	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	1	0	0
T91	0	2	0	0
T132	0	1	0	0
T150	0	2	0	0
T161	0	3	0	0
T168	0	1	0	0
T170	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	36	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	1	0	0
T91	0	1	0	0
T132	0	1	0	0
T150	0	2	0	0
T161	0	3	0	0
T168	0	1	0	0
T170	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	36	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	1	0	0
T91	0	1	0	0
T132	0	1	0	0
T150	0	2	0	0
T161	0	3	0	0
T168	0	1	0	0
T170	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2786	0	0
T9	963	270	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T42	0	78	0	0
T43	0	93	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T91	0	42	0	0
T132	0	38	0	0
T150	0	79	0	0
T161	0	269	0	0
T168	0	212	0	0
T170	0	167	0	0
T171	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1816	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	2	0	0
T9	0	2	0	0
T16	3046	12	0	0
T17	502	5	0	0
T18	403	0	0	0
T25	0	4	0	0
T52	19637	0	0	0
T59	0	6	0	0
T62	0	2	0	0
T69	0	4	0	0
T81	1774	0	0	0
T82	423	2	0	0
T118	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	20	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T42	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T91	0	1	0	0
T92	0	1	0	0
T132	0	1	0	0
T150	0	2	0	0
T161	0	2	0	0
T168	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T14
1	1	Covered	T5,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T37,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T8,T37,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T37,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T45
1	0	Covered	T5,T1,T14
1	1	Covered	T8,T37,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T45,T46
0	1	Covered	T8,T162,T132
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T45,T46
0	1	Covered	T37,T45,T46
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T45,T46
1	-	Covered	T37,T45,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T37,T45
DetectSt	168	Covered	T8,T37,T45
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T37,T45,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T37,T45
DebounceSt->IdleSt	163	Covered	T43,T90,T174
DetectSt->IdleSt	186	Covered	T8,T162,T132
DetectSt->StableSt	191	Covered	T37,T45,T46
IdleSt->DebounceSt	148	Covered	T8,T37,T45
StableSt->IdleSt	206	Covered	T37,T45,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T37,T45
0	1	Covered	T8,T37,T45
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T37,T45
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T37,T45
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T37,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T174,T175
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T37,T45
DetectSt	-	-	-	-	1	-	-	Covered	T8,T162,T132
DetectSt	-	-	-	-	0	1	-	Covered	T37,T45,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T45,T46
StableSt	-	-	-	-	-	-	0	Covered	T37,T45,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	88	0	0
CntIncr_A	4968661	2446	0	0
CntNoWrap_A	4968661	4511946	0	0
DetectStDropOut_A	4968661	3	0	0
DetectedOut_A	4968661	3645	0	0
DetectedPulseOut_A	4968661	39	0	0
DisabledIdleSt_A	4968661	4499582	0	0
DisabledNoDetection_A	4968661	4501317	0	0
EnterDebounceSt_A	4968661	46	0	0
EnterDetectSt_A	4968661	42	0	0
EnterStableSt_A	4968661	39	0	0
PulseIsPulse_A	4968661	39	0	0
StayInStableSt	4968661	3587	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	88	0	0
T8	598	2	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	2	0	0
T147	0	2	0	0
T157	0	2	0	0
T162	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2446	0	0
T8	598	26	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	19	0	0
T39	0	80	0	0
T43	0	21	0	0
T45	0	58	0	0
T46	0	34	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	83	0	0
T147	0	33	0	0
T157	0	68	0	0
T162	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511946	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T132	0	1	0	0
T162	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3645	0	0
T37	1908	17	0	0
T39	0	312	0	0
T40	2945	0	0	0
T45	0	7	0	0
T46	0	42	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T138	0	44	0	0
T147	0	45	0	0
T157	0	108	0	0
T158	0	146	0	0
T162	0	72	0	0
T163	0	384	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	39	0	0
T37	1908	1	0	0
T39	0	1	0	0
T40	2945	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T138	0	1	0	0
T147	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4499582	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4501317	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	46	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	1	0	0
T147	0	1	0	0
T157	0	1	0	0
T162	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	42	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	1	0	0
T147	0	1	0	0
T157	0	1	0	0
T162	0	2	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	39	0	0
T37	1908	1	0	0
T39	0	1	0	0
T40	2945	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T138	0	1	0	0
T147	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	39	0	0
T37	1908	1	0	0
T39	0	1	0	0
T40	2945	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T138	0	1	0	0
T147	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3587	0	0
T37	1908	16	0	0
T39	0	310	0	0
T40	2945	0	0	0
T45	0	6	0	0
T46	0	41	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T138	0	43	0	0
T147	0	43	0	0
T157	0	107	0	0
T158	0	144	0	0
T162	0	70	0	0
T163	0	382	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	19	0	0
T37	1908	1	0	0
T40	2945	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T92	0	1	0	0
T101	32404	0	0	0
T138	0	1	0	0
T149	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0
T168	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T28,T37,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T28,T37,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T28,T37,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T30,T28,T37
1	0	Covered	T5,T7,T1
1	1	Covered	T28,T37,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T37,T40
0	1	Covered	T176
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T37,T40
0	1	Covered	T40,T148,T168
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T37,T40
1	-	Covered	T40,T148,T168

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T37,T40
DetectSt	168	Covered	T28,T37,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T28,T37,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T37,T40
DebounceSt->IdleSt	163	Covered	T90,T155
DetectSt->IdleSt	186	Covered	T176
DetectSt->StableSt	191	Covered	T28,T37,T40
IdleSt->DebounceSt	148	Covered	T28,T37,T40
StableSt->IdleSt	206	Covered	T28,T37,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T28,T37,T40
0	1	Covered	T28,T37,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T37,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T28,T37,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T37,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T155
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T37,T40
DetectSt	-	-	-	-	1	-	-	Covered	T176
DetectSt	-	-	-	-	0	1	-	Covered	T28,T37,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T148,T168
StableSt	-	-	-	-	-	-	0	Covered	T28,T37,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	56	0	0
CntIncr_A	4968661	33352	0	0
CntNoWrap_A	4968661	4511978	0	0
DetectStDropOut_A	4968661	1	0	0
DetectedOut_A	4968661	1700	0	0
DetectedPulseOut_A	4968661	26	0	0
DisabledIdleSt_A	4968661	4434494	0	0
DisabledNoDetection_A	4968661	4436224	0	0
EnterDebounceSt_A	4968661	29	0	0
EnterDetectSt_A	4968661	27	0	0
EnterStableSt_A	4968661	26	0	0
PulseIsPulse_A	4968661	26	0	0
StayInStableSt	4968661	1661	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	4968661	5265	0	0
gen_low_level_sva.LowLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	56	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T28	3195	2	0	0
T29	502	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	2	0	0
T40	0	4	0	0
T42	724	0	0	0
T43	0	2	0	0
T46	0	2	0	0
T77	1022	0	0	0
T78	435	0	0	0
T132	0	2	0	0
T139	0	2	0	0
T148	0	4	0	0
T150	0	2	0	0
T168	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	33352	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T28	3195	80	0	0
T29	502	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	19	0	0
T40	0	160	0	0
T42	724	0	0	0
T43	0	21	0	0
T46	0	34	0	0
T77	1022	0	0	0
T78	435	0	0	0
T132	0	64	0	0
T139	0	65	0	0
T148	0	40	0	0
T150	0	49	0	0
T168	0	166	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511978	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1	0	0
T176	3636	1	0	0
T177	522	0	0	0
T178	489	0	0	0
T179	21853	0	0	0
T180	731	0	0	0
T181	415	0	0	0
T182	526	0	0	0
T183	557	0	0	0
T184	421	0	0	0
T185	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1700	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T28	3195	48	0	0
T29	502	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	145	0	0
T40	0	287	0	0
T42	724	0	0	0
T43	0	161	0	0
T46	0	81	0	0
T77	1022	0	0	0
T78	435	0	0	0
T132	0	103	0	0
T139	0	190	0	0
T148	0	83	0	0
T150	0	41	0	0
T168	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	26	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T28	3195	1	0	0
T29	502	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T42	724	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T77	1022	0	0	0
T78	435	0	0	0
T132	0	1	0	0
T139	0	1	0	0
T148	0	2	0	0
T150	0	1	0	0
T168	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4434494	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4436224	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	29	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T28	3195	1	0	0
T29	502	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T42	724	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T77	1022	0	0	0
T78	435	0	0	0
T132	0	1	0	0
T139	0	1	0	0
T148	0	2	0	0
T150	0	1	0	0
T168	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	27	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T28	3195	1	0	0
T29	502	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T42	724	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T77	1022	0	0	0
T78	435	0	0	0
T132	0	1	0	0
T139	0	1	0	0
T148	0	2	0	0
T150	0	1	0	0
T168	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	26	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T28	3195	1	0	0
T29	502	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T42	724	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T77	1022	0	0	0
T78	435	0	0	0
T132	0	1	0	0
T139	0	1	0	0
T148	0	2	0	0
T150	0	1	0	0
T168	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	26	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T28	3195	1	0	0
T29	502	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T42	724	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T77	1022	0	0	0
T78	435	0	0	0
T132	0	1	0	0
T139	0	1	0	0
T148	0	2	0	0
T150	0	1	0	0
T168	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1661	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T28	3195	46	0	0
T29	502	0	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	143	0	0
T40	0	284	0	0
T42	724	0	0	0
T43	0	159	0	0
T46	0	79	0	0
T77	1022	0	0	0
T78	435	0	0	0
T132	0	102	0	0
T139	0	188	0	0
T148	0	80	0	0
T150	0	40	0	0
T168	0	1	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	5265	0	0
T1	14193	26	0	0
T2	10710	12	0	0
T3	0	14	0	0
T4	0	12	0	0
T5	5416	22	0	0
T6	405	0	0	0
T7	4404	0	0	0
T8	0	1	0	0
T14	5270	22	0	0
T15	2369	0	0	0
T16	3046	7	0	0
T17	502	4	0	0
T18	403	0	0	0
T52	0	10	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	12	0	0
T40	2945	1	0	0
T51	15751	0	0	0
T73	487	0	0	0
T83	505	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T132	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T161	0	1	0	0
T166	414	0	0	0
T168	0	2	0	0
T172	0	1	0	0
T186	0	1	0	0
T187	402	0	0	0
T188	8402	0	0	0
T189	311805	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T14
1	1	Covered	T5,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T9,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T8,T9,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T9,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T30
1	0	Covered	T5,T1,T14
1	1	Covered	T8,T9,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T30
0	1	Covered	T159,T155
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T30
0	1	Covered	T8,T42,T44
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T30
1	-	Covered	T8,T42,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T30
DetectSt	168	Covered	T8,T9,T30
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T8,T9,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T30
DebounceSt->IdleSt	163	Covered	T9,T160,T90
DetectSt->IdleSt	186	Covered	T159,T155
DetectSt->StableSt	191	Covered	T8,T9,T30
IdleSt->DebounceSt	148	Covered	T8,T9,T30
StableSt->IdleSt	206	Covered	T8,T28,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T30
0	1	Covered	T8,T9,T30
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T30
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T30
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T160
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T30
DetectSt	-	-	-	-	1	-	-	Covered	T159,T155
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T42,T44
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	89	0	0
CntIncr_A	4968661	2514	0	0
CntNoWrap_A	4968661	4511945	0	0
DetectStDropOut_A	4968661	2	0	0
DetectedOut_A	4968661	3660	0	0
DetectedPulseOut_A	4968661	41	0	0
DisabledIdleSt_A	4968661	4437166	0	0
DisabledNoDetection_A	4968661	4438905	0	0
EnterDebounceSt_A	4968661	46	0	0
EnterDetectSt_A	4968661	43	0	0
EnterStableSt_A	4968661	41	0	0
PulseIsPulse_A	4968661	41	0	0
StayInStableSt	4968661	3598	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	89	0	0
T8	598	2	0	0
T9	963	3	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T31	769	0	0	0
T39	0	2	0	0
T42	0	2	0	0
T44	0	4	0	0
T46	0	4	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	4	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2514	0	0
T8	598	26	0	0
T9	963	154	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T28	0	80	0	0
T30	0	41	0	0
T31	769	0	0	0
T39	0	80	0	0
T42	0	57	0	0
T44	0	44	0	0
T46	0	68	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	166	0	0
T169	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511945	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2	0	0
T112	9560	0	0	0
T155	0	1	0	0
T159	1210	1	0	0
T190	427	0	0	0
T191	524	0	0	0
T192	557	0	0	0
T193	409	0	0	0
T194	19540	0	0	0
T195	30713	0	0	0
T196	943	0	0	0
T197	19334	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3660	0	0
T8	598	69	0	0
T9	963	41	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T28	0	50	0	0
T30	0	38	0	0
T31	769	0	0	0
T39	0	182	0	0
T42	0	43	0	0
T44	0	86	0	0
T46	0	82	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	355	0	0
T169	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	41	0	0
T8	598	1	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T31	769	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	2	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	2	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4437166	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4438905	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	46	0	0
T8	598	1	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T31	769	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	2	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	2	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	43	0	0
T8	598	1	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T31	769	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	2	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	2	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	41	0	0
T8	598	1	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T31	769	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	2	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	2	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	41	0	0
T8	598	1	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T31	769	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	2	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	2	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3598	0	0
T8	598	68	0	0
T9	963	39	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T28	0	48	0	0
T30	0	36	0	0
T31	769	0	0	0
T39	0	181	0	0
T42	0	42	0	0
T44	0	83	0	0
T46	0	79	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	352	0	0
T169	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	19	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T138	0	1	0	0
T148	0	1	0	0
T159	0	1	0	0
T163	0	1	0	0
T198	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T42,T37,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T42,T37,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T42,T37,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T30,T28,T42
1	0	Covered	T5,T7,T1
1	1	Covered	T42,T37,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T42,T37,T40
0	1	Covered	T176
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T37,T40
0	1	Covered	T40,T46,T41
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T37,T40
1	-	Covered	T40,T46,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T42,T37,T40
DetectSt	168	Covered	T42,T37,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T42,T37,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T42,T37,T40
DebounceSt->IdleSt	163	Covered	T44,T146,T90
DetectSt->IdleSt	186	Covered	T176
DetectSt->StableSt	191	Covered	T42,T37,T40
IdleSt->DebounceSt	148	Covered	T42,T37,T40
StableSt->IdleSt	206	Covered	T37,T40,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T37,T40
0	1	Covered	T42,T37,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T37,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T37,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T37,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T146,T175
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T37,T40
DetectSt	-	-	-	-	1	-	-	Covered	T176
DetectSt	-	-	-	-	0	1	-	Covered	T42,T37,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T46,T41
StableSt	-	-	-	-	-	-	0	Covered	T42,T37,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	72	0	0
CntIncr_A	4968661	2095	0	0
CntNoWrap_A	4968661	4511962	0	0
DetectStDropOut_A	4968661	1	0	0
DetectedOut_A	4968661	2841	0	0
DetectedPulseOut_A	4968661	33	0	0
DisabledIdleSt_A	4968661	4433477	0	0
DisabledNoDetection_A	4968661	4435204	0	0
EnterDebounceSt_A	4968661	38	0	0
EnterDetectSt_A	4968661	34	0	0
EnterStableSt_A	4968661	33	0	0
PulseIsPulse_A	4968661	33	0	0
StayInStableSt	4968661	2791	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	4968661	4897	0	0
gen_low_level_sva.LowLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	72	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	4	0	0
T41	0	2	0	0
T42	724	2	0	0
T44	0	1	0	0
T46	0	2	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	2	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	2	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2095	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	19	0	0
T38	0	95	0	0
T40	0	160	0	0
T41	0	46	0	0
T42	724	57	0	0
T44	0	22	0	0
T46	0	34	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	74	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	20	0	0
T157	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511962	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1	0	0
T176	3636	1	0	0
T177	522	0	0	0
T178	489	0	0	0
T179	21853	0	0	0
T180	731	0	0	0
T181	415	0	0	0
T182	526	0	0	0
T183	557	0	0	0
T184	421	0	0	0
T185	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2841	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	82	0	0
T38	0	168	0	0
T40	0	161	0	0
T41	0	40	0	0
T42	724	96	0	0
T46	0	7	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	44	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	2	0	0
T157	0	109	0	0
T158	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	33	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	724	1	0	0
T46	0	1	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	1	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4433477	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4435204	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	38	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	724	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	1	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	1	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	34	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	724	1	0	0
T46	0	1	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	1	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	33	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	724	1	0	0
T46	0	1	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	1	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	33	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	724	1	0	0
T46	0	1	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	1	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2791	0	0
T24	592	0	0	0
T26	498	0	0	0
T27	197659	0	0	0
T29	502	0	0	0
T37	0	80	0	0
T38	0	166	0	0
T40	0	158	0	0
T41	0	39	0	0
T42	724	94	0	0
T46	0	6	0	0
T72	493	0	0	0
T79	502	0	0	0
T80	504	0	0	0
T122	0	42	0	0
T144	591	0	0	0
T145	423	0	0	0
T148	0	1	0	0
T157	0	108	0	0
T158	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4897	0	0
T1	14193	26	0	0
T2	10710	14	0	0
T3	0	9	0	0
T4	0	11	0	0
T5	5416	29	0	0
T6	405	0	0	0
T7	4404	0	0	0
T8	0	1	0	0
T14	5270	32	0	0
T15	2369	0	0	0
T16	3046	4	0	0
T17	502	3	0	0
T18	403	0	0	0
T52	0	11	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	15	0	0
T40	2945	1	0	0
T41	0	1	0	0
T46	0	1	0	0
T51	15751	0	0	0
T73	487	0	0	0
T83	505	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T166	414	0	0	0
T167	0	1	0	0
T187	402	0	0	0
T188	8402	0	0	0
T189	311805	0	0	0
T199	0	1	0	0