Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T14
1	1	Covered	T5,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T37,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T8,T37,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T37,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T42,T37
1	0	Covered	T5,T1,T14
1	1	Covered	T8,T37,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T37,T40
0	1	Covered	T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T37,T40
0	1	Covered	T37,T40,T139
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T37,T40
1	-	Covered	T37,T40,T139

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T37,T40
DetectSt	168	Covered	T8,T37,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T8,T37,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T37,T40
DebounceSt->IdleSt	163	Covered	T43,T90
DetectSt->IdleSt	186	Covered	T151
DetectSt->StableSt	191	Covered	T8,T37,T40
IdleSt->DebounceSt	148	Covered	T8,T37,T40
StableSt->IdleSt	206	Covered	T37,T40,T139

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T37,T40
0	1	Covered	T8,T37,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T37,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T37,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T37,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T43
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T37,T40
DetectSt	-	-	-	-	1	-	-	Covered	T151
DetectSt	-	-	-	-	0	1	-	Covered	T8,T37,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T40,T139
StableSt	-	-	-	-	-	-	0	Covered	T8,T37,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	92	0	0
CntIncr_A	4968661	2696	0	0
CntNoWrap_A	4968661	4511942	0	0
DetectStDropOut_A	4968661	1	0	0
DetectedOut_A	4968661	3898	0	0
DetectedPulseOut_A	4968661	44	0	0
DisabledIdleSt_A	4968661	4435836	0	0
DisabledNoDetection_A	4968661	4437572	0	0
EnterDebounceSt_A	4968661	47	0	0
EnterDetectSt_A	4968661	45	0	0
EnterStableSt_A	4968661	44	0	0
PulseIsPulse_A	4968661	44	0	0
StayInStableSt	4968661	3834	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	92	0	0
T8	598	2	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	4	0	0
T43	0	3	0	0
T46	0	2	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T139	0	4	0	0
T162	0	2	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2696	0	0
T8	598	26	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	19	0	0
T38	0	95	0	0
T39	0	80	0	0
T40	0	160	0	0
T43	0	42	0	0
T46	0	34	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T139	0	130	0	0
T162	0	14	0	0
T169	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511942	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1	0	0
T151	536	1	0	0
T152	832	0	0	0
T171	754	0	0	0
T200	726	0	0	0
T201	1877	0	0	0
T202	494	0	0	0
T203	761	0	0	0
T204	738	0	0	0
T205	443	0	0	0
T206	758	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3898	0	0
T8	598	163	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	43	0	0
T38	0	455	0	0
T39	0	430	0	0
T40	0	85	0	0
T43	0	1	0	0
T46	0	211	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T139	0	50	0	0
T162	0	47	0	0
T169	0	92	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	44	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T139	0	2	0	0
T162	0	1	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4435836	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4437572	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	47	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T139	0	2	0	0
T162	0	1	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	45	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T139	0	2	0	0
T162	0	1	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	44	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T139	0	2	0	0
T162	0	1	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	44	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T139	0	2	0	0
T162	0	1	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3834	0	0
T8	598	161	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	42	0	0
T38	0	453	0	0
T39	0	428	0	0
T40	0	82	0	0
T46	0	209	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T139	0	47	0	0
T162	0	45	0	0
T163	0	52	0	0
T169	0	90	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	23	0	0
T37	1908	1	0	0
T40	2945	1	0	0
T43	0	1	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T139	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0
T158	0	1	0	0
T163	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0
T168	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T37,T40,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T37,T40,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T37,T40,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T30,T42
1	0	Covered	T5,T7,T1
1	1	Covered	T37,T40,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T40,T41
0	1	Covered	T92,T153
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T40,T41
0	1	Covered	T40,T41,T163
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T40,T41
1	-	Covered	T40,T41,T163

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T37,T40,T41
DetectSt	168	Covered	T37,T40,T41
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T37,T40,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T37,T40,T41
DebounceSt->IdleSt	163	Covered	T90,T155
DetectSt->IdleSt	186	Covered	T92,T153
DetectSt->StableSt	191	Covered	T37,T40,T41
IdleSt->DebounceSt	148	Covered	T37,T40,T41
StableSt->IdleSt	206	Covered	T37,T40,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T37,T40,T41
0	1	Covered	T37,T40,T41
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T37,T40,T41
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T37,T40,T41
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T37,T40,T41
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T37,T40,T41
DetectSt	-	-	-	-	1	-	-	Covered	T92,T153
DetectSt	-	-	-	-	0	1	-	Covered	T37,T40,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T41,T163
StableSt	-	-	-	-	-	-	0	Covered	T37,T40,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	37	0	0
CntIncr_A	4968661	1048	0	0
CntNoWrap_A	4968661	4511997	0	0
DetectStDropOut_A	4968661	2	0	0
DetectedOut_A	4968661	1245	0	0
DetectedPulseOut_A	4968661	16	0	0
DisabledIdleSt_A	4968661	4436578	0	0
DisabledNoDetection_A	4968661	4438314	0	0
EnterDebounceSt_A	4968661	20	0	0
EnterDetectSt_A	4968661	18	0	0
EnterStableSt_A	4968661	16	0	0
PulseIsPulse_A	4968661	16	0	0
StayInStableSt	4968661	1221	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	4968661	4899	0	0
gen_low_level_sva.LowLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	7	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	37	0	0
T37	1908	2	0	0
T40	2945	2	0	0
T41	0	2	0	0
T54	2601	0	0	0
T63	0	2	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T147	0	2	0	0
T149	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0
T161	0	2	0	0
T163	0	2	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1048	0	0
T37	1908	19	0	0
T40	2945	80	0	0
T41	0	46	0	0
T54	2601	0	0	0
T63	0	32	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T147	0	33	0	0
T149	0	34	0	0
T158	0	73	0	0
T159	0	100	0	0
T161	0	73	0	0
T163	0	95	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511997	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2	0	0
T92	3186	1	0	0
T153	0	1	0	0
T160	606	0	0	0
T208	522	0	0	0
T209	7549	0	0	0
T210	440	0	0	0
T211	501	0	0	0
T212	11787	0	0	0
T213	9806	0	0	0
T214	13449	0	0	0
T215	16611	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1245	0	0
T37	1908	81	0	0
T40	2945	243	0	0
T41	0	87	0	0
T54	2601	0	0	0
T63	0	3	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T147	0	40	0	0
T149	0	43	0	0
T158	0	43	0	0
T159	0	41	0	0
T161	0	49	0	0
T163	0	138	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	16	0	0
T37	1908	1	0	0
T40	2945	1	0	0
T41	0	1	0	0
T54	2601	0	0	0
T63	0	1	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T147	0	1	0	0
T149	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T161	0	1	0	0
T163	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4436578	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4438314	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	20	0	0
T37	1908	1	0	0
T40	2945	1	0	0
T41	0	1	0	0
T54	2601	0	0	0
T63	0	1	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T147	0	1	0	0
T149	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T161	0	1	0	0
T163	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	18	0	0
T37	1908	1	0	0
T40	2945	1	0	0
T41	0	1	0	0
T54	2601	0	0	0
T63	0	1	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T147	0	1	0	0
T149	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T161	0	1	0	0
T163	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	16	0	0
T37	1908	1	0	0
T40	2945	1	0	0
T41	0	1	0	0
T54	2601	0	0	0
T63	0	1	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T147	0	1	0	0
T149	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T161	0	1	0	0
T163	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	16	0	0
T37	1908	1	0	0
T40	2945	1	0	0
T41	0	1	0	0
T54	2601	0	0	0
T63	0	1	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T147	0	1	0	0
T149	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T161	0	1	0	0
T163	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1221	0	0
T37	1908	79	0	0
T40	2945	242	0	0
T41	0	86	0	0
T54	2601	0	0	0
T63	0	2	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T147	0	38	0	0
T149	0	42	0	0
T158	0	41	0	0
T159	0	40	0	0
T161	0	47	0	0
T163	0	137	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4899	0	0
T1	14193	27	0	0
T2	10710	11	0	0
T3	0	15	0	0
T4	0	11	0	0
T5	5416	29	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	23	0	0
T15	2369	0	0	0
T16	3046	6	0	0
T17	502	4	0	0
T18	403	0	0	0
T52	0	9	0	0
T82	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	7	0	0
T40	2945	1	0	0
T41	0	1	0	0
T51	15751	0	0	0
T73	487	0	0	0
T83	505	0	0	0
T89	6434	0	0	0
T94	0	1	0	0
T101	32404	0	0	0
T149	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T163	0	1	0	0
T166	414	0	0	0
T187	402	0	0	0
T188	8402	0	0	0
T189	311805	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T14
1	1	Covered	T5,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T30,T40,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T30,T40,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T30,T40,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T30,T28,T40
1	0	Covered	T5,T1,T14
1	1	Covered	T30,T40,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T40,T38
0	1	Covered	T155
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T40,T38
0	1	Covered	T40,T38,T39
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T40,T38
1	-	Covered	T40,T38,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T30,T40,T38
DetectSt	168	Covered	T30,T40,T38
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T30,T40,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T40,T38
DebounceSt->IdleSt	163	Covered	T169,T152,T90
DetectSt->IdleSt	186	Covered	T155
DetectSt->StableSt	191	Covered	T30,T40,T38
IdleSt->DebounceSt	148	Covered	T30,T40,T38
StableSt->IdleSt	206	Covered	T40,T38,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T30,T40,T38
0	1	Covered	T30,T40,T38
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T40,T38
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T30,T40,T38
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T40,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T169,T152,T177
DebounceSt	-	0	0	-	-	-	-	Covered	T30,T40,T38
DetectSt	-	-	-	-	1	-	-	Covered	T155
DetectSt	-	-	-	-	0	1	-	Covered	T30,T40,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T38,T39
StableSt	-	-	-	-	-	-	0	Covered	T30,T40,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	86	0	0
CntIncr_A	4968661	2649	0	0
CntNoWrap_A	4968661	4511948	0	0
DetectStDropOut_A	4968661	1	0	0
DetectedOut_A	4968661	3379	0	0
DetectedPulseOut_A	4968661	40	0	0
DisabledIdleSt_A	4968661	4499209	0	0
DisabledNoDetection_A	4968661	4500943	0	0
EnterDebounceSt_A	4968661	45	0	0
EnterDetectSt_A	4968661	41	0	0
EnterStableSt_A	4968661	40	0	0
PulseIsPulse_A	4968661	40	0	0
StayInStableSt	4968661	3320	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	86	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	0	0	0
T30	545	2	0	0
T33	609	0	0	0
T36	1188	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	4	0	0
T42	724	0	0	0
T44	0	2	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	4	0	0
T147	0	2	0	0
T157	0	2	0	0
T169	0	1	0	0
T216	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2649	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	0	0	0
T30	545	41	0	0
T33	609	0	0	0
T36	1188	0	0	0
T38	0	95	0	0
T39	0	80	0	0
T40	0	160	0	0
T42	724	0	0	0
T44	0	22	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	166	0	0
T147	0	33	0	0
T157	0	68	0	0
T169	0	46	0	0
T216	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511948	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1	0	0
T155	3423	1	0	0
T217	23309	0	0	0
T218	2007	0	0	0
T219	414	0	0	0
T220	680	0	0	0
T221	521	0	0	0
T222	523	0	0	0
T223	558	0	0	0
T224	7646	0	0	0
T225	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3379	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	0	0	0
T30	545	38	0	0
T33	609	0	0	0
T36	1188	0	0	0
T38	0	168	0	0
T39	0	61	0	0
T40	0	86	0	0
T42	724	0	0	0
T44	0	118	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	355	0	0
T147	0	89	0	0
T157	0	173	0	0
T158	0	29	0	0
T216	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	40	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	0	0	0
T30	545	1	0	0
T33	609	0	0	0
T36	1188	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	724	0	0	0
T44	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T216	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4499209	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4500943	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	45	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	0	0	0
T30	545	1	0	0
T33	609	0	0	0
T36	1188	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	724	0	0	0
T44	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T157	0	1	0	0
T169	0	1	0	0
T216	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	41	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	0	0	0
T30	545	1	0	0
T33	609	0	0	0
T36	1188	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	724	0	0	0
T44	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T216	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	40	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	0	0	0
T30	545	1	0	0
T33	609	0	0	0
T36	1188	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	724	0	0	0
T44	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T216	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	40	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	0	0	0
T30	545	1	0	0
T33	609	0	0	0
T36	1188	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	724	0	0	0
T44	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T216	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3320	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	0	0	0
T30	545	36	0	0
T33	609	0	0	0
T36	1188	0	0	0
T38	0	167	0	0
T39	0	60	0	0
T40	0	84	0	0
T42	724	0	0	0
T44	0	116	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	353	0	0
T147	0	88	0	0
T157	0	172	0	0
T158	0	28	0	0
T216	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	20	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	2945	2	0	0
T51	15751	0	0	0
T73	487	0	0	0
T83	505	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T149	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T166	414	0	0	0
T170	0	1	0	0
T171	0	1	0	0
T187	402	0	0	0
T188	8402	0	0	0
T189	311805	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T30,T37
1	0	Covered	T5,T7,T1
1	1	Covered	T9,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T38,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T38,T39
0	1	Covered	T9,T155,T153
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T38,T39
1	-	Covered	T9,T155,T153

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T38,T39
DetectSt	168	Covered	T9,T38,T39
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T9,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T38,T39
DebounceSt->IdleSt	163	Covered	T90
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T38,T39
IdleSt->DebounceSt	148	Covered	T9,T38,T39
StableSt->IdleSt	206	Covered	T9,T63,T186

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T38,T39
0	1	Covered	T9,T38,T39
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T38,T39
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T38,T39
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T38,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T63,T155
StableSt	-	-	-	-	-	-	0	Covered	T9,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	43	0	0
CntIncr_A	4968661	1408	0	0
CntNoWrap_A	4968661	4511991	0	0
DetectStDropOut_A	4968661	0	0	0
DetectedOut_A	4968661	1899	0	0
DetectedPulseOut_A	4968661	21	0	0
DisabledIdleSt_A	4968661	4437053	0	0
DisabledNoDetection_A	4968661	4438792	0	0
EnterDebounceSt_A	4968661	22	0	0
EnterDetectSt_A	4968661	21	0	0
EnterStableSt_A	4968661	21	0	0
PulseIsPulse_A	4968661	21	0	0
StayInStableSt	4968661	1862	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	4968661	4972	0	0
gen_low_level_sva.LowLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	4	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	43	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T43	0	2	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T168	0	2	0	0
T169	0	2	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1408	0	0
T9	963	77	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T38	0	95	0	0
T39	0	80	0	0
T43	0	21	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	32	0	0
T157	0	68	0	0
T158	0	73	0	0
T168	0	83	0	0
T169	0	46	0	0
T170	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511991	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1899	0	0
T9	963	35	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T38	0	43	0	0
T39	0	50	0	0
T43	0	73	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	3	0	0
T157	0	116	0	0
T158	0	42	0	0
T168	0	132	0	0
T169	0	45	0	0
T170	0	49	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	21	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4437053	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4438792	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	22	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	21	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	21	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	21	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1862	0	0
T9	963	34	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T38	0	41	0	0
T39	0	48	0	0
T43	0	71	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T63	0	2	0	0
T157	0	114	0	0
T158	0	40	0	0
T168	0	130	0	0
T169	0	43	0	0
T170	0	47	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4972	0	0
T1	14193	35	0	0
T2	10710	14	0	0
T3	0	11	0	0
T4	0	10	0	0
T5	5416	28	0	0
T6	405	0	0	0
T7	4404	0	0	0
T8	0	1	0	0
T14	5270	32	0	0
T15	2369	0	0	0
T16	3046	6	0	0
T17	502	5	0	0
T18	403	0	0	0
T52	0	13	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T153	0	1	0	0
T155	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T14
1	1	Covered	T5,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T30,T28,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T30,T28,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T30,T28,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T30,T28,T37
1	0	Covered	T5,T1,T14
1	1	Covered	T30,T28,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T28,T37
0	1	Covered	T41,T155
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T28,T37
0	1	Covered	T37,T40,T41
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T28,T37
1	-	Covered	T37,T40,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T30,T28,T37
DetectSt	168	Covered	T30,T28,T37
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T30,T28,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T28,T37
DebounceSt->IdleSt	163	Covered	T44,T186,T90
DetectSt->IdleSt	186	Covered	T41,T155
DetectSt->StableSt	191	Covered	T30,T28,T37
IdleSt->DebounceSt	148	Covered	T30,T28,T37
StableSt->IdleSt	206	Covered	T28,T37,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T30,T28,T37
0	1	Covered	T30,T28,T37
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T28,T37
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T30,T28,T37
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T28,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T186
DebounceSt	-	0	0	-	-	-	-	Covered	T30,T28,T37
DetectSt	-	-	-	-	1	-	-	Covered	T41,T155
DetectSt	-	-	-	-	0	1	-	Covered	T30,T28,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T40,T41
StableSt	-	-	-	-	-	-	0	Covered	T30,T28,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	101	0	0
CntIncr_A	4968661	3089	0	0
CntNoWrap_A	4968661	4511933	0	0
DetectStDropOut_A	4968661	2	0	0
DetectedOut_A	4968661	5093	0	0
DetectedPulseOut_A	4968661	47	0	0
DisabledIdleSt_A	4968661	4432317	0	0
DisabledNoDetection_A	4968661	4434044	0	0
EnterDebounceSt_A	4968661	52	0	0
EnterDetectSt_A	4968661	49	0	0
EnterStableSt_A	4968661	47	0	0
PulseIsPulse_A	4968661	47	0	0
StayInStableSt	4968661	5024	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	101	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	2	0	0
T30	545	2	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	4	0	0
T41	0	4	0	0
T42	724	0	0	0
T44	0	1	0	0
T45	0	2	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	4	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3089	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	80	0	0
T30	545	41	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	19	0	0
T39	0	80	0	0
T40	0	160	0	0
T41	0	92	0	0
T42	724	0	0	0
T44	0	22	0	0
T45	0	58	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	166	0	0
T169	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511933	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2	0	0
T41	2133	1	0	0
T58	749	0	0	0
T65	139214	0	0	0
T66	1099	0	0	0
T104	9537	0	0	0
T155	0	1	0	0
T226	1819	0	0	0
T227	491	0	0	0
T228	1996	0	0	0
T229	424	0	0	0
T230	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	5093	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	47	0	0
T30	545	95	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	80	0	0
T39	0	313	0	0
T40	0	448	0	0
T41	0	18	0	0
T42	724	0	0	0
T45	0	42	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	213	0	0
T147	0	89	0	0
T169	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	47	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	1	0	0
T30	545	1	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	724	0	0	0
T45	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4432317	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4434044	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	52	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	1	0	0
T30	545	1	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	724	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	2	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	49	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	1	0	0
T30	545	1	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	724	0	0	0
T45	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	47	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	1	0	0
T30	545	1	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	724	0	0	0
T45	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	47	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	1	0	0
T30	545	1	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	724	0	0	0
T45	0	1	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	2	0	0
T147	0	1	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	5024	0	0
T23	538	0	0	0
T26	498	0	0	0
T28	3195	45	0	0
T30	545	93	0	0
T33	609	0	0	0
T36	1188	0	0	0
T37	0	79	0	0
T39	0	311	0	0
T40	0	445	0	0
T41	0	17	0	0
T42	724	0	0	0
T43	0	130	0	0
T45	0	40	0	0
T76	5069	0	0	0
T77	1022	0	0	0
T78	435	0	0	0
T138	0	210	0	0
T147	0	88	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	24	0	0
T37	1908	1	0	0
T40	2945	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T54	2601	0	0	0
T83	505	0	0	0
T85	5569	0	0	0
T89	6434	0	0	0
T91	0	1	0	0
T101	32404	0	0	0
T122	0	1	0	0
T138	0	1	0	0
T147	0	1	0	0
T159	0	1	0	0
T164	402	0	0	0
T165	402	0	0	0
T166	414	0	0	0
T169	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T9,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T8,T9,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T9,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T30
1	0	Covered	T5,T7,T1
1	1	Covered	T8,T9,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T37
0	1	Covered	T40,T153
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T37
0	1	Covered	T8,T46,T43
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T37
1	-	Covered	T8,T46,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T37
DetectSt	168	Covered	T8,T9,T37
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T8,T9,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T37
DebounceSt->IdleSt	163	Covered	T90
DetectSt->IdleSt	186	Covered	T40,T153
DetectSt->StableSt	191	Covered	T8,T9,T37
IdleSt->DebounceSt	148	Covered	T8,T9,T37
StableSt->IdleSt	206	Covered	T8,T37,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T37
0	1	Covered	T8,T9,T37
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T37
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T37
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T90
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T37
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T37
DetectSt	-	-	-	-	1	-	-	Covered	T40,T153
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T46,T43
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	47	0	0
CntIncr_A	4968661	1362	0	0
CntNoWrap_A	4968661	4511987	0	0
DetectStDropOut_A	4968661	2	0	0
DetectedOut_A	4968661	2109	0	0
DetectedPulseOut_A	4968661	21	0	0
DisabledIdleSt_A	4968661	4499305	0	0
DisabledNoDetection_A	4968661	4501042	0	0
EnterDebounceSt_A	4968661	24	0	0
EnterDetectSt_A	4968661	23	0	0
EnterStableSt_A	4968661	21	0	0
PulseIsPulse_A	4968661	21	0	0
StayInStableSt	4968661	2075	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	4968661	5379	0	0
gen_low_level_sva.LowLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	7	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	47	0	0
T8	598	2	0	0
T9	963	2	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	2	0	0
T40	0	2	0	0
T43	0	2	0	0
T46	0	2	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	2	0	0
T122	0	2	0	0
T147	0	2	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1362	0	0
T8	598	26	0	0
T9	963	77	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	19	0	0
T40	0	80	0	0
T43	0	21	0	0
T46	0	34	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	87	0	0
T122	0	74	0	0
T147	0	33	0	0
T159	0	100	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511987	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2	0	0
T40	2945	1	0	0
T51	15751	0	0	0
T73	487	0	0	0
T83	505	0	0	0
T89	6434	0	0	0
T101	32404	0	0	0
T153	0	1	0	0
T166	414	0	0	0
T187	402	0	0	0
T188	8402	0	0	0
T189	311805	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2109	0	0
T8	598	70	0	0
T9	963	398	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	82	0	0
T43	0	1	0	0
T46	0	8	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	97	0	0
T122	0	119	0	0
T132	0	103	0	0
T147	0	40	0	0
T159	0	283	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	21	0	0
T8	598	1	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	1	0	0
T122	0	1	0	0
T132	0	1	0	0
T147	0	1	0	0
T159	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4499305	0	0
T1	14193	13790	0	0
T2	10710	10305	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4501042	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	24	0	0
T8	598	1	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	1	0	0
T122	0	1	0	0
T147	0	1	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	23	0	0
T8	598	1	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	1	0	0
T122	0	1	0	0
T147	0	1	0	0
T159	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	21	0	0
T8	598	1	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	1	0	0
T122	0	1	0	0
T132	0	1	0	0
T147	0	1	0	0
T159	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	21	0	0
T8	598	1	0	0
T9	963	1	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	1	0	0
T122	0	1	0	0
T132	0	1	0	0
T147	0	1	0	0
T159	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2075	0	0
T8	598	69	0	0
T9	963	396	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T37	0	80	0	0
T46	0	7	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T91	0	95	0	0
T122	0	117	0	0
T132	0	101	0	0
T147	0	38	0	0
T149	0	159	0	0
T159	0	281	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	5379	0	0
T1	14193	26	0	0
T2	10710	10	0	0
T3	0	10	0	0
T4	0	10	0	0
T5	5416	28	0	0
T6	405	0	0	0
T7	4404	0	0	0
T8	0	1	0	0
T14	5270	22	0	0
T15	2369	0	0	0
T16	3046	10	0	0
T17	502	5	0	0
T18	403	0	0	0
T52	0	11	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	7	0	0
T8	598	1	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T31	769	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	469	0	0	0
T52	19637	0	0	0
T59	668	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T146	0	1	0	0
T154	0	1	0	0
T160	0	1	0	0
T199	0	1	0	0