Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T1,T48,T50
1	1	Covered	T5,T1,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T14
0	1	Covered	T5,T14,T76
1	0	Covered	T1,T50,T51

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T47,T48,T49
0	1	Covered	T48,T49,T86
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T47,T48,T49
1	-	Covered	T48,T49,T86

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T1,T14
DetectSt	168	Covered	T5,T1,T14
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T47,T48,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T1,T14
DebounceSt->IdleSt	163	Covered	T98,T63,T231
DetectSt->IdleSt	186	Covered	T5,T1,T14
DetectSt->StableSt	191	Covered	T47,T48,T49
IdleSt->DebounceSt	148	Covered	T5,T1,T14
StableSt->IdleSt	206	Covered	T48,T49,T86

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T14
0	1	Covered	T5,T1,T14
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T14
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T1,T14
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T1,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T98,T63,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T1,T14
DetectSt	-	-	-	-	1	-	-	Covered	T5,T1,T14
DetectSt	-	-	-	-	0	1	-	Covered	T47,T48,T49
DetectSt	-	-	-	-	0	0	-	Covered	T5,T1,T14
StableSt	-	-	-	-	-	-	1	Covered	T48,T49,T86
StableSt	-	-	-	-	-	-	0	Covered	T47,T48,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	2903	0	0
CntIncr_A	4968661	104044	0	0
CntNoWrap_A	4968661	4509131	0	0
DetectStDropOut_A	4968661	240	0	0
DetectedOut_A	4968661	99359	0	0
DetectedPulseOut_A	4968661	1030	0	0
DisabledIdleSt_A	4968661	4024468	0	0
DisabledNoDetection_A	4968661	4026006	0	0
EnterDebounceSt_A	4968661	1463	0	0
EnterDetectSt_A	4968661	1441	0	0
EnterStableSt_A	4968661	1030	0	0
PulseIsPulse_A	4968661	1030	0	0
StayInStableSt	4968661	98184	0	0
gen_high_event_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	885	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2903	0	0
T1	14193	20	0	0
T2	10710	0	0	0
T5	5416	32	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	12	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T47	0	2	0	0
T48	0	12	0	0
T49	0	20	0	0
T50	0	24	0	0
T51	0	50	0	0
T76	0	52	0	0
T85	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	104044	0	0
T1	14193	1568	0	0
T2	10710	0	0	0
T5	5416	889	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	314	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T47	0	21	0	0
T48	0	300	0	0
T49	0	560	0	0
T50	0	969	0	0
T51	0	1646	0	0
T76	0	1283	0	0
T85	0	760	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4509131	0	0
T1	14193	13770	0	0
T2	10710	10305	0	0
T5	5416	4983	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4857	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	240	0	0
T1	14193	0	0	0
T2	10710	0	0	0
T5	5416	16	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	6	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T76	0	26	0	0
T85	0	13	0	0
T107	0	10	0	0
T108	0	13	0	0
T109	0	22	0	0
T110	0	4	0	0
T112	0	4	0	0
T113	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	99359	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T47	469	44	0	0
T48	0	432	0	0
T49	0	845	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T86	0	1292	0	0
T232	0	126	0	0
T233	0	1014	0	0
T234	0	2779	0	0
T235	0	2479	0	0
T236	0	800	0	0
T237	0	1081	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1030	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T47	469	1	0	0
T48	0	6	0	0
T49	0	10	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T86	0	32	0	0
T232	0	5	0	0
T233	0	8	0	0
T234	0	11	0	0
T235	0	30	0	0
T236	0	14	0	0
T237	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4024468	0	0
T1	14193	5774	0	0
T2	10710	10305	0	0
T5	5416	2015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	2014	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4026006	0	0
T1	14193	5775	0	0
T2	10710	10308	0	0
T5	5416	2015	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	2014	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1463	0	0
T1	14193	10	0	0
T2	10710	0	0	0
T5	5416	16	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	6	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T47	0	1	0	0
T48	0	6	0	0
T49	0	10	0	0
T50	0	12	0	0
T51	0	25	0	0
T76	0	26	0	0
T85	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1441	0	0
T1	14193	10	0	0
T2	10710	0	0	0
T5	5416	16	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	6	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T47	0	1	0	0
T48	0	6	0	0
T49	0	10	0	0
T50	0	12	0	0
T51	0	25	0	0
T76	0	26	0	0
T85	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1030	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T47	469	1	0	0
T48	0	6	0	0
T49	0	10	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T86	0	32	0	0
T232	0	5	0	0
T233	0	8	0	0
T234	0	11	0	0
T235	0	30	0	0
T236	0	14	0	0
T237	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1030	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T47	469	1	0	0
T48	0	6	0	0
T49	0	10	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T86	0	32	0	0
T232	0	5	0	0
T233	0	8	0	0
T234	0	11	0	0
T235	0	30	0	0
T236	0	14	0	0
T237	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	98184	0	0
T9	963	0	0	0
T10	36866	0	0	0
T11	12460	0	0	0
T12	1232	0	0	0
T31	769	0	0	0
T32	779	0	0	0
T47	469	42	0	0
T48	0	426	0	0
T49	0	833	0	0
T59	668	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T86	0	1260	0	0
T232	0	121	0	0
T233	0	1005	0	0
T234	0	2762	0	0
T235	0	2448	0	0
T236	0	784	0	0
T237	0	1058	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	885	0	0
T23	538	0	0	0
T25	492	0	0	0
T30	545	0	0	0
T48	15560	6	0	0
T49	0	8	0	0
T50	12242	0	0	0
T69	436	0	0	0
T70	731	0	0	0
T71	422	0	0	0
T76	5069	0	0	0
T86	0	32	0	0
T118	422	0	0	0
T232	0	5	0	0
T233	0	7	0	0
T234	0	5	0	0
T235	0	29	0	0
T236	0	12	0	0
T237	0	23	0	0
T238	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T5,T7,T1
1	1	Covered	T2,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T11,T105,T106
1	0	Covered	T63,T90

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T90

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T4
DetectSt	168	Covered	T2,T3,T4
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T4
DebounceSt->IdleSt	163	Covered	T47,T13,T89
DetectSt->IdleSt	186	Covered	T11,T105,T106
DetectSt->StableSt	191	Covered	T2,T3,T4
IdleSt->DebounceSt	148	Covered	T2,T3,T4
StableSt->IdleSt	206	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T13,T89
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T11,T105,T106
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	876	0	0
CntIncr_A	4968661	42471	0	0
CntNoWrap_A	4968661	4511158	0	0
DetectStDropOut_A	4968661	41	0	0
DetectedOut_A	4968661	18747	0	0
DetectedPulseOut_A	4968661	371	0	0
DisabledIdleSt_A	4968661	4154725	0	0
DisabledNoDetection_A	4968661	4155925	0	0
EnterDebounceSt_A	4968661	463	0	0
EnterDetectSt_A	4968661	415	0	0
EnterStableSt_A	4968661	371	0	0
PulseIsPulse_A	4968661	371	0	0
StayInStableSt	4968661	18310	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	303	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	876	0	0
T2	10710	4	0	0
T3	23340	6	0	0
T4	17753	6	0	0
T8	598	0	0	0
T9	963	0	0	0
T10	0	16	0	0
T11	0	24	0	0
T13	0	7	0	0
T31	769	0	0	0
T47	469	1	0	0
T52	19637	20	0	0
T81	1774	0	0	0
T82	423	0	0	0
T89	0	21	0	0
T101	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	42471	0	0
T2	10710	270	0	0
T3	23340	387	0	0
T4	17753	516	0	0
T8	598	0	0	0
T9	963	0	0	0
T10	0	776	0	0
T11	0	647	0	0
T13	0	178	0	0
T31	769	0	0	0
T47	469	20	0	0
T52	19637	1390	0	0
T81	1774	0	0	0
T82	423	0	0	0
T89	0	1048	0	0
T101	0	405	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511158	0	0
T1	14193	13790	0	0
T2	10710	10301	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	41	0	0
T11	12460	12	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T32	779	0	0	0
T48	15560	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T69	436	0	0	0
T70	731	0	0	0
T105	0	5	0	0
T106	0	4	0	0
T111	0	3	0	0
T114	0	3	0	0
T115	0	4	0	0
T116	0	5	0	0
T117	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	18747	0	0
T2	10710	55	0	0
T3	23340	179	0	0
T4	17753	70	0	0
T8	598	0	0	0
T9	963	0	0	0
T10	0	385	0	0
T13	0	45	0	0
T31	769	0	0	0
T38	0	3	0	0
T47	469	0	0	0
T49	0	29	0	0
T52	19637	614	0	0
T81	1774	0	0	0
T82	423	0	0	0
T89	0	319	0	0
T101	0	363	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	371	0	0
T2	10710	2	0	0
T3	23340	3	0	0
T4	17753	3	0	0
T8	598	0	0	0
T9	963	0	0	0
T10	0	8	0	0
T13	0	3	0	0
T31	769	0	0	0
T38	0	1	0	0
T47	469	0	0	0
T49	0	1	0	0
T52	19637	10	0	0
T81	1774	0	0	0
T82	423	0	0	0
T89	0	10	0	0
T101	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4154725	0	0
T1	14193	13790	0	0
T2	10710	6044	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4155925	0	0
T1	14193	13792	0	0
T2	10710	6044	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	463	0	0
T2	10710	2	0	0
T3	23340	3	0	0
T4	17753	3	0	0
T8	598	0	0	0
T9	963	0	0	0
T10	0	8	0	0
T11	0	12	0	0
T13	0	4	0	0
T31	769	0	0	0
T47	469	1	0	0
T52	19637	10	0	0
T81	1774	0	0	0
T82	423	0	0	0
T89	0	11	0	0
T101	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	415	0	0
T2	10710	2	0	0
T3	23340	3	0	0
T4	17753	3	0	0
T8	598	0	0	0
T9	963	0	0	0
T10	0	8	0	0
T11	0	12	0	0
T13	0	3	0	0
T31	769	0	0	0
T38	0	1	0	0
T47	469	0	0	0
T52	19637	10	0	0
T81	1774	0	0	0
T82	423	0	0	0
T89	0	10	0	0
T101	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	371	0	0
T2	10710	2	0	0
T3	23340	3	0	0
T4	17753	3	0	0
T8	598	0	0	0
T9	963	0	0	0
T10	0	8	0	0
T13	0	3	0	0
T31	769	0	0	0
T38	0	1	0	0
T47	469	0	0	0
T49	0	1	0	0
T52	19637	10	0	0
T81	1774	0	0	0
T82	423	0	0	0
T89	0	10	0	0
T101	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	371	0	0
T2	10710	2	0	0
T3	23340	3	0	0
T4	17753	3	0	0
T8	598	0	0	0
T9	963	0	0	0
T10	0	8	0	0
T13	0	3	0	0
T31	769	0	0	0
T38	0	1	0	0
T47	469	0	0	0
T49	0	1	0	0
T52	19637	10	0	0
T81	1774	0	0	0
T82	423	0	0	0
T89	0	10	0	0
T101	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	18310	0	0
T2	10710	53	0	0
T3	23340	176	0	0
T4	17753	67	0	0
T8	598	0	0	0
T9	963	0	0	0
T10	0	377	0	0
T13	0	42	0	0
T31	769	0	0	0
T38	0	2	0	0
T47	469	0	0	0
T49	0	28	0	0
T52	19637	604	0	0
T81	1774	0	0	0
T82	423	0	0	0
T89	0	309	0	0
T101	0	360	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	303	0	0
T2	10710	2	0	0
T3	23340	3	0	0
T4	17753	3	0	0
T8	598	0	0	0
T9	963	0	0	0
T10	0	8	0	0
T13	0	3	0	0
T31	769	0	0	0
T38	0	1	0	0
T47	469	0	0	0
T49	0	1	0	0
T52	19637	10	0	0
T81	1774	0	0	0
T82	423	0	0	0
T89	0	10	0	0
T101	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T1,T48,T50
1	1	Covered	T5,T1,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T14
0	1	Covered	T5,T14,T50
1	0	Covered	T48,T50,T51

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T49,T86
0	1	Covered	T1,T49,T86
1	0	Covered	T48

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T48,T49
1	-	Covered	T1,T49,T86

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T1,T14
DetectSt	168	Covered	T5,T1,T14
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T48,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T1,T14
DebounceSt->IdleSt	163	Covered	T98,T63,T231
DetectSt->IdleSt	186	Covered	T5,T14,T48
DetectSt->StableSt	191	Covered	T1,T48,T49
IdleSt->DebounceSt	148	Covered	T5,T1,T14
StableSt->IdleSt	206	Covered	T1,T48,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T14
0	1	Covered	T5,T1,T14
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T14
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T1,T14
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T1,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T98,T63,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T1,T14
DetectSt	-	-	-	-	1	-	-	Covered	T5,T14,T48
DetectSt	-	-	-	-	0	1	-	Covered	T1,T48,T49
DetectSt	-	-	-	-	0	0	-	Covered	T5,T1,T14
StableSt	-	-	-	-	-	-	1	Covered	T1,T48,T49
StableSt	-	-	-	-	-	-	0	Covered	T1,T49,T86
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	3025	0	0
CntIncr_A	4968661	104041	0	0
CntNoWrap_A	4968661	4509009	0	0
DetectStDropOut_A	4968661	336	0	0
DetectedOut_A	4968661	70328	0	0
DetectedPulseOut_A	4968661	910	0	0
DisabledIdleSt_A	4968661	4048692	0	0
DisabledNoDetection_A	4968661	4050280	0	0
EnterDebounceSt_A	4968661	1524	0	0
EnterDetectSt_A	4968661	1502	0	0
EnterStableSt_A	4968661	910	0	0
PulseIsPulse_A	4968661	910	0	0
StayInStableSt	4968661	69323	0	0
gen_high_event_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	814	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3025	0	0
T1	14193	58	0	0
T2	10710	0	0	0
T5	5416	24	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	26	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	18	0	0
T49	0	24	0	0
T50	0	16	0	0
T51	0	38	0	0
T76	0	52	0	0
T85	0	22	0	0
T86	0	38	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	104041	0	0
T1	14193	2291	0	0
T2	10710	0	0	0
T5	5416	661	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	680	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	572	0	0
T49	0	636	0	0
T50	0	642	0	0
T51	0	1240	0	0
T76	0	1283	0	0
T85	0	647	0	0
T86	0	836	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4509009	0	0
T1	14193	13732	0	0
T2	10710	10305	0	0
T5	5416	4991	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4843	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	336	0	0
T1	14193	0	0	0
T2	10710	0	0	0
T5	5416	12	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	13	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T50	0	3	0	0
T51	0	6	0	0
T76	0	26	0	0
T85	0	11	0	0
T108	0	21	0	0
T109	0	12	0	0
T238	0	14	0	0
T239	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	70328	0	0
T1	14193	2626	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	1	0	0
T49	0	872	0	0
T86	0	265	0	0
T232	0	268	0	0
T233	0	3710	0	0
T234	0	2548	0	0
T235	0	107	0	0
T236	0	1234	0	0
T237	0	1259	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	910	0	0
T1	14193	29	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	1	0	0
T49	0	12	0	0
T86	0	19	0	0
T232	0	7	0	0
T233	0	26	0	0
T234	0	11	0	0
T235	0	8	0	0
T236	0	26	0	0
T237	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4048692	0	0
T1	14193	5375	0	0
T2	10710	10305	0	0
T5	5416	2015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	2014	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4050280	0	0
T1	14193	5376	0	0
T2	10710	10308	0	0
T5	5416	2015	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	2014	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1524	0	0
T1	14193	29	0	0
T2	10710	0	0	0
T5	5416	12	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	13	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	9	0	0
T49	0	12	0	0
T50	0	8	0	0
T51	0	19	0	0
T76	0	26	0	0
T85	0	11	0	0
T86	0	19	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1502	0	0
T1	14193	29	0	0
T2	10710	0	0	0
T5	5416	12	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	13	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	9	0	0
T49	0	12	0	0
T50	0	8	0	0
T51	0	19	0	0
T76	0	26	0	0
T85	0	11	0	0
T86	0	19	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	910	0	0
T1	14193	29	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	1	0	0
T49	0	12	0	0
T86	0	19	0	0
T232	0	7	0	0
T233	0	26	0	0
T234	0	11	0	0
T235	0	8	0	0
T236	0	26	0	0
T237	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	910	0	0
T1	14193	29	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	1	0	0
T49	0	12	0	0
T86	0	19	0	0
T232	0	7	0	0
T233	0	26	0	0
T234	0	11	0	0
T235	0	8	0	0
T236	0	26	0	0
T237	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	69323	0	0
T1	14193	2597	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	859	0	0
T86	0	246	0	0
T232	0	260	0	0
T233	0	3678	0	0
T234	0	2531	0	0
T235	0	99	0	0
T236	0	1205	0	0
T237	0	1242	0	0
T240	0	2156	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	814	0	0
T1	14193	29	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	11	0	0
T86	0	19	0	0
T232	0	6	0	0
T233	0	20	0	0
T234	0	5	0	0
T235	0	8	0	0
T236	0	23	0	0
T237	0	15	0	0
T240	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T1
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T89,T104
1	0	Covered	T63,T90

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T63,T90

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T4
1	-	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T2,T52,T10
DetectSt->IdleSt	186	Covered	T2,T89,T104
DetectSt->StableSt	191	Covered	T1,T3,T4
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T52,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T2,T89,T104
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	666	0	0
CntIncr_A	4968661	39056	0	0
CntNoWrap_A	4968661	4511368	0	0
DetectStDropOut_A	4968661	62	0	0
DetectedOut_A	4968661	12734	0	0
DetectedPulseOut_A	4968661	248	0	0
DisabledIdleSt_A	4968661	4198103	0	0
DisabledNoDetection_A	4968661	4199401	0	0
EnterDebounceSt_A	4968661	353	0	0
EnterDetectSt_A	4968661	313	0	0
EnterStableSt_A	4968661	248	0	0
PulseIsPulse_A	4968661	248	0	0
StayInStableSt	4968661	12444	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	203	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	666	0	0
T1	14193	4	0	0
T2	10710	5	0	0
T3	23340	4	0	0
T4	17753	4	0	0
T8	598	0	0	0
T10	0	1	0	0
T11	0	10	0	0
T13	0	6	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T52	0	5	0	0
T89	0	6	0	0
T101	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	39056	0	0
T1	14193	142	0	0
T2	10710	395	0	0
T3	23340	196	0	0
T4	17753	264	0	0
T8	598	0	0	0
T10	0	47	0	0
T11	0	178	0	0
T13	0	132	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T52	0	315	0	0
T89	0	394	0	0
T101	0	672	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511368	0	0
T1	14193	13786	0	0
T2	10710	10300	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	62	0	0
T2	10710	2	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T9	963	0	0	0
T31	769	0	0	0
T47	469	0	0	0
T52	19637	0	0	0
T81	1774	0	0	0
T82	423	0	0	0
T89	0	3	0	0
T104	0	1	0	0
T111	0	6	0	0
T115	0	2	0	0
T241	0	4	0	0
T242	0	7	0	0
T243	0	2	0	0
T244	0	2	0	0
T245	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	12734	0	0
T1	14193	138	0	0
T2	10710	0	0	0
T3	23340	181	0	0
T4	17753	126	0	0
T8	598	0	0	0
T11	0	84	0	0
T13	0	72	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T52	0	154	0	0
T101	0	355	0	0
T232	0	75	0	0
T233	0	411	0	0
T234	0	399	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	248	0	0
T1	14193	2	0	0
T2	10710	0	0	0
T3	23340	2	0	0
T4	17753	2	0	0
T8	598	0	0	0
T11	0	4	0	0
T13	0	3	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T52	0	2	0	0
T101	0	4	0	0
T232	0	1	0	0
T233	0	5	0	0
T234	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4198103	0	0
T1	14193	11164	0	0
T2	10710	6044	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4199401	0	0
T1	14193	11166	0	0
T2	10710	6044	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	353	0	0
T1	14193	2	0	0
T2	10710	3	0	0
T3	23340	2	0	0
T4	17753	2	0	0
T8	598	0	0	0
T10	0	1	0	0
T11	0	6	0	0
T13	0	3	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T52	0	3	0	0
T89	0	3	0	0
T101	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	313	0	0
T1	14193	2	0	0
T2	10710	2	0	0
T3	23340	2	0	0
T4	17753	2	0	0
T8	598	0	0	0
T11	0	4	0	0
T13	0	3	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T52	0	2	0	0
T89	0	3	0	0
T101	0	4	0	0
T232	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	248	0	0
T1	14193	2	0	0
T2	10710	0	0	0
T3	23340	2	0	0
T4	17753	2	0	0
T8	598	0	0	0
T11	0	4	0	0
T13	0	3	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T52	0	2	0	0
T101	0	4	0	0
T232	0	1	0	0
T233	0	5	0	0
T234	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	248	0	0
T1	14193	2	0	0
T2	10710	0	0	0
T3	23340	2	0	0
T4	17753	2	0	0
T8	598	0	0	0
T11	0	4	0	0
T13	0	3	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T52	0	2	0	0
T101	0	4	0	0
T232	0	1	0	0
T233	0	5	0	0
T234	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	12444	0	0
T1	14193	136	0	0
T2	10710	0	0	0
T3	23340	179	0	0
T4	17753	124	0	0
T8	598	0	0	0
T11	0	80	0	0
T13	0	69	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T52	0	152	0	0
T101	0	351	0	0
T232	0	74	0	0
T233	0	401	0	0
T234	0	394	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	203	0	0
T1	14193	2	0	0
T2	10710	0	0	0
T3	23340	2	0	0
T4	17753	2	0	0
T8	598	0	0	0
T11	0	4	0	0
T13	0	3	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T52	0	2	0	0
T101	0	4	0	0
T136	0	5	0	0
T232	0	1	0	0
T234	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T1,T48,T50
1	1	Covered	T5,T1,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T14
0	1	Covered	T5,T14,T76
1	0	Covered	T51,T86,T237

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T48,T50
0	1	Covered	T1,T48,T50
1	0	Covered	T93

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T48,T50
1	-	Covered	T1,T48,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T1,T14
DetectSt	168	Covered	T5,T1,T14
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T48,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T1,T14
DebounceSt->IdleSt	163	Covered	T98,T63,T231
DetectSt->IdleSt	186	Covered	T5,T14,T76
DetectSt->StableSt	191	Covered	T1,T48,T50
IdleSt->DebounceSt	148	Covered	T5,T1,T14
StableSt->IdleSt	206	Covered	T1,T48,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T14
0	1	Covered	T5,T1,T14
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T14
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T1,T14
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T1,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T98,T63,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T1,T14
DetectSt	-	-	-	-	1	-	-	Covered	T5,T14,T76
DetectSt	-	-	-	-	0	1	-	Covered	T1,T48,T50
DetectSt	-	-	-	-	0	0	-	Covered	T5,T1,T14
StableSt	-	-	-	-	-	-	1	Covered	T1,T48,T50
StableSt	-	-	-	-	-	-	0	Covered	T1,T48,T50
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	3055	0	0
CntIncr_A	4968661	108441	0	0
CntNoWrap_A	4968661	4508979	0	0
DetectStDropOut_A	4968661	326	0	0
DetectedOut_A	4968661	69129	0	0
DetectedPulseOut_A	4968661	859	0	0
DisabledIdleSt_A	4968661	4049162	0	0
DisabledNoDetection_A	4968661	4050759	0	0
EnterDebounceSt_A	4968661	1546	0	0
EnterDetectSt_A	4968661	1509	0	0
EnterStableSt_A	4968661	859	0	0
PulseIsPulse_A	4968661	859	0	0
StayInStableSt	4968661	68184	0	0
gen_high_event_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	764	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	3055	0	0
T1	14193	50	0	0
T2	10710	0	0	0
T5	5416	34	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	46	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	50	0	0
T49	0	62	0	0
T50	0	46	0	0
T51	0	30	0	0
T76	0	14	0	0
T85	0	46	0	0
T86	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	108441	0	0
T1	14193	2225	0	0
T2	10710	0	0	0
T5	5416	943	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	1216	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	800	0	0
T49	0	1643	0	0
T50	0	1748	0	0
T51	0	980	0	0
T76	0	338	0	0
T85	0	1356	0	0
T86	0	1448	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4508979	0	0
T1	14193	13740	0	0
T2	10710	10305	0	0
T5	5416	4981	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4823	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	326	0	0
T1	14193	0	0	0
T2	10710	0	0	0
T5	5416	17	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	23	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T51	0	5	0	0
T76	0	7	0	0
T85	0	23	0	0
T86	0	4	0	0
T108	0	26	0	0
T109	0	5	0	0
T237	0	3	0	0
T238	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	69129	0	0
T1	14193	3042	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	2126	0	0
T49	0	3117	0	0
T50	0	1011	0	0
T232	0	2013	0	0
T233	0	1371	0	0
T234	0	2416	0	0
T235	0	385	0	0
T236	0	2547	0	0
T240	0	292	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	859	0	0
T1	14193	25	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	25	0	0
T49	0	31	0	0
T50	0	23	0	0
T232	0	27	0	0
T233	0	11	0	0
T234	0	11	0	0
T235	0	15	0	0
T236	0	24	0	0
T240	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4049162	0	0
T1	14193	4408	0	0
T2	10710	10305	0	0
T5	5416	2015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	2014	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4050759	0	0
T1	14193	4408	0	0
T2	10710	10308	0	0
T5	5416	2015	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	2014	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1546	0	0
T1	14193	25	0	0
T2	10710	0	0	0
T5	5416	17	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	23	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	25	0	0
T49	0	31	0	0
T50	0	23	0	0
T51	0	15	0	0
T76	0	7	0	0
T85	0	23	0	0
T86	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1509	0	0
T1	14193	25	0	0
T2	10710	0	0	0
T5	5416	17	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	23	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	25	0	0
T49	0	31	0	0
T50	0	23	0	0
T51	0	15	0	0
T76	0	7	0	0
T85	0	23	0	0
T86	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	859	0	0
T1	14193	25	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	25	0	0
T49	0	31	0	0
T50	0	23	0	0
T232	0	27	0	0
T233	0	11	0	0
T234	0	11	0	0
T235	0	15	0	0
T236	0	24	0	0
T240	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	859	0	0
T1	14193	25	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	25	0	0
T49	0	31	0	0
T50	0	23	0	0
T232	0	27	0	0
T233	0	11	0	0
T234	0	11	0	0
T235	0	15	0	0
T236	0	24	0	0
T240	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	68184	0	0
T1	14193	3016	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	2097	0	0
T49	0	3083	0	0
T50	0	986	0	0
T232	0	1982	0	0
T233	0	1357	0	0
T234	0	2399	0	0
T235	0	370	0	0
T236	0	2521	0	0
T240	0	287	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	764	0	0
T1	14193	24	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	21	0	0
T49	0	28	0	0
T50	0	21	0	0
T232	0	23	0	0
T233	0	8	0	0
T234	0	5	0	0
T235	0	15	0	0
T236	0	22	0	0
T240	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T1
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T246,T111
1	0	Covered	T63,T90

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T90

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T1,T2,T3
DetectSt->IdleSt	186	Covered	T11,T246,T111
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T11,T246,T111
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	705	0	0
CntIncr_A	4968661	37458	0	0
CntNoWrap_A	4968661	4511329	0	0
DetectStDropOut_A	4968661	30	0	0
DetectedOut_A	4968661	12860	0	0
DetectedPulseOut_A	4968661	297	0	0
DisabledIdleSt_A	4968661	4193007	0	0
DisabledNoDetection_A	4968661	4194292	0	0
EnterDebounceSt_A	4968661	374	0	0
EnterDetectSt_A	4968661	331	0	0
EnterStableSt_A	4968661	297	0	0
PulseIsPulse_A	4968661	297	0	0
StayInStableSt	4968661	12533	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	265	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	705	0	0
T1	14193	3	0	0
T2	10710	3	0	0
T3	23340	14	0	0
T4	17753	6	0	0
T8	598	0	0	0
T10	0	22	0	0
T11	0	11	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	8	0	0
T50	0	4	0	0
T52	0	12	0	0
T89	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	37458	0	0
T1	14193	138	0	0
T2	10710	198	0	0
T3	23340	1200	0	0
T4	17753	558	0	0
T8	598	0	0	0
T10	0	1331	0	0
T11	0	289	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	176	0	0
T50	0	132	0	0
T52	0	1116	0	0
T89	0	216	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511329	0	0
T1	14193	13787	0	0
T2	10710	10302	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	30	0	0
T11	12460	5	0	0
T12	1232	0	0	0
T13	10564	0	0	0
T32	779	0	0	0
T48	15560	0	0	0
T60	403	0	0	0
T61	1073	0	0	0
T62	423	0	0	0
T69	436	0	0	0
T70	731	0	0	0
T111	0	13	0	0
T116	0	1	0	0
T243	0	3	0	0
T246	0	2	0	0
T247	0	3	0	0
T248	0	2	0	0
T249	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	12860	0	0
T1	14193	50	0	0
T2	10710	34	0	0
T3	23340	27	0	0
T4	17753	27	0	0
T8	598	0	0	0
T10	0	264	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	266	0	0
T50	0	91	0	0
T52	0	84	0	0
T89	0	178	0	0
T101	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	297	0	0
T1	14193	1	0	0
T2	10710	1	0	0
T3	23340	5	0	0
T4	17753	3	0	0
T8	598	0	0	0
T10	0	11	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	4	0	0
T50	0	2	0	0
T52	0	6	0	0
T89	0	3	0	0
T101	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4193007	0	0
T1	14193	10749	0	0
T2	10710	6044	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4194292	0	0
T1	14193	10750	0	0
T2	10710	6044	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	374	0	0
T1	14193	2	0	0
T2	10710	2	0	0
T3	23340	9	0	0
T4	17753	3	0	0
T8	598	0	0	0
T10	0	11	0	0
T11	0	6	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	4	0	0
T50	0	2	0	0
T52	0	6	0	0
T89	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	331	0	0
T1	14193	1	0	0
T2	10710	1	0	0
T3	23340	5	0	0
T4	17753	3	0	0
T8	598	0	0	0
T10	0	11	0	0
T11	0	5	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	4	0	0
T50	0	2	0	0
T52	0	6	0	0
T89	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	297	0	0
T1	14193	1	0	0
T2	10710	1	0	0
T3	23340	5	0	0
T4	17753	3	0	0
T8	598	0	0	0
T10	0	11	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	4	0	0
T50	0	2	0	0
T52	0	6	0	0
T89	0	3	0	0
T101	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	297	0	0
T1	14193	1	0	0
T2	10710	1	0	0
T3	23340	5	0	0
T4	17753	3	0	0
T8	598	0	0	0
T10	0	11	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	4	0	0
T50	0	2	0	0
T52	0	6	0	0
T89	0	3	0	0
T101	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	12533	0	0
T1	14193	49	0	0
T2	10710	33	0	0
T3	23340	22	0	0
T4	17753	24	0	0
T8	598	0	0	0
T10	0	253	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	262	0	0
T50	0	89	0	0
T52	0	78	0	0
T89	0	175	0	0
T101	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	265	0	0
T1	14193	1	0	0
T2	10710	1	0	0
T3	23340	5	0	0
T4	17753	3	0	0
T8	598	0	0	0
T10	0	11	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T48	0	4	0	0
T50	0	2	0	0
T52	0	6	0	0
T89	0	3	0	0
T101	0	9	0	0