Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T1,T48,T50
1	1	Covered	T5,T1,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T14
0	1	Covered	T5,T14,T76
1	0	Covered	T233,T107,T250

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T50,T51
0	1	Covered	T1,T50,T51
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T50,T51
1	-	Covered	T1,T50,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T1,T14
DetectSt	168	Covered	T5,T1,T14
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T50,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T1,T14
DebounceSt->IdleSt	163	Covered	T98,T63,T231
DetectSt->IdleSt	186	Covered	T5,T14,T76
DetectSt->StableSt	191	Covered	T1,T50,T51
IdleSt->DebounceSt	148	Covered	T5,T1,T14
StableSt->IdleSt	206	Covered	T1,T50,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T14
0	1	Covered	T5,T1,T14
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T14
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T1,T14
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T1,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T98,T63,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T1,T14
DetectSt	-	-	-	-	1	-	-	Covered	T5,T14,T76
DetectSt	-	-	-	-	0	1	-	Covered	T1,T50,T51
DetectSt	-	-	-	-	0	0	-	Covered	T5,T1,T14
StableSt	-	-	-	-	-	-	1	Covered	T1,T50,T51
StableSt	-	-	-	-	-	-	0	Covered	T1,T50,T51
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	2881	0	0
CntIncr_A	4968661	109367	0	0
CntNoWrap_A	4968661	4509153	0	0
DetectStDropOut_A	4968661	244	0	0
DetectedOut_A	4968661	87526	0	0
DetectedPulseOut_A	4968661	999	0	0
DisabledIdleSt_A	4968661	4032623	0	0
DisabledNoDetection_A	4968661	4034185	0	0
EnterDebounceSt_A	4968661	1451	0	0
EnterDetectSt_A	4968661	1430	0	0
EnterStableSt_A	4968661	999	0	0
PulseIsPulse_A	4968661	999	0	0
StayInStableSt	4968661	86406	0	0
gen_high_event_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	878	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	2881	0	0
T1	14193	50	0	0
T2	10710	0	0	0
T5	5416	20	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	46	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	14	0	0
T50	0	52	0	0
T51	0	50	0	0
T76	0	8	0	0
T85	0	44	0	0
T86	0	8	0	0
T232	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	109367	0	0
T1	14193	2125	0	0
T2	10710	0	0	0
T5	5416	558	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	1216	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	525	0	0
T50	0	1716	0	0
T51	0	1350	0	0
T76	0	193	0	0
T85	0	1302	0	0
T86	0	160	0	0
T232	0	945	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4509153	0	0
T1	14193	13740	0	0
T2	10710	10305	0	0
T5	5416	4995	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4823	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	244	0	0
T1	14193	0	0	0
T2	10710	0	0	0
T5	5416	10	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	23	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T76	0	4	0	0
T85	0	22	0	0
T107	0	20	0	0
T108	0	14	0	0
T109	0	12	0	0
T112	0	4	0	0
T239	0	29	0	0
T250	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	87526	0	0
T1	14193	3132	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	445	0	0
T50	0	1612	0	0
T51	0	2076	0	0
T86	0	69	0	0
T232	0	2418	0	0
T234	0	1078	0	0
T235	0	488	0	0
T236	0	477	0	0
T237	0	2086	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	999	0	0
T1	14193	25	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	7	0	0
T50	0	26	0	0
T51	0	25	0	0
T86	0	4	0	0
T232	0	27	0	0
T234	0	6	0	0
T235	0	15	0	0
T236	0	12	0	0
T237	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4032623	0	0
T1	14193	4410	0	0
T2	10710	10305	0	0
T5	5416	2015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	2014	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4034185	0	0
T1	14193	4410	0	0
T2	10710	10308	0	0
T5	5416	2015	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	2014	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1451	0	0
T1	14193	25	0	0
T2	10710	0	0	0
T5	5416	10	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	23	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	7	0	0
T50	0	26	0	0
T51	0	25	0	0
T76	0	4	0	0
T85	0	22	0	0
T86	0	4	0	0
T232	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	1430	0	0
T1	14193	25	0	0
T2	10710	0	0	0
T5	5416	10	0	0
T6	405	0	0	0
T7	4404	0	0	0
T14	5270	23	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	7	0	0
T50	0	26	0	0
T51	0	25	0	0
T76	0	4	0	0
T85	0	22	0	0
T86	0	4	0	0
T232	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	999	0	0
T1	14193	25	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	7	0	0
T50	0	26	0	0
T51	0	25	0	0
T86	0	4	0	0
T232	0	27	0	0
T234	0	6	0	0
T235	0	15	0	0
T236	0	12	0	0
T237	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	999	0	0
T1	14193	25	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	7	0	0
T50	0	26	0	0
T51	0	25	0	0
T86	0	4	0	0
T232	0	27	0	0
T234	0	6	0	0
T235	0	15	0	0
T236	0	12	0	0
T237	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	86406	0	0
T1	14193	3106	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	437	0	0
T50	0	1584	0	0
T51	0	2047	0	0
T86	0	65	0	0
T232	0	2387	0	0
T234	0	1069	0	0
T235	0	473	0	0
T236	0	463	0	0
T237	0	2064	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	878	0	0
T1	14193	24	0	0
T2	10710	0	0	0
T3	23340	0	0	0
T4	17753	0	0	0
T8	598	0	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	6	0	0
T50	0	24	0	0
T51	0	21	0	0
T86	0	4	0	0
T232	0	23	0	0
T234	0	3	0	0
T235	0	15	0	0
T236	0	10	0	0
T237	0	20	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T1
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T89,T105,T106
1	0	Covered	T63,T90

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T90

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T1,T2,T4
DetectSt->IdleSt	186	Covered	T89,T105,T106
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T90
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T2,T4
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T89,T105,T106
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4968661	802	0	0
CntIncr_A	4968661	45104	0	0
CntNoWrap_A	4968661	4511232	0	0
DetectStDropOut_A	4968661	66	0	0
DetectedOut_A	4968661	13330	0	0
DetectedPulseOut_A	4968661	306	0	0
DisabledIdleSt_A	4968661	4171055	0	0
DisabledNoDetection_A	4968661	4172304	0	0
EnterDebounceSt_A	4968661	426	0	0
EnterDetectSt_A	4968661	376	0	0
EnterStableSt_A	4968661	306	0	0
PulseIsPulse_A	4968661	306	0	0
StayInStableSt	4968661	12982	0	0
gen_high_level_sva.HighLevelEvent_A	4968661	4513807	0	0
gen_not_sticky_sva.StableStDropOut_A	4968661	262	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	802	0	0
T1	14193	3	0	0
T2	10710	5	0	0
T3	23340	2	0	0
T4	17753	11	0	0
T8	598	0	0	0
T10	0	8	0	0
T11	0	8	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T50	0	4	0	0
T52	0	23	0	0
T89	0	25	0	0
T101	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	45104	0	0
T1	14193	109	0	0
T2	10710	380	0	0
T3	23340	118	0	0
T4	17753	640	0	0
T8	598	0	0	0
T10	0	504	0	0
T11	0	190	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T50	0	134	0	0
T52	0	1827	0	0
T89	0	1629	0	0
T101	0	528	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4511232	0	0
T1	14193	13787	0	0
T2	10710	10300	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	66	0	0
T51	15751	0	0	0
T73	487	0	0	0
T83	505	0	0	0
T84	1447	0	0	0
T89	6434	12	0	0
T101	32404	0	0	0
T105	0	3	0	0
T106	0	2	0	0
T166	414	0	0	0
T187	402	0	0	0
T188	8402	0	0	0
T189	311805	0	0	0
T243	0	2	0	0
T246	0	5	0	0
T247	0	3	0	0
T248	0	1	0	0
T251	0	3	0	0
T252	0	11	0	0
T253	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	13330	0	0
T1	14193	79	0	0
T2	10710	15	0	0
T3	23340	70	0	0
T4	17753	431	0	0
T8	598	0	0	0
T10	0	73	0	0
T11	0	17	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T50	0	87	0	0
T51	0	250	0	0
T52	0	380	0	0
T101	0	499	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	306	0	0
T1	14193	1	0	0
T2	10710	2	0	0
T3	23340	1	0	0
T4	17753	5	0	0
T8	598	0	0	0
T10	0	4	0	0
T11	0	3	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T50	0	2	0	0
T51	0	4	0	0
T52	0	10	0	0
T101	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4171055	0	0
T1	14193	10659	0	0
T2	10710	6044	0	0
T5	5416	5015	0	0
T6	405	4	0	0
T7	4404	2	0	0
T14	5270	4869	0	0
T15	2369	10	0	0
T16	3046	641	0	0
T17	502	101	0	0
T18	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4172304	0	0
T1	14193	10660	0	0
T2	10710	6044	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	426	0	0
T1	14193	2	0	0
T2	10710	3	0	0
T3	23340	1	0	0
T4	17753	6	0	0
T8	598	0	0	0
T10	0	4	0	0
T11	0	5	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T50	0	2	0	0
T52	0	13	0	0
T89	0	13	0	0
T101	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	376	0	0
T1	14193	1	0	0
T2	10710	2	0	0
T3	23340	1	0	0
T4	17753	5	0	0
T8	598	0	0	0
T10	0	4	0	0
T11	0	3	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T50	0	2	0	0
T52	0	10	0	0
T89	0	12	0	0
T101	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	306	0	0
T1	14193	1	0	0
T2	10710	2	0	0
T3	23340	1	0	0
T4	17753	5	0	0
T8	598	0	0	0
T10	0	4	0	0
T11	0	3	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T50	0	2	0	0
T51	0	4	0	0
T52	0	10	0	0
T101	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	306	0	0
T1	14193	1	0	0
T2	10710	2	0	0
T3	23340	1	0	0
T4	17753	5	0	0
T8	598	0	0	0
T10	0	4	0	0
T11	0	3	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T50	0	2	0	0
T51	0	4	0	0
T52	0	10	0	0
T101	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	12982	0	0
T1	14193	78	0	0
T2	10710	13	0	0
T3	23340	69	0	0
T4	17753	426	0	0
T8	598	0	0	0
T10	0	69	0	0
T11	0	14	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T50	0	85	0	0
T51	0	242	0	0
T52	0	370	0	0
T101	0	495	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	4513807	0	0
T1	14193	13792	0	0
T2	10710	10308	0	0
T5	5416	5016	0	0
T6	405	5	0	0
T7	4404	4	0	0
T14	5270	4870	0	0
T15	2369	20	0	0
T16	3046	646	0	0
T17	502	102	0	0
T18	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4968661	262	0	0
T1	14193	1	0	0
T2	10710	2	0	0
T3	23340	1	0	0
T4	17753	5	0	0
T8	598	0	0	0
T10	0	4	0	0
T11	0	3	0	0
T14	5270	0	0	0
T15	2369	0	0	0
T16	3046	0	0	0
T17	502	0	0	0
T18	403	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T52	0	10	0	0
T101	0	4	0	0