Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1117175658	12953	0	0
auto_block_debounce_ctl_rd_A	1117175658	2117	0	0
auto_block_out_ctl_rd_A	1117175658	2750	0	0
com_det_ctl_0_rd_A	1117175658	3905	0	0
com_det_ctl_1_rd_A	1117175658	3847	0	0
com_det_ctl_2_rd_A	1117175658	3993	0	0
com_det_ctl_3_rd_A	1117175658	3903	0	0
com_out_ctl_0_rd_A	1117175658	4485	0	0
com_out_ctl_1_rd_A	1117175658	4364	0	0
com_out_ctl_2_rd_A	1117175658	4428	0	0
com_out_ctl_3_rd_A	1117175658	4592	0	0
com_pre_det_ctl_0_rd_A	1117175658	1711	0	0
com_pre_det_ctl_1_rd_A	1117175658	1574	0	0
com_pre_det_ctl_2_rd_A	1117175658	1579	0	0
com_pre_det_ctl_3_rd_A	1117175658	1548	0	0
com_pre_sel_ctl_0_rd_A	1117175658	4613	0	0
com_pre_sel_ctl_1_rd_A	1117175658	4771	0	0
com_pre_sel_ctl_2_rd_A	1117175658	4629	0	0
com_pre_sel_ctl_3_rd_A	1117175658	4609	0	0
com_sel_ctl_0_rd_A	1117175658	4659	0	0
com_sel_ctl_1_rd_A	1117175658	4817	0	0
com_sel_ctl_2_rd_A	1117175658	4719	0	0
com_sel_ctl_3_rd_A	1117175658	4541	0	0
ec_rst_ctl_rd_A	1117175658	2365	0	0
intr_enable_rd_A	1117175658	2026	0	0
key_intr_ctl_rd_A	1117175658	4229	0	0
key_intr_debounce_ctl_rd_A	1117175658	1493	0	0
key_invert_ctl_rd_A	1117175658	5772	0	0
pin_allowed_ctl_rd_A	1117175658	5846	0	0
pin_out_ctl_rd_A	1117175658	4899	0	0
pin_out_value_rd_A	1117175658	4792	0	0
regwen_rd_A	1117175658	1557	0	0
ulp_ac_debounce_ctl_rd_A	1117175658	1693	0	0
ulp_ctl_rd_A	1117175658	1690	0	0
ulp_lid_debounce_ctl_rd_A	1117175658	1723	0	0
ulp_pwrb_debounce_ctl_rd_A	1117175658	1620	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	12953	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	9	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	11	0	0
T52	952460	0	0	0
T55	0	9	0	0
T61	0	8	0	0
T70	0	4	0	0
T77	0	3	0	0
T81	346026	10	0	0
T140	0	14	0	0
T147	0	4	0	0
T283	0	23	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	2117	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	47	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	53	0	0
T32	0	9	0	0
T52	952460	0	0	0
T54	0	14	0	0
T55	0	37	0	0
T61	0	14	0	0
T70	0	12	0	0
T77	0	18	0	0
T81	346026	38	0	0
T284	0	8	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	2750	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	42	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	32	0	0
T32	0	16	0	0
T52	952460	0	0	0
T54	0	11	0	0
T55	0	40	0	0
T61	0	19	0	0
T70	0	14	0	0
T77	0	6	0	0
T81	346026	29	0	0
T284	0	9	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	3905	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	25	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	44	0	0
T50	0	38	0	0
T52	952460	0	0	0
T55	0	28	0	0
T61	0	14	0	0
T70	0	11	0	0
T77	0	31	0	0
T81	346026	46	0	0
T232	0	84	0	0
T233	0	77	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	3847	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	35	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	32	0	0
T50	0	35	0	0
T52	952460	0	0	0
T55	0	46	0	0
T61	0	14	0	0
T70	0	22	0	0
T77	0	8	0	0
T81	346026	27	0	0
T232	0	56	0	0
T233	0	67	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	3993	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	37	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	17	0	0
T50	0	49	0	0
T52	952460	0	0	0
T55	0	35	0	0
T61	0	24	0	0
T70	0	23	0	0
T77	0	26	0	0
T81	346026	26	0	0
T232	0	60	0	0
T233	0	74	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	3903	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	45	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	34	0	0
T50	0	26	0	0
T52	952460	0	0	0
T55	0	39	0	0
T61	0	25	0	0
T70	0	16	0	0
T77	0	12	0	0
T81	346026	44	0	0
T232	0	54	0	0
T233	0	65	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4485	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	44	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	49	0	0
T50	0	34	0	0
T52	952460	0	0	0
T55	0	44	0	0
T61	0	20	0	0
T70	0	6	0	0
T77	0	15	0	0
T81	346026	40	0	0
T232	0	62	0	0
T233	0	91	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4364	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	37	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	33	0	0
T50	0	56	0	0
T52	952460	0	0	0
T55	0	37	0	0
T61	0	15	0	0
T70	0	18	0	0
T77	0	1	0	0
T81	346026	55	0	0
T232	0	22	0	0
T233	0	50	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4428	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	23	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	35	0	0
T50	0	31	0	0
T52	952460	0	0	0
T55	0	30	0	0
T61	0	18	0	0
T70	0	20	0	0
T77	0	9	0	0
T81	346026	44	0	0
T232	0	47	0	0
T233	0	71	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4592	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	31	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	38	0	0
T50	0	42	0	0
T52	952460	0	0	0
T55	0	31	0	0
T61	0	18	0	0
T70	0	20	0	0
T77	0	6	0	0
T81	346026	46	0	0
T232	0	42	0	0
T233	0	83	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	1711	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	59	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	46	0	0
T52	952460	0	0	0
T55	0	41	0	0
T61	0	25	0	0
T70	0	22	0	0
T77	0	8	0	0
T81	346026	48	0	0
T125	0	15	0	0
T131	0	26	0	0
T285	0	16	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	1574	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	39	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	31	0	0
T52	952460	0	0	0
T55	0	22	0	0
T61	0	19	0	0
T70	0	28	0	0
T77	0	12	0	0
T81	346026	61	0	0
T125	0	4	0	0
T131	0	17	0	0
T285	0	26	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	1579	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	16	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	34	0	0
T52	952460	0	0	0
T55	0	32	0	0
T61	0	8	0	0
T70	0	26	0	0
T77	0	19	0	0
T81	346026	39	0	0
T125	0	12	0	0
T131	0	21	0	0
T285	0	31	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	1548	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	37	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	32	0	0
T52	952460	0	0	0
T55	0	31	0	0
T61	0	13	0	0
T70	0	22	0	0
T77	0	8	0	0
T81	346026	57	0	0
T125	0	1	0	0
T131	0	5	0	0
T285	0	42	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4613	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	59	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	39	0	0
T50	0	32	0	0
T52	952460	0	0	0
T55	0	41	0	0
T61	0	17	0	0
T70	0	22	0	0
T77	0	13	0	0
T81	346026	38	0	0
T232	0	45	0	0
T233	0	67	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4771	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	31	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	35	0	0
T50	0	59	0	0
T52	952460	0	0	0
T55	0	34	0	0
T61	0	17	0	0
T70	0	19	0	0
T77	0	12	0	0
T81	346026	48	0	0
T232	0	67	0	0
T233	0	63	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4629	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	48	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	43	0	0
T50	0	43	0	0
T52	952460	0	0	0
T55	0	33	0	0
T61	0	11	0	0
T70	0	14	0	0
T77	0	15	0	0
T81	346026	41	0	0
T232	0	73	0	0
T233	0	69	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4609	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	35	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	48	0	0
T50	0	50	0	0
T52	952460	0	0	0
T55	0	33	0	0
T61	0	17	0	0
T70	0	14	0	0
T77	0	9	0	0
T81	346026	45	0	0
T232	0	54	0	0
T233	0	81	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4659	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	42	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	45	0	0
T50	0	54	0	0
T52	952460	0	0	0
T55	0	44	0	0
T61	0	16	0	0
T70	0	12	0	0
T77	0	11	0	0
T81	346026	51	0	0
T232	0	40	0	0
T233	0	72	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4817	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	33	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	43	0	0
T50	0	27	0	0
T52	952460	0	0	0
T55	0	9	0	0
T61	0	25	0	0
T70	0	24	0	0
T77	0	9	0	0
T81	346026	38	0	0
T232	0	37	0	0
T233	0	57	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4719	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	40	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	23	0	0
T50	0	47	0	0
T52	952460	0	0	0
T55	0	23	0	0
T61	0	24	0	0
T70	0	13	0	0
T77	0	10	0	0
T81	346026	44	0	0
T232	0	64	0	0
T233	0	69	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4541	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	60	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	49	0	0
T50	0	38	0	0
T52	952460	0	0	0
T55	0	28	0	0
T61	0	11	0	0
T70	0	28	0	0
T77	0	15	0	0
T81	346026	38	0	0
T232	0	73	0	0
T233	0	49	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	2365	0	0
T1	681261	0	0	0
T2	133880	0	0	0
T5	203125	5	0	0
T6	48668	0	0	0
T7	107924	0	0	0
T14	632482	0	0	0
T15	580595	27	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	55	0	0
T50	0	11	0	0
T55	0	38	0	0
T61	0	29	0	0
T70	0	20	0	0
T77	0	11	0	0
T81	0	48	0	0
T144	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	2026	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	21	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	50	0	0
T38	0	19	0	0
T52	952460	0	0	0
T54	0	25	0	0
T55	0	47	0	0
T61	0	21	0	0
T70	0	20	0	0
T77	0	10	0	0
T81	346026	36	0	0
T125	0	8	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4229	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	1	0	0
T9	0	1	0	0
T15	580595	31	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	51	0	0
T30	0	2	0	0
T38	0	8	0	0
T52	952460	0	0	0
T61	0	19	0	0
T70	0	8	0	0
T77	0	25	0	0
T81	346026	46	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	1493	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	38	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	37	0	0
T52	952460	0	0	0
T55	0	33	0	0
T61	0	8	0	0
T70	0	25	0	0
T77	0	1	0	0
T81	346026	46	0	0
T125	0	1	0	0
T131	0	18	0	0
T285	0	28	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	5772	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	36	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T25	0	68	0	0
T26	0	56	0	0
T28	0	36	0	0
T52	952460	0	0	0
T55	0	85	0	0
T61	0	29	0	0
T70	0	23	0	0
T75	0	20	0	0
T77	0	5	0	0
T81	346026	45	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	5846	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	27	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	30	0	0
T52	952460	0	0	0
T54	0	84	0	0
T55	0	39	0	0
T61	0	6	0	0
T70	0	19	0	0
T77	0	27	0	0
T79	0	51	0	0
T81	346026	70	0	0
T83	0	73	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4899	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	31	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	32	0	0
T52	952460	0	0	0
T54	0	81	0	0
T55	0	38	0	0
T61	0	9	0	0
T70	0	19	0	0
T77	0	7	0	0
T79	0	58	0	0
T81	346026	36	0	0
T83	0	76	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	4792	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	40	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	46	0	0
T52	952460	0	0	0
T54	0	61	0	0
T55	0	43	0	0
T61	0	22	0	0
T70	0	20	0	0
T77	0	21	0	0
T79	0	61	0	0
T81	346026	40	0	0
T83	0	56	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	1557	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	36	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	26	0	0
T52	952460	0	0	0
T55	0	22	0	0
T61	0	18	0	0
T70	0	8	0	0
T77	0	6	0	0
T81	346026	37	0	0
T125	0	13	0	0
T131	0	11	0	0
T285	0	39	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	1693	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	52	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T23	0	8	0	0
T28	0	46	0	0
T52	952460	0	0	0
T55	0	28	0	0
T61	0	19	0	0
T70	0	14	0	0
T77	0	8	0	0
T81	346026	38	0	0
T88	0	5	0	0
T119	0	12	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	1690	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	45	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	50	0	0
T52	952460	0	0	0
T55	0	44	0	0
T61	0	11	0	0
T70	0	20	0	0
T77	0	7	0	0
T81	346026	37	0	0
T88	0	9	0	0
T119	0	3	0	0
T133	0	4	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	1723	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	44	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T28	0	25	0	0
T52	952460	0	0	0
T55	0	38	0	0
T61	0	19	0	0
T70	0	19	0	0
T77	0	16	0	0
T81	346026	40	0	0
T88	0	10	0	0
T119	0	6	0	0
T133	0	9	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1117175658	1620	0	0
T2	133880	0	0	0
T3	291766	0	0	0
T4	443836	0	0	0
T8	130918	0	0	0
T15	580595	37	0	0
T16	380814	0	0	0
T17	218525	0	0	0
T18	102986	0	0	0
T23	0	7	0	0
T28	0	45	0	0
T52	952460	0	0	0
T55	0	33	0	0
T61	0	24	0	0
T70	0	16	0	0
T77	0	10	0	0
T81	346026	35	0	0
T88	0	17	0	0
T119	0	13	0	0