Unified Coverage Report :: Module :: sysrst_ctrl_comboact

Module : sysrst_ctrl_comboact

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act	99.19	100.00	97.56			100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act	99.19	100.00	97.56			100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act	99.19	100.00	97.56			100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act	99.19	100.00	97.56			100.00

---

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : sysrst_ctrl_comboact

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
41	1	1
48	1	1
49	1	1
52	1	1
53	1	1
62	1	1
63	1	1
70	1	1
71	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1

---

Cond Coverage for Module : sysrst_ctrl_comboact

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T14
1	1	Covered	T2,T3,T10

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T1,T14
1	1	Covered	T1,T2,T3

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T14
1	1	Covered	T1,T3,T52

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T5,T1,T14
1	1	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T52
1	0	Covered	T1,T3,T52

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T1,T14

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

---

Branch Coverage for Module : sysrst_ctrl_comboact

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ? 
-2-:	63	(timer_expired) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T7
0	1	Covered	T5,T1,T14
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	71	(timer_expired) ? 
-2-:	71	((ec_rst_l_q == 1'b0)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T14
0	1	Covered	T5,T6,T7
0	0	Covered	T5,T1,T14

	LineNo.	Expression
-1-:	79	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
41	1	1
48	1	1
49	1	1
52	1	1
53	1	1
62	1	1
63	1	1
70	1	1
71	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T52
1	0	Covered	T2,T10,T11
1	1	Covered	T2,T10,T101

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T101
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T52
1	0	Covered	T3,T13,T48
1	1	Covered	T3,T13,T101

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T52,T10
1	0	Covered	T2,T3,T47
1	1	Covered	T2,T3,T13

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T10,T101
1	0	Covered	T2,T10,T101

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T3,T13,T101
1	0	Covered	T3,T13,T101

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T2,T3,T4

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T1,T14

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ? 
-2-:	63	(timer_expired) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T7
0	1	Covered	T5,T1,T14
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	71	(timer_expired) ? 
-2-:	71	((ec_rst_l_q == 1'b0)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T14
0	1	Covered	T5,T6,T7
0	0	Covered	T5,T1,T14

	LineNo.	Expression
-1-:	79	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
41	1	1
48	1	1
49	1	1
52	1	1
53	1	1
62	1	1
63	1	1
70	1	1
71	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T52
1	0	Covered	T2,T3,T10
1	1	Covered	T3,T11,T101

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T232
1	0	Covered	T5,T1,T14
1	1	Covered	T1,T3,T52

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T14,T2,T48
1	1	Covered	T101,T232,T136

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T52,T13
1	0	Covered	T5,T1,T2
1	1	Covered	T1,T4,T11

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T3,T11,T101
1	0	Covered	T3,T11,T101

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T101,T232,T136
1	0	Covered	T101,T232,T136

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T3,T52

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T1,T14

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ? 
-2-:	63	(timer_expired) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T7
0	1	Covered	T5,T1,T14
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	71	(timer_expired) ? 
-2-:	71	((ec_rst_l_q == 1'b0)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T14
0	1	Covered	T5,T6,T7
0	0	Covered	T5,T1,T14

	LineNo.	Expression
-1-:	79	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
41	1	1
48	1	1
49	1	1
52	1	1
53	1	1
62	1	1
63	1	1
70	1	1
71	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T14,T3
1	1	Covered	T3,T10,T48

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T14,T2
1	1	Covered	T2,T50,T89

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T10
1	0	Covered	T5,T1,T3
1	1	Covered	T1,T3,T52

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T52
1	0	Covered	T5,T1,T14
1	1	Covered	T1,T4,T10

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T3,T10,T48
1	0	Covered	T3,T10,T48

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T3,T52
1	0	Covered	T1,T3,T52

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T2,T50,T89

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T1,T14

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ? 
-2-:	63	(timer_expired) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T7
0	1	Covered	T5,T1,T14
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	71	(timer_expired) ? 
-2-:	71	((ec_rst_l_q == 1'b0)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T14
0	1	Covered	T5,T6,T7
0	0	Covered	T5,T1,T14

	LineNo.	Expression
-1-:	79	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
41	1	1
48	1	1
49	1	1
52	1	1
53	1	1
62	1	1
63	1	1
70	1	1
71	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T52,T51
1	0	Covered	T5,T1,T14
1	1	Covered	T1,T2,T4

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T10
1	0	Covered	T5,T14,T2
1	1	Covered	T2,T3,T52

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T52,T10
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T2,T4

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T14,T3,T10
1	1	Covered	T3,T10,T11

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T2,T3,T52

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T1,T14

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T14

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T5,T1,T14
1	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ? 
-2-:	63	(timer_expired) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T7
0	1	Covered	T5,T1,T14
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	71	(timer_expired) ? 
-2-:	71	((ec_rst_l_q == 1'b0)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T14
0	1	Covered	T5,T6,T7
0	0	Covered	T5,T1,T14

	LineNo.	Expression
-1-:	79	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7