Unified Coverage Report :: Group :: tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_combo_precondition_det_cg

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_combo_precondition_det_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	75.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_precondition_det_cg0	66.67	1	100	1	64	64
sysrst_ctrl_combo_precondition_det_cg1	66.67	1	100	1	64	64
sysrst_ctrl_combo_precondition_det_cg2	66.67	1	100	1	64	64
sysrst_ctrl_combo_precondition_det_cg3	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_precondition_det_cg0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.67	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_precondition_det_cg0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	1	2	66.67

Variables for Group Instance sysrst_ctrl_combo_precondition_det_cg0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_precondition_timer	3	1	2	66.67	100	1	1	0

---

Group Instance : sysrst_ctrl_combo_precondition_det_cg1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.67	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_precondition_det_cg1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	1	2	66.67

Variables for Group Instance sysrst_ctrl_combo_precondition_det_cg1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_precondition_timer	3	1	2	66.67	100	1	1	0

---

Group Instance : sysrst_ctrl_combo_precondition_det_cg2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.67	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_precondition_det_cg2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	1	2	66.67

Variables for Group Instance sysrst_ctrl_combo_precondition_det_cg2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_precondition_timer	3	1	2	66.67	100	1	1	0

---

Group Instance : sysrst_ctrl_combo_precondition_det_cg3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_precondition_det_cg3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance sysrst_ctrl_combo_precondition_det_cg3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_precondition_timer	3	0	3	100.00	100	1	1	0

Summary for Variable cp_precondition_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_precondition_timer

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
mid_range	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max_range

9

1

T8

2

T225

3

T360

4

min_range

342

1

T1

8

T10

6

T41

1

Summary for Variable cp_precondition_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_precondition_timer

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
mid_range	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max_range

3

1

T232

1

T373

1

T374

1

min_range

348

1

T1

8

T8

2

T10

6

Summary for Variable cp_precondition_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_precondition_timer

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
mid_range	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_range	1	1			T375	1		-	-		-	-
min_range	350	1			T1	8		T8	2		T10	6

Summary for Variable cp_precondition_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_precondition_timer

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_range	5	1			T232	1		T350	4		-	-
mid_range	6	1			T376	6		-	-		-	-
min_range	340	1			T1	8		T8	2		T10	6