Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1908

1

T1

60

T8

3

T9

6

auto[1]

644

1

T8

1

T9

3

T10

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1879

1

T1

32

T8

4

T9

3

auto[1]

673

1

T1

28

T9

6

T11

11

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1864

1

T1

36

T8

3

T9

9

auto[1]

688

1

T1

24

T8

1

T10

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1864

1

T1

50

T8

3

T10

20

auto[1]

688

1

T1

10

T8

1

T9

9

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2294

1

T1

22

T8

4

T9

9

auto[1]

258

1

T1

38

T10

3

T39

16

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2347

1

T1

50

T8

3

T9

9

auto[1]

205

1

T1

10

T8

1

T10

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2324

1

T1

60

T8

4

T9

9

auto[1]

228

1

T10

2

T39

2

T72

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2344

1

T1

32

T8

4

T9

9

auto[1]

208

1

T1

28

T10

5

T39

15

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2310

1

T1

60

T8

4

T9

9

auto[1]

242

1

T10

3

T39

1

T28

8

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1964

1

T1

22

T8

4

T9

9

auto[1]

588

1

T1

38

T11

7

T39

9

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

847

1

T9

9

T11

24

T27

13

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

81

1

T230

4

T337

1

T269

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

89

1

T28

2

T228

8

T337

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T240

1

T338

8

T353

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

68

1

T28

2

T240

4

T354

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

41

1

T1

28

T39

6

T229

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

16

1

T74

1

T228

5

T355

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T10

3

-

-

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

87

1

T228

8

T231

2

T354

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T229

1

T231

2

T225

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T354

2

T239

3

T338

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T356

6

T346

2

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

16

1

T72

1

T74

5

T357

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T74

1

T350

4

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

81

1

T8

1

T45

4

T74

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T1

10

T72

2

T148

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

14

1

T28

2

T240

5

T358

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T359

2

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

17

1

T360

3

T361

3

T362

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T88

2

T341

1

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

10

1

T39

1

T230

1

T355

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

21

1

T214

4

T363

3

T148

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

2

1

T10

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

138

1

T10

2

T39

1

T28

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T27

10

T46

8

T72

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

64

1

T26

2

T107

7

T214

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

127

1

T36

8

T74

10

T354

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

38

1

T9

3

T338

5

T364

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

66

1

T233

4

T225

4

T247

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T36

3

T108

1

T282

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

88

1

T10

3

T39

3

T74

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

51

1

T49

11

T230

1

T337

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T108

4

T246

8

T95

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T108

1

T169

1

T282

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

91

1

T27

2

T228

10

T269

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

44

1

T8

1

T11

9

T233

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41

1

T1

10

T45

4

T32

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T11

4

T32

4

T282

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

129

1

T46

11

T169

13

T74

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

56

1

T74

1

T239

3

T245

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T1

14

T39

3

T72

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T228

8

T269

1

T214

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

82

1

T9

6

T107

5

T229

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

36

1

T364

4

T225

3

T95

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T26

4

T32

5

T230

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T356

11

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T46

9

T28

2

T228

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

32

1

T228

8

T337

2

T91

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

57

1

T1

14

T49

5

T240

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T169

1

T245

2

T96

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

22

1

T11

8

T27

1

T107

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T365

1

T146

2

T356

9

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T11

3

T339

2

T366

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T169

1

T335

1

T99

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded