Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

733

1

T5

10

T14

11

T69

11

auto[1]

752

1

T5

10

T14

9

T69

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

350

1

T5

5

T14

4

T69

4

from_0to1

342

1

T5

5

T14

3

T69

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

759

1

T5

9

T14

10

T69

10

auto[1]

726

1

T5

11

T14

10

T69

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

757

1

T5

15

T14

8

T69

12

auto[1]

728

1

T5

5

T14

12

T69

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

49

1

T5

1

T14

1

T64

1

auto[0]

from_1to0

auto[0]

auto[1]

38

1

T126

1

T118

1

T122

2

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T5

1

T69

2

T32

1

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T5

1

T32

1

T382

1

auto[0]

from_0to1

auto[0]

auto[0]

43

1

T69

2

T64

1

T118

1

auto[0]

from_0to1

auto[0]

auto[1]

41

1

T69

1

T32

1

T291

1

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T5

1

T64

1

T32

1

auto[0]

from_0to1

auto[1]

auto[1]

36

1

T292

1

T188

1

T383

1

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T14

1

T69

1

T382

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T32

1

T382

1

T122

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T5

2

T69

1

T123

2

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T14

2

T64

3

T126

1

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T5

2

T14

1

T32

1

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T14

1

T69

1

T64

1

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T5

1

T14

1

T64

1

auto[1]

from_0to1

auto[1]

auto[1]

36

1

T5

1

T64

1

T126

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

737

1

T5

7

T14

9

T69

14

auto[1]

748

1

T5

13

T14

11

T69

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

352

1

T5

4

T14

5

T69

5

from_0to1

356

1

T5

5

T14

5

T69

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

772

1

T5

11

T14

13

T69

12

auto[1]

713

1

T5

9

T14

7

T69

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

761

1

T5

16

T14

7

T69

4

auto[1]

724

1

T5

4

T14

13

T69

16

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T5

1

T69

1

T64

1

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T5

2

T14

2

T69

1

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T382

1

T291

1

T118

1

auto[0]

from_1to0

auto[1]

auto[1]

37

1

T69

1

T126

1

T291

1

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T32

1

T382

1

T291

1

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T14

3

T69

2

T64

2

auto[0]

from_0to1

auto[1]

auto[0]

42

1

T5

1

T64

1

T126

4

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T69

1

T32

1

T292

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T5

1

T69

1

T64

1

auto[1]

from_1to0

auto[0]

auto[1]

41

1

T14

1

T64

1

T292

1

auto[1]

from_1to0

auto[1]

auto[0]

46

1

T14

1

T64

2

T292

3

auto[1]

from_1to0

auto[1]

auto[1]

44

1

T14

1

T69

1

T64

1

auto[1]

from_0to1

auto[0]

auto[0]

42

1

T5

1

T14

1

T382

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T69

2

T64

1

T382

1

auto[1]

from_0to1

auto[1]

auto[0]

39

1

T5

1

T64

1

T126

1

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T5

2

T14

1

T32

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

707

1

T5

4

T14

8

T69

6

auto[1]

778

1

T5

16

T14

12

T69

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

341

1

T5

6

T14

4

T69

4

from_0to1

346

1

T5

5

T14

4

T69

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

736

1

T5

10

T14

9

T69

7

auto[1]

749

1

T5

10

T14

11

T69

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

731

1

T5

9

T14

10

T69

9

auto[1]

754

1

T5

11

T14

10

T69

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T5

1

T32

1

T382

1

auto[0]

from_1to0

auto[0]

auto[1]

35

1

T64

1

T126

1

T292

1

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T69

1

T126

1

T292

1

auto[0]

from_1to0

auto[1]

auto[1]

33

1

T14

1

T64

1

T382

2

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T69

1

T64

2

T126

1

auto[0]

from_0to1

auto[0]

auto[1]

46

1

T5

1

T64

1

T126

1

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T5

1

T14

1

T69

1

auto[0]

from_0to1

auto[1]

auto[1]

45

1

T14

1

T69

1

T126

1

auto[1]

from_1to0

auto[0]

auto[0]

40

1

T14

2

T69

1

T32

1

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T5

1

T69

1

T64

1

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T5

2

T14

1

T32

1

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T5

2

T69

1

T64

1

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T5

2

T126

1

T32

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T14

1

T64

1

T382

1

auto[1]

from_0to1

auto[1]

auto[0]

26

1

T14

1

T69

1

T292

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T5

1

T126

2

T382

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

721

1

T5

12

T14

11

T69

11

auto[1]

764

1

T5

8

T14

9

T69

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

370

1

T5

4

T14

4

T69

6

from_0to1

373

1

T5

3

T14

5

T69

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

740

1

T5

9

T14

9

T69

9

auto[1]

745

1

T5

11

T14

11

T69

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

732

1

T5

11

T14

10

T69

11

auto[1]

753

1

T5

9

T14

10

T69

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

46

1

T5

1

T126

1

T32

1

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T14

1

T69

2

T64

2

auto[0]

from_1to0

auto[1]

auto[0]

44

1

T5

1

T69

2

T126

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T5

1

T14

2

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T69

1

T64

1

T32

1

auto[0]

from_0to1

auto[0]

auto[1]

42

1

T14

1

T126

1

T291

1

auto[0]

from_0to1

auto[1]

auto[0]

42

1

T69

2

T126

1

T32

2

auto[0]

from_0to1

auto[1]

auto[1]

46

1

T5

1

T14

2

T69

1

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T69

1

T32

1

T382

1

auto[1]

from_1to0

auto[0]

auto[1]

40

1

T5

1

T64

2

T292

1

auto[1]

from_1to0

auto[1]

auto[0]

48

1

T14

1

T118

1

T123

3

auto[1]

from_1to0

auto[1]

auto[1]

40

1

T32

1

T382

1

T122

1

auto[1]

from_0to1

auto[0]

auto[0]

46

1

T5

1

T14

1

T64

2

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T64

1

T32

1

T382

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T5

1

T14

1

T69

2

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T382

2

T291

1

T118

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

750

1

T5

11

T14

9

T69

9

auto[1]

735

1

T5

9

T14

11

T69

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

342

1

T5

6

T14

4

T69

7

from_0to1

348

1

T5

6

T14

4

T69

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

756

1

T5

12

T14

12

T69

13

auto[1]

729

1

T5

8

T14

8

T69

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

749

1

T5

13

T14

11

T69

9

auto[1]

736

1

T5

7

T14

9

T69

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T69

1

T64

1

T126

1

auto[0]

from_1to0

auto[0]

auto[1]

40

1

T291

1

T292

1

T122

2

auto[0]

from_1to0

auto[1]

auto[0]

43

1

T69

1

T32

2

T382

1

auto[0]

from_1to0

auto[1]

auto[1]

47

1

T5

2

T69

1

T64

2

auto[0]

from_0to1

auto[0]

auto[0]

41

1

T5

1

T69

2

T64

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T5

1

T14

1

T69

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T5

1

T64

1

T32

1

auto[0]

from_0to1

auto[1]

auto[1]

40

1

T69

1

T64

1

T382

2

auto[1]

from_1to0

auto[0]

auto[0]

42

1

T5

1

T14

2

T69

1

auto[1]

from_1to0

auto[0]

auto[1]

41

1

T5

1

T69

1

T64

1

auto[1]

from_1to0

auto[1]

auto[0]

42

1

T5

1

T14

1

T69

1

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T5

1

T14

1

T69

1

auto[1]

from_0to1

auto[0]

auto[0]

40

1

T5

1

T14

1

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

43

1

T69

1

T64

1

T126

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T5

2

T14

1

T382

1

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T14

1

T69

1

T291

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

760

1

T5

11

T14

8

T69

6

auto[1]

725

1

T5

9

T14

12

T69

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

344

1

T5

3

T14

4

T69

5

from_0to1

357

1

T5

3

T14

4

T69

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

761

1

T5

12

T14

12

T69

13

auto[1]

724

1

T5

8

T14

8

T69

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

760

1

T5

11

T14

10

T69

8

auto[1]

725

1

T5

9

T14

10

T69

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T5

1

T14

1

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

40

1

T69

1

T118

1

T122

1

auto[0]

from_1to0

auto[1]

auto[0]

48

1

T32

1

T382

1

T291

1

auto[0]

from_1to0

auto[1]

auto[1]

38

1

T126

1

T382

3

T292

1

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T32

1

T291

1

T122

2

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T69

2

T64

1

T126

1

auto[0]

from_0to1

auto[1]

auto[0]

40

1

T5

1

T64

1

T32

2

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T5

1

T14

1

T126

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T14

1

T126

1

T118

1

auto[1]

from_1to0

auto[0]

auto[1]

53

1

T14

2

T69

1

T64

1

auto[1]

from_1to0

auto[1]

auto[0]

30

1

T69

2

T64

2

T32

1

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T5

2

T64

1

T126

2

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T5

1

T14

1

T64

1

auto[1]

from_0to1

auto[0]

auto[1]

43

1

T69

2

T64

1

T126

1

auto[1]

from_0to1

auto[1]

auto[0]

42

1

T14

1

T126

1

T32

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T14

1

T69

1

T382

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

730

1

T5

10

T14

7

T69

8

auto[1]

755

1

T5

10

T14

13

T69

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

340

1

T5

6

T14

5

T69

5

from_0to1

340

1

T5

6

T14

6

T69

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

742

1

T5

12

T14

11

T69

14

auto[1]

743

1

T5

8

T14

9

T69

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

745

1

T5

10

T14

10

T69

13

auto[1]

740

1

T5

10

T14

10

T69

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T5

1

T69

1

T64

1

auto[0]

from_1to0

auto[0]

auto[1]

39

1

T64

1

T126

1

T382

1

auto[0]

from_1to0

auto[1]

auto[0]

44

1

T14

1

T126

1

T32

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T5

1

T14

1

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T5

2

T69

2

T126

2

auto[0]

from_0to1

auto[0]

auto[1]

29

1

T5

1

T126

1

T32

1

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T64

1

T126

1

T382

2

auto[0]

from_0to1

auto[1]

auto[1]

42

1

T14

1

T64

1

T32

1

auto[1]

from_1to0

auto[0]

auto[0]

44

1

T14

2

T69

2

T64

1

auto[1]

from_1to0

auto[0]

auto[1]

30

1

T5

2

T14

1

T69

1

auto[1]

from_1to0

auto[1]

auto[0]

48

1

T5

2

T64

2

T126

1

auto[1]

from_1to0

auto[1]

auto[1]

43

1

T126

1

T382

2

T291

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T14

2

T69

1

T64

1

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T5

2

T14

1

T69

2

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T14

2

T69

1

T126

2

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T5

1

T64

1

T382

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

771

1

T5

8

T14

8

T69

10

auto[1]

714

1

T5

12

T14

12

T69

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

357

1

T5

3

T14

6

T69

5

from_0to1

357

1

T5

4

T14

6

T69

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

739

1

T5

12

T14

11

T69

10

auto[1]

746

1

T5

8

T14

9

T69

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

763

1

T5

8

T14

6

T69

12

auto[1]

722

1

T5

12

T14

14

T69

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T5

1

T69

2

T64

2

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T14

1

T69

1

T64

1

auto[0]

from_1to0

auto[1]

auto[0]

43

1

T14

1

T291

1

T292

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T126

1

T32

2

T382

1

auto[0]

from_0to1

auto[0]

auto[0]

33

1

T126

1

T382

1

T291

1

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T5

1

T14

1

T64

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T69

1

T64

1

T291

1

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T69

1

T64

1

T382

1

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T5

1

T14

1

T69

2

auto[1]

from_1to0

auto[0]

auto[1]

42

1

T5

1

T14

1

T64

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T14

1

T64

1

T292

1

auto[1]

from_1to0

auto[1]

auto[1]

40

1

T14

1

T126

2

T382

1

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T69

1

T126

1

T32

1

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T5

2

T14

2

T126

2

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T5

1

T69

1

T64

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T14

3

T64

1

T32

2