Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	145980	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117322

1

T1

424

T4

7

T5

47

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	137977	1			T1	379		T4	2		T5	62
values[0x0]	62061	1			T1	328		T4	12		T5	27
values[0x1]	63264	1			T1	354		T4	6		T5	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	118131	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145171

1

T1

525

T4

8

T5

55

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	881	1			T1	4		T14	10		T22	1
valid_sources[0x01]	1860	1			T1	4		T14	3		T3	3
valid_sources[0x02]	1739	1			T4	3		T14	5		T101	2
valid_sources[0x03]	1034	1			T1	9		T21	1		T22	1
valid_sources[0x04]	838	1			T1	5		T14	2		T53	4
valid_sources[0x05]	825	1			T1	6		T14	3		T25	1
valid_sources[0x06]	782	1			T1	3		T2	1		T101	1
valid_sources[0x07]	974	1			T21	1		T25	2		T8	7
valid_sources[0x08]	918	1			T1	6		T8	1		T9	2
valid_sources[0x09]	999	1			T1	4		T3	1		T21	1
valid_sources[0x0a]	1212	1			T1	1		T2	2		T14	7
valid_sources[0x0b]	1031	1			T1	5		T14	2		T25	6
valid_sources[0x0c]	870	1			T1	9		T2	2		T51	1
valid_sources[0x0d]	870	1			T1	8		T2	3		T14	4
valid_sources[0x0e]	985	1			T1	9		T2	1		T14	1
valid_sources[0x0f]	953	1			T1	8		T14	15		T101	1
valid_sources[0x10]	1006	1			T1	6		T14	7		T15	2
valid_sources[0x11]	1656	1			T2	1		T14	10		T25	5
valid_sources[0x12]	940	1			T1	6		T14	2		T52	2
valid_sources[0x13]	1676	1			T1	6		T21	2		T53	2
valid_sources[0x14]	909	1			T1	6		T51	2		T53	2
valid_sources[0x15]	895	1			T1	6		T8	2		T39	3
valid_sources[0x16]	808	1			T1	2		T14	1		T53	2
valid_sources[0x17]	735	1			T53	2		T22	1		T25	5
valid_sources[0x18]	883	1			T1	2		T16	1		T7	1
valid_sources[0x19]	1440	1			T1	5		T8	1		T9	1
valid_sources[0x1a]	952	1			T1	9		T4	1		T14	4
valid_sources[0x1b]	1063	1			T1	5		T14	5		T16	4
valid_sources[0x1c]	840	1			T1	3		T13	1		T14	3
valid_sources[0x1d]	1012	1			T1	10		T52	9		T8	4
valid_sources[0x1e]	853	1			T1	4		T2	4		T25	3
valid_sources[0x1f]	865	1			T1	1		T4	2		T2	2
valid_sources[0x20]	810	1			T1	3		T6	6		T22	2
valid_sources[0x21]	894	1			T1	4		T14	6		T16	1
valid_sources[0x22]	1376	1			T1	6		T2	4		T21	1
valid_sources[0x23]	853	1			T1	2		T14	2		T8	4
valid_sources[0x24]	864	1			T14	4		T25	1		T8	3
valid_sources[0x25]	1014	1			T25	2		T8	3		T9	3
valid_sources[0x26]	885	1			T1	7		T53	3		T22	2
valid_sources[0x27]	908	1			T1	4		T14	7		T24	1
valid_sources[0x28]	1398	1			T1	2		T14	1		T7	1
valid_sources[0x29]	1047	1			T1	6		T14	7		T16	1
valid_sources[0x2a]	1307	1			T6	2		T53	14		T25	5
valid_sources[0x2b]	921	1			T1	12		T14	3		T16	2
valid_sources[0x2c]	1018	1			T1	1		T14	2		T25	1
valid_sources[0x2d]	1009	1			T1	4		T4	1		T22	2
valid_sources[0x2e]	801	1			T1	7		T14	2		T22	2
valid_sources[0x2f]	938	1			T1	8		T2	2		T14	2
valid_sources[0x30]	768	1			T1	3		T15	1		T16	2
valid_sources[0x31]	888	1			T1	4		T14	3		T24	1
valid_sources[0x32]	1021	1			T1	4		T2	2		T14	3
valid_sources[0x33]	1314	1			T1	4		T7	1		T25	1
valid_sources[0x34]	787	1			T1	2		T14	3		T22	1
valid_sources[0x35]	921	1			T1	5		T21	1		T22	1
valid_sources[0x36]	798	1			T1	1		T14	6		T21	1
valid_sources[0x37]	1020	1			T5	122		T22	1		T25	1
valid_sources[0x38]	1758	1			T21	1		T25	4		T8	5
valid_sources[0x39]	1371	1			T1	9		T16	1		T21	1
valid_sources[0x3a]	888	1			T1	6		T14	4		T101	2
valid_sources[0x3b]	1143	1			T1	1		T14	1		T25	2
valid_sources[0x3c]	918	1			T1	1		T2	1		T14	2
valid_sources[0x3d]	1497	1			T1	8		T4	1		T25	2
valid_sources[0x3e]	832	1			T1	2		T14	2		T51	1
valid_sources[0x3f]	1040	1			T1	7		T25	8		T8	4
valid_sources[0x40]	996	1			T1	4		T4	4		T14	5
valid_sources[0x41]	872	1			T1	6		T14	2		T52	5
valid_sources[0x42]	1736	1			T1	6		T13	6		T14	3
valid_sources[0x43]	937	1			T1	3		T14	1		T25	4
valid_sources[0x44]	892	1			T1	2		T4	1		T14	1
valid_sources[0x45]	882	1			T1	3		T25	3		T8	3
valid_sources[0x46]	957	1			T1	2		T22	2		T25	5
valid_sources[0x47]	845	1			T1	4		T25	7		T8	2
valid_sources[0x48]	879	1			T1	1		T22	1		T25	2
valid_sources[0x49]	1196	1			T1	4		T14	3		T52	3
valid_sources[0x4a]	746	1			T1	10		T13	2		T14	1
valid_sources[0x4b]	759	1			T1	3		T14	2		T15	2
valid_sources[0x4c]	882	1			T1	8		T14	9		T22	2
valid_sources[0x4d]	826	1			T1	6		T14	13		T21	1
valid_sources[0x4e]	953	1			T1	4		T14	2		T53	1
valid_sources[0x4f]	946	1			T1	4		T14	2		T53	2
valid_sources[0x50]	967	1			T1	5		T14	6		T3	1
valid_sources[0x51]	1061	1			T1	5		T14	1		T3	1
valid_sources[0x52]	1421	1			T1	3		T14	1		T25	2
valid_sources[0x53]	1062	1			T1	4		T14	6		T16	1
valid_sources[0x54]	778	1			T1	3		T14	9		T52	1
valid_sources[0x55]	2007	1			T1	3		T14	1		T52	2
valid_sources[0x56]	840	1			T1	2		T16	1		T22	7
valid_sources[0x57]	1079	1			T1	5		T13	6		T21	1
valid_sources[0x58]	1198	1			T1	5		T16	4		T25	4
valid_sources[0x59]	789	1			T1	3		T14	6		T3	2
valid_sources[0x5a]	928	1			T1	3		T14	4		T25	4
valid_sources[0x5b]	793	1			T1	2		T14	8		T16	1
valid_sources[0x5c]	783	1			T1	3		T14	2		T25	4
valid_sources[0x5d]	1642	1			T1	9		T14	6		T3	1
valid_sources[0x5e]	876	1			T1	4		T14	3		T53	1
valid_sources[0x5f]	974	1			T1	4		T14	1		T3	1
valid_sources[0x60]	853	1			T1	7		T14	1		T16	3
valid_sources[0x61]	1382	1			T1	6		T14	6		T25	5
valid_sources[0x62]	999	1			T1	6		T25	2		T8	4
valid_sources[0x63]	902	1			T1	8		T25	5		T8	8
valid_sources[0x64]	898	1			T14	3		T25	3		T8	4
valid_sources[0x65]	904	1			T1	8		T51	4		T24	1
valid_sources[0x66]	849	1			T14	1		T52	1		T25	1
valid_sources[0x67]	1846	1			T1	5		T16	3		T22	1
valid_sources[0x68]	829	1			T1	3		T14	1		T22	2
valid_sources[0x69]	1076	1			T1	3		T14	1		T22	1
valid_sources[0x6a]	769	1			T1	2		T14	1		T15	3
valid_sources[0x6b]	961	1			T1	15		T14	2		T15	3
valid_sources[0x6c]	821	1			T1	4		T2	1		T16	1
valid_sources[0x6d]	880	1			T1	8		T53	21		T25	1
valid_sources[0x6e]	1679	1			T1	2		T14	11		T16	1
valid_sources[0x6f]	1338	1			T2	1		T14	2		T53	6
valid_sources[0x70]	1183	1			T1	2		T3	1		T16	1
valid_sources[0x71]	974	1			T1	2		T14	5		T52	4
valid_sources[0x72]	1576	1			T21	1		T8	3		T9	2
valid_sources[0x73]	1058	1			T1	3		T52	11		T22	2
valid_sources[0x74]	853	1			T1	3		T14	5		T25	2
valid_sources[0x75]	1411	1			T1	1		T7	1		T52	4
valid_sources[0x76]	771	1			T1	2		T14	7		T7	1
valid_sources[0x77]	3335	1			T1	5		T53	2		T25	5
valid_sources[0x78]	809	1			T1	3		T25	4		T8	6
valid_sources[0x79]	935	1			T1	1		T22	1		T25	6
valid_sources[0x7a]	972	1			T1	2		T14	4		T50	1
valid_sources[0x7b]	865	1			T1	1		T14	2		T52	1
valid_sources[0x7c]	794	1			T1	4		T14	7		T53	3
valid_sources[0x7d]	976	1			T1	3		T2	2		T14	7
valid_sources[0x7e]	840	1			T1	5		T16	1		T8	3
valid_sources[0x7f]	915	1			T1	1		T14	9		T25	2
valid_sources[0x80]	862	1			T1	4		T14	1		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63666

1

T1

183

T4

2

T5

27

values[0x0]

all_enables

biggest_size

31047

1

T1

146

T4

4

T5

14

values[0x1]

all_enables

biggest_size

22609

1

T1

95

T4

1

T5

6