Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T13,T14,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T13,T14,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T13,T14,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T22
1	0	Covered	T1,T5,T2
1	1	Covered	T13,T14,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T22
0	1	Covered	T22,T82,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T22
0	1	Covered	T13,T14,T22
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T22
1	-	Covered	T13,T14,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T14,T22
DetectSt	168	Covered	T13,T14,T22
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T13,T14,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T14,T22
DebounceSt->IdleSt	163	Covered	T13,T48,T112
DetectSt->IdleSt	186	Covered	T22,T82,T92
DetectSt->StableSt	191	Covered	T13,T14,T22
IdleSt->DebounceSt	148	Covered	T13,T14,T22
StableSt->IdleSt	206	Covered	T13,T14,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T14,T22
0	1	Covered	T13,T14,T22
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T22
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T14,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T81
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T14,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T48,T112
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T14,T22
DetectSt	-	-	-	-	1	-	-	Covered	T22,T82,T92
DetectSt	-	-	-	-	0	1	-	Covered	T13,T14,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T14,T22
StableSt	-	-	-	-	-	-	0	Covered	T13,T14,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	203	0	0
CntIncr_A	5884758	250854	0	0
CntNoWrap_A	5884758	5402355	0	0
DetectStDropOut_A	5884758	4	0	0
DetectedOut_A	5884758	590	0	0
DetectedPulseOut_A	5884758	91	0	0
DisabledIdleSt_A	5884758	5147271	0	0
DisabledNoDetection_A	5884758	5149221	0	0
EnterDebounceSt_A	5884758	109	0	0
EnterDetectSt_A	5884758	95	0	0
EnterStableSt_A	5884758	91	0	0
PulseIsPulse_A	5884758	91	0	0
StayInStableSt	5884758	498	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5884758	5672	0	0
gen_low_level_sva.LowLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	89	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	203	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T13	56063	5	0	0
T14	4623	4	0	0
T15	1559	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	0	6	0	0
T40	0	4	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T47	0	4	0	0
T48	0	5	0	0
T49	0	4	0	0
T50	403	0	0	0
T51	436	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	250854	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T13	56063	55546	0	0
T14	4623	182	0	0
T15	1559	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	0	44104	0	0
T40	0	92	0	0
T42	0	97	0	0
T43	0	42	0	0
T44	0	200	0	0
T47	0	42	0	0
T48	0	138	0	0
T49	0	162	0	0
T50	403	0	0	0
T51	436	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5402355	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55657	0	0
T14	4623	628	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	4	0	0
T8	10079	0	0	0
T9	21941	0	0	0
T10	16396	0	0	0
T22	46703	1	0	0
T25	4716	0	0	0
T40	645	0	0	0
T62	494	0	0	0
T68	526	0	0	0
T82	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T101	418	0	0	0
T102	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	590	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T13	56063	6	0	0
T14	4623	10	0	0
T15	1559	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	0	18	0	0
T40	0	13	0	0
T42	0	4	0	0
T43	0	10	0	0
T44	0	16	0	0
T47	0	12	0	0
T48	0	10	0	0
T49	0	11	0	0
T50	403	0	0	0
T51	436	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	91	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T13	56063	2	0	0
T14	4623	2	0	0
T15	1559	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	0	2	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5147271	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	4	0	0
T14	4623	388	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5149221	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	4	0	0
T14	4623	401	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	109	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T13	56063	3	0	0
T14	4623	2	0	0
T15	1559	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	0	3	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	0	2	0	0
T48	0	3	0	0
T49	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	95	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T13	56063	2	0	0
T14	4623	2	0	0
T15	1559	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	0	3	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	91	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T13	56063	2	0	0
T14	4623	2	0	0
T15	1559	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	0	2	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	91	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T13	56063	2	0	0
T14	4623	2	0	0
T15	1559	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	0	2	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	498	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T13	56063	4	0	0
T14	4623	8	0	0
T15	1559	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	0	16	0	0
T40	0	11	0	0
T42	0	3	0	0
T43	0	9	0	0
T44	0	14	0	0
T47	0	10	0	0
T48	0	8	0	0
T49	0	9	0	0
T50	403	0	0	0
T51	436	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5672	0	0
T1	20567	32	0	0
T2	1290	12	0	0
T3	1232	1	0	0
T4	406	0	0	0
T5	503	4	0	0
T6	629	2	0	0
T13	56063	3	0	0
T14	4623	19	0	0
T15	1559	9	0	0
T16	493	8	0	0
T21	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	89	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T13	56063	2	0	0
T14	4623	2	0	0
T15	1559	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	0	2	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T12,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T12,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T12,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T20
1	0	Covered	T1,T5,T13
1	1	Covered	T2,T12,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T20
0	1	Covered	T2,T20,T76
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T20
0	1	Unreachable
1	0	Covered	T2,T12,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T12,T20
DetectSt	168	Covered	T2,T12,T20
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T12,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T12,T20
DebounceSt->IdleSt	163	Covered	T2,T20,T57
DetectSt->IdleSt	186	Covered	T2,T20,T76
DetectSt->StableSt	191	Covered	T2,T12,T20
IdleSt->DebounceSt	148	Covered	T2,T12,T20
StableSt->IdleSt	206	Covered	T2,T12,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T12,T20
0	1	Covered	T2,T12,T20
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T20
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T12,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T12,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T20,T57
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T12,T20
DetectSt	-	-	-	-	1	-	-	Covered	T2,T20,T76
DetectSt	-	-	-	-	0	1	-	Covered	T2,T12,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T12,T20
StableSt	-	-	-	-	-	-	0	Covered	T2,T12,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	156	0	0
CntIncr_A	5884758	5258	0	0
CntNoWrap_A	5884758	5402402	0	0
DetectStDropOut_A	5884758	17	0	0
DetectedOut_A	5884758	5463	0	0
DetectedPulseOut_A	5884758	39	0	0
DisabledIdleSt_A	5884758	5033987	0	0
DisabledNoDetection_A	5884758	5035976	0	0
EnterDebounceSt_A	5884758	100	0	0
EnterDetectSt_A	5884758	56	0	0
EnterStableSt_A	5884758	39	0	0
PulseIsPulse_A	5884758	39	0	0
StayInStableSt	5884758	5424	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5884758	5672	0	0
gen_low_level_sva.LowLevelEvent_A	5884758	5404547	0	0
gen_sticky_sva.StableStDropOut_A	5884758	352399	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	156	0	0
T2	1290	13	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	4	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	6	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	5	0	0
T60	0	2	0	0
T75	0	4	0	0
T76	0	6	0	0
T77	0	3	0	0
T78	0	4	0	0
T79	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5258	0	0
T2	1290	176	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	122	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	112	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	112	0	0
T60	0	46	0	0
T75	0	118	0	0
T76	0	163	0	0
T77	0	26	0	0
T78	0	116	0	0
T79	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5402402	0	0
T1	20567	20152	0	0
T2	1290	876	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	17	0	0
T2	1290	2	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T76	0	1	0	0
T113	0	3	0	0
T114	0	2	0	0
T115	0	4	0	0
T116	0	3	0	0
T117	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5463	0	0
T2	1290	96	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	493	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	31	0	0
T60	0	229	0	0
T75	0	250	0	0
T76	0	569	0	0
T77	0	41	0	0
T79	0	263	0	0
T86	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	39	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	1	0	0
T79	0	3	0	0
T86	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5033987	0	0
T1	20567	20152	0	0
T2	1290	81	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5035976	0	0
T1	20567	20160	0	0
T2	1290	82	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	100	0	0
T2	1290	8	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	4	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	4	0	0
T60	0	1	0	0
T75	0	2	0	0
T76	0	3	0	0
T77	0	2	0	0
T78	0	4	0	0
T79	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	56	0	0
T2	1290	5	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	2	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T75	0	2	0	0
T76	0	3	0	0
T77	0	1	0	0
T79	0	3	0	0
T86	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	39	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	1	0	0
T79	0	3	0	0
T86	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	39	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	1	0	0
T79	0	3	0	0
T86	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5424	0	0
T2	1290	93	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	491	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	30	0	0
T60	0	228	0	0
T75	0	248	0	0
T76	0	567	0	0
T77	0	40	0	0
T79	0	260	0	0
T86	0	78	0	0
T110	0	602	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5672	0	0
T1	20567	32	0	0
T2	1290	12	0	0
T3	1232	1	0	0
T4	406	0	0	0
T5	503	4	0	0
T6	629	2	0	0
T13	56063	3	0	0
T14	4623	19	0	0
T15	1559	9	0	0
T16	493	8	0	0
T21	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	352399	0	0
T2	1290	310	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	275	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	111	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	52	0	0
T60	0	265	0	0
T75	0	296	0	0
T76	0	509	0	0
T77	0	479	0	0
T79	0	618	0	0
T86	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T5,T2,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T2,T14
1	1	Covered	T5,T2,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T12,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T12,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T12,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T20
1	0	Covered	T5,T14,T15
1	1	Covered	T2,T12,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T20
0	1	Covered	T76
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T20
0	1	Unreachable
1	0	Covered	T2,T12,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T12,T20
DetectSt	168	Covered	T2,T12,T20
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T12,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T12,T20
DebounceSt->IdleSt	163	Covered	T75,T76,T110
DetectSt->IdleSt	186	Covered	T76
DetectSt->StableSt	191	Covered	T2,T12,T20
IdleSt->DebounceSt	148	Covered	T2,T12,T20
StableSt->IdleSt	206	Covered	T2,T12,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T12,T20
0	1	Covered	T2,T12,T20
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T20
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T12,T20
IdleSt	0	-	-	-	-	-	-	Covered	T5,T2,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T12,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T76,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T12,T20
DetectSt	-	-	-	-	1	-	-	Covered	T76
DetectSt	-	-	-	-	0	1	-	Covered	T2,T12,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T12,T20
StableSt	-	-	-	-	-	-	0	Covered	T2,T12,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	125	0	0
CntIncr_A	5884758	4430	0	0
CntNoWrap_A	5884758	5402433	0	0
DetectStDropOut_A	5884758	2	0	0
DetectedOut_A	5884758	8264	0	0
DetectedPulseOut_A	5884758	43	0	0
DisabledIdleSt_A	5884758	5033987	0	0
DisabledNoDetection_A	5884758	5035976	0	0
EnterDebounceSt_A	5884758	80	0	0
EnterDetectSt_A	5884758	45	0	0
EnterStableSt_A	5884758	43	0	0
PulseIsPulse_A	5884758	43	0	0
StayInStableSt	5884758	8221	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_sticky_sva.StableStDropOut_A	5884758	351492	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	125	0	0
T2	1290	6	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	4	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	2	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	2	0	0
T60	0	2	0	0
T75	0	4	0	0
T76	0	9	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	4430	0	0
T2	1290	96	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	198	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	71	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	11	0	0
T60	0	84	0	0
T75	0	284	0	0
T76	0	104	0	0
T77	0	87	0	0
T78	0	100	0	0
T79	0	111	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5402433	0	0
T1	20567	20152	0	0
T2	1290	883	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	2	0	0
T33	3116	0	0	0
T76	5272	2	0	0
T77	1106	0	0	0
T118	3420	0	0	0
T119	719	0	0	0
T120	445	0	0	0
T121	434	0	0	0
T122	2570	0	0	0
T123	502	0	0	0
T124	780	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	8264	0	0
T2	1290	405	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	498	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	377	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	81	0	0
T60	0	342	0	0
T76	0	246	0	0
T77	0	470	0	0
T78	0	636	0	0
T79	0	627	0	0
T86	0	28	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	43	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0
T86	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5033987	0	0
T1	20567	20152	0	0
T2	1290	81	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5035976	0	0
T1	20567	20160	0	0
T2	1290	82	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	80	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T75	0	4	0	0
T76	0	5	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	45	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T76	0	4	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0
T86	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	43	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0
T86	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	43	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0
T86	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	8221	0	0
T2	1290	402	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	496	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	376	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	80	0	0
T60	0	341	0	0
T76	0	244	0	0
T77	0	469	0	0
T78	0	635	0	0
T79	0	624	0	0
T86	0	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	351492	0	0
T2	1290	250	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	193	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	84	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	177	0	0
T60	0	118	0	0
T76	0	594	0	0
T77	0	107	0	0
T78	0	96	0	0
T79	0	218	0	0
T86	0	128	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T12,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T12,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T12,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T20
1	0	Covered	T1,T5,T14
1	1	Covered	T2,T12,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T20
0	1	Covered	T20,T57,T75
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T20
0	1	Unreachable
1	0	Covered	T2,T12,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T12,T20
DetectSt	168	Covered	T2,T12,T20
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T12,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T12,T20
DebounceSt->IdleSt	163	Covered	T57,T60,T86
DetectSt->IdleSt	186	Covered	T20,T57,T75
DetectSt->StableSt	191	Covered	T2,T12,T20
IdleSt->DebounceSt	148	Covered	T2,T12,T20
StableSt->IdleSt	206	Covered	T2,T12,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T12,T20
0	1	Covered	T2,T12,T20
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T20
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T12,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T12,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T57,T60,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T12,T20
DetectSt	-	-	-	-	1	-	-	Covered	T20,T57,T75
DetectSt	-	-	-	-	0	1	-	Covered	T2,T12,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T12,T20
StableSt	-	-	-	-	-	-	0	Covered	T2,T12,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	134	0	0
CntIncr_A	5884758	53213	0	0
CntNoWrap_A	5884758	5402424	0	0
DetectStDropOut_A	5884758	12	0	0
DetectedOut_A	5884758	304693	0	0
DetectedPulseOut_A	5884758	42	0	0
DisabledIdleSt_A	5884758	5033987	0	0
DisabledNoDetection_A	5884758	5035976	0	0
EnterDebounceSt_A	5884758	80	0	0
EnterDetectSt_A	5884758	54	0	0
EnterStableSt_A	5884758	42	0	0
PulseIsPulse_A	5884758	42	0	0
StayInStableSt	5884758	304651	0	0
gen_high_event_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_sticky_sva.StableStDropOut_A	5884758	7734	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	134	0	0
T2	1290	6	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	4	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	6	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	8	0	0
T60	0	5	0	0
T75	0	4	0	0
T76	0	4	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	53213	0	0
T2	1290	69	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	182	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	189	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	70	0	0
T60	0	250	0	0
T75	0	196	0	0
T76	0	147	0	0
T77	0	79	0	0
T78	0	72	0	0
T79	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5402424	0	0
T1	20567	20152	0	0
T2	1290	883	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	12	0	0
T20	1397	2	0	0
T26	16414	0	0	0
T28	13159	0	0	0
T57	0	3	0	0
T65	489	0	0	0
T75	0	1	0	0
T107	29068	0	0	0
T110	0	2	0	0
T115	0	2	0	0
T125	0	2	0	0
T126	509	0	0	0
T127	527	0	0	0
T128	410	0	0	0
T129	432	0	0	0
T130	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	304693	0	0
T2	1290	337	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	638	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	65	0	0
T21	498	0	0	0
T50	403	0	0	0
T75	0	200	0	0
T76	0	977	0	0
T77	0	535	0	0
T78	0	260	0	0
T79	0	599	0	0
T110	0	105	0	0
T111	0	154	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	42	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0
T110	0	2	0	0
T111	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5033987	0	0
T1	20567	20152	0	0
T2	1290	81	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5035976	0	0
T1	20567	20160	0	0
T2	1290	82	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	80	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	3	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	5	0	0
T60	0	5	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	54	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	3	0	0
T21	498	0	0	0
T50	403	0	0	0
T57	0	3	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0
T110	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	42	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0
T110	0	2	0	0
T111	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	42	0	0
T2	1290	3	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	1	0	0
T21	498	0	0	0
T50	403	0	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0
T110	0	2	0	0
T111	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	304651	0	0
T2	1290	334	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	636	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	64	0	0
T21	498	0	0	0
T50	403	0	0	0
T75	0	199	0	0
T76	0	975	0	0
T77	0	534	0	0
T78	0	259	0	0
T79	0	596	0	0
T110	0	103	0	0
T111	0	152	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	7734	0	0
T2	1290	382	0	0
T3	1232	0	0	0
T6	629	0	0	0
T7	945	0	0	0
T12	0	88	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T20	0	163	0	0
T21	498	0	0	0
T50	403	0	0	0
T75	0	198	0	0
T76	0	233	0	0
T77	0	59	0	0
T78	0	518	0	0
T79	0	275	0	0
T110	0	395	0	0
T111	0	223	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T31,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T7,T31,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T31,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T29,T31
1	0	Covered	T1,T4,T5
1	1	Covered	T7,T31,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T31,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T31,T38
0	1	Covered	T7,T31,T131
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T31,T38
1	-	Covered	T7,T31,T131

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T31,T38
DetectSt	168	Covered	T7,T31,T38
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T31,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T31,T38
DebounceSt->IdleSt	163	Covered	T80,T81
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T31,T38
IdleSt->DebounceSt	148	Covered	T7,T31,T38
StableSt->IdleSt	206	Covered	T7,T31,T131

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T31,T38
0	1	Covered	T7,T31,T38
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T31,T38
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T31,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T31,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T31,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T31,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T31,T131
StableSt	-	-	-	-	-	-	0	Covered	T7,T31,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	34	0	0
CntIncr_A	5884758	993	0	0
CntNoWrap_A	5884758	5402524	0	0
DetectStDropOut_A	5884758	0	0	0
DetectedOut_A	5884758	1135	0	0
DetectedPulseOut_A	5884758	16	0	0
DisabledIdleSt_A	5884758	5374635	0	0
DisabledNoDetection_A	5884758	5376593	0	0
EnterDebounceSt_A	5884758	18	0	0
EnterDetectSt_A	5884758	16	0	0
EnterStableSt_A	5884758	16	0	0
PulseIsPulse_A	5884758	16	0	0
StayInStableSt	5884758	1115	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	34	0	0
T7	945	2	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T31	0	2	0	0
T38	0	2	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T80	0	1	0	0
T101	418	0	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	2	0	0
T134	0	2	0	0
T135	0	4	0	0
T136	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	993	0	0
T7	945	87	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T31	0	79	0	0
T38	0	24	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T80	0	32	0	0
T101	418	0	0	0
T131	0	51	0	0
T132	0	71	0	0
T133	0	29	0	0
T134	0	30	0	0
T135	0	194	0	0
T136	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5402524	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1135	0	0
T7	945	42	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T31	0	40	0	0
T38	0	41	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T101	418	0	0	0
T131	0	139	0	0
T132	0	116	0	0
T133	0	54	0	0
T134	0	39	0	0
T135	0	33	0	0
T136	0	388	0	0
T137	0	120	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	16	0	0
T7	945	1	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T31	0	1	0	0
T38	0	1	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T101	418	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5374635	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5376593	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	18	0	0
T7	945	1	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T31	0	1	0	0
T38	0	1	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T80	0	1	0	0
T101	418	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	2	0	0
T136	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	16	0	0
T7	945	1	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T31	0	1	0	0
T38	0	1	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T101	418	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	16	0	0
T7	945	1	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T31	0	1	0	0
T38	0	1	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T101	418	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	16	0	0
T7	945	1	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T31	0	1	0	0
T38	0	1	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T101	418	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1115	0	0
T7	945	41	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T31	0	39	0	0
T38	0	39	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T101	418	0	0	0
T131	0	138	0	0
T132	0	115	0	0
T133	0	52	0	0
T134	0	37	0	0
T135	0	31	0	0
T136	0	386	0	0
T137	0	119	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	12	0	0
T7	945	1	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T31	0	1	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T101	418	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T135	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T36
1	0	Covered	T1,T5,T14
1	1	Covered	T6,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T36,T37
0	1	Covered	T142
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T36,T37
0	1	Covered	T6,T37,T30
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T36,T37
1	-	Covered	T6,T37,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T36,T37
DetectSt	168	Covered	T6,T36,T37
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T36,T37
DebounceSt->IdleSt	163	Covered	T38,T80,T81
DetectSt->IdleSt	186	Covered	T142
DetectSt->StableSt	191	Covered	T6,T36,T37
IdleSt->DebounceSt	148	Covered	T6,T36,T37
StableSt->IdleSt	206	Covered	T6,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T36,T37
0	1	Covered	T6,T36,T37
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T36,T37
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T38
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T36,T37
DetectSt	-	-	-	-	1	-	-	Covered	T142
DetectSt	-	-	-	-	0	1	-	Covered	T6,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T37,T30
StableSt	-	-	-	-	-	-	0	Covered	T6,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	89	0	0
CntIncr_A	5884758	80783	0	0
CntNoWrap_A	5884758	5402469	0	0
DetectStDropOut_A	5884758	1	0	0
DetectedOut_A	5884758	69720	0	0
DetectedPulseOut_A	5884758	42	0	0
DisabledIdleSt_A	5884758	5213213	0	0
DisabledNoDetection_A	5884758	5215161	0	0
EnterDebounceSt_A	5884758	46	0	0
EnterDetectSt_A	5884758	43	0	0
EnterStableSt_A	5884758	42	0	0
PulseIsPulse_A	5884758	42	0	0
StayInStableSt	5884758	69658	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5884758	1683	0	0
gen_low_level_sva.LowLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	89	0	0
T6	629	4	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	4	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	2	0	0
T131	0	4	0	0
T132	0	4	0	0
T143	0	2	0	0
T144	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	80783	0	0
T6	629	26	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	26	0	0
T36	0	78	0	0
T37	0	23	0	0
T38	0	24	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	76	0	0
T131	0	102	0	0
T132	0	142	0	0
T143	0	25	0	0
T144	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5402469	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	224	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1	0	0
T142	32148	1	0	0
T145	501	0	0	0
T146	11574	0	0	0
T147	502	0	0	0
T148	34749	0	0	0
T149	498	0	0	0
T150	454	0	0	0
T151	10461	0	0	0
T152	526	0	0	0
T153	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	69720	0	0
T6	629	6	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	43	0	0
T36	0	143	0	0
T37	0	6	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	116	0	0
T131	0	41	0	0
T132	0	300	0	0
T133	0	3	0	0
T143	0	46	0	0
T144	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	42	0	0
T6	629	2	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5213213	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	4	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5215161	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	4	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	46	0	0
T6	629	2	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T131	0	2	0	0
T132	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	43	0	0
T6	629	2	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	42	0	0
T6	629	2	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	42	0	0
T6	629	2	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	69658	0	0
T6	629	4	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	41	0	0
T36	0	141	0	0
T37	0	5	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	114	0	0
T131	0	38	0	0
T132	0	297	0	0
T133	0	2	0	0
T143	0	44	0	0
T144	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1683	0	0
T2	1290	0	0	0
T3	1232	3	0	0
T5	503	6	0	0
T6	629	2	0	0
T7	945	2	0	0
T13	56063	0	0	0
T14	4623	18	0	0
T15	1559	0	0	0
T16	493	4	0	0
T21	498	4	0	0
T22	0	11	0	0
T51	0	3	0	0
T101	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	22	0	0
T6	629	2	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	2	0	0
T37	0	1	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T135	0	2	0	0
T144	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0