Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T14
1	1	Covered	T1,T5,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T31,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T31,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T31,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T31,T37
1	0	Covered	T1,T5,T14
1	1	Covered	T3,T31,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T31,T37
0	1	Covered	T189
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T31,T37
0	1	Covered	T3,T31,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T31,T37
1	-	Covered	T3,T31,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T31,T37
DetectSt	168	Covered	T3,T31,T37
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T31,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T31,T37
DebounceSt->IdleSt	163	Covered	T38,T80,T195
DetectSt->IdleSt	186	Covered	T189
DetectSt->StableSt	191	Covered	T3,T31,T37
IdleSt->DebounceSt	148	Covered	T3,T31,T37
StableSt->IdleSt	206	Covered	T3,T31,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T31,T37
0	1	Covered	T3,T31,T37
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T31,T37
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T31,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T31,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T195,T196
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T31,T37
DetectSt	-	-	-	-	1	-	-	Covered	T189
DetectSt	-	-	-	-	0	1	-	Covered	T3,T31,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T31,T37
StableSt	-	-	-	-	-	-	0	Covered	T3,T31,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	72	0	0
CntIncr_A	5884758	2102	0	0
CntNoWrap_A	5884758	5402486	0	0
DetectStDropOut_A	5884758	1	0	0
DetectedOut_A	5884758	2905	0	0
DetectedPulseOut_A	5884758	32	0	0
DisabledIdleSt_A	5884758	5375143	0	0
DisabledNoDetection_A	5884758	5377102	0	0
EnterDebounceSt_A	5884758	39	0	0
EnterDetectSt_A	5884758	33	0	0
EnterStableSt_A	5884758	32	0	0
PulseIsPulse_A	5884758	32	0	0
StayInStableSt	5884758	2864	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	72	0	0
T3	1232	2	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T31	0	4	0	0
T33	0	4	0	0
T37	0	4	0	0
T38	0	1	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	4	0	0
T134	0	2	0	0
T143	0	4	0	0
T176	0	2	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	2102	0	0
T3	1232	90	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T31	0	158	0	0
T33	0	30	0	0
T37	0	46	0	0
T38	0	24	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	142	0	0
T134	0	30	0	0
T143	0	50	0	0
T176	0	15	0	0
T194	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5402486	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	829	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1	0	0
T161	51294	0	0	0
T189	22470	1	0	0
T197	421	0	0	0
T198	410	0	0	0
T199	632	0	0	0
T200	13301	0	0	0
T201	525	0	0	0
T202	4402	0	0	0
T203	547	0	0	0
T204	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	2905	0	0
T3	1232	417	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T31	0	242	0	0
T33	0	21	0	0
T37	0	84	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	173	0	0
T134	0	39	0	0
T143	0	110	0	0
T155	0	184	0	0
T176	0	2	0	0
T194	0	30	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	32	0	0
T3	1232	1	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T31	0	2	0	0
T33	0	2	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	2	0	0
T134	0	1	0	0
T143	0	2	0	0
T155	0	1	0	0
T176	0	1	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5375143	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	4	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5377102	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	4	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	39	0	0
T3	1232	1	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T31	0	2	0	0
T33	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	2	0	0
T134	0	1	0	0
T143	0	2	0	0
T176	0	1	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	33	0	0
T3	1232	1	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T31	0	2	0	0
T33	0	2	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	2	0	0
T134	0	1	0	0
T143	0	2	0	0
T155	0	1	0	0
T176	0	1	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	32	0	0
T3	1232	1	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T31	0	2	0	0
T33	0	2	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	2	0	0
T134	0	1	0	0
T143	0	2	0	0
T155	0	1	0	0
T176	0	1	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	32	0	0
T3	1232	1	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T31	0	2	0	0
T33	0	2	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	2	0	0
T134	0	1	0	0
T143	0	2	0	0
T155	0	1	0	0
T176	0	1	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	2864	0	0
T3	1232	416	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T31	0	240	0	0
T33	0	19	0	0
T37	0	82	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	171	0	0
T134	0	37	0	0
T143	0	107	0	0
T155	0	183	0	0
T176	0	1	0	0
T194	0	28	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	23	0	0
T3	1232	1	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T31	0	2	0	0
T33	0	2	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	2	0	0
T143	0	1	0	0
T155	0	1	0	0
T176	0	1	0	0
T178	0	2	0	0
T205	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T14
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T14
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T32,T34
1	0	Covered	T1,T5,T14
1	1	Covered	T3,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T35
0	1	Not Covered
1	0	Covered	T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T35
0	1	Covered	T34,T35,T132
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T34,T35
1	-	Covered	T34,T35,T132

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T34,T35
DetectSt	168	Covered	T3,T34,T35
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T34,T35
DebounceSt->IdleSt	163	Covered	T178,T81
DetectSt->IdleSt	186	Covered	T80
DetectSt->StableSt	191	Covered	T3,T34,T35
IdleSt->DebounceSt	148	Covered	T3,T34,T35
StableSt->IdleSt	206	Covered	T34,T35,T132

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T34,T35
0	1	Covered	T3,T34,T35
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T34,T35
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T81
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T178
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T80
DetectSt	-	-	-	-	0	1	-	Covered	T3,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T35,T132
StableSt	-	-	-	-	-	-	0	Covered	T3,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	54	0	0
CntIncr_A	5884758	1716	0	0
CntNoWrap_A	5884758	5402504	0	0
DetectStDropOut_A	5884758	0	0	0
DetectedOut_A	5884758	2050	0	0
DetectedPulseOut_A	5884758	25	0	0
DisabledIdleSt_A	5884758	5179986	0	0
DisabledNoDetection_A	5884758	5181943	0	0
EnterDebounceSt_A	5884758	28	0	0
EnterDetectSt_A	5884758	26	0	0
EnterStableSt_A	5884758	25	0	0
PulseIsPulse_A	5884758	25	0	0
StayInStableSt	5884758	2012	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5884758	5170	0	0
gen_low_level_sva.LowLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	54	0	0
T3	1232	2	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T34	0	4	0	0
T35	0	4	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T80	0	2	0	0
T132	0	4	0	0
T135	0	4	0	0
T136	0	2	0	0
T175	0	4	0	0
T178	0	3	0	0
T205	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1716	0	0
T3	1232	90	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T34	0	114	0	0
T35	0	174	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T80	0	32	0	0
T132	0	142	0	0
T135	0	194	0	0
T136	0	70	0	0
T175	0	44	0	0
T178	0	112	0	0
T205	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5402504	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	829	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	2050	0	0
T3	1232	225	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T34	0	86	0	0
T35	0	247	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	171	0	0
T135	0	173	0	0
T136	0	52	0	0
T137	0	78	0	0
T175	0	181	0	0
T178	0	30	0	0
T205	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	25	0	0
T3	1232	1	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	2	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	2	0	0
T175	0	2	0	0
T178	0	1	0	0
T205	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5179986	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	4	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5181943	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	4	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	28	0	0
T3	1232	1	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T80	0	1	0	0
T132	0	2	0	0
T135	0	2	0	0
T136	0	1	0	0
T175	0	2	0	0
T178	0	2	0	0
T205	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	26	0	0
T3	1232	1	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T80	0	1	0	0
T132	0	2	0	0
T135	0	2	0	0
T136	0	1	0	0
T175	0	2	0	0
T178	0	1	0	0
T205	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	25	0	0
T3	1232	1	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	2	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	2	0	0
T175	0	2	0	0
T178	0	1	0	0
T205	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	25	0	0
T3	1232	1	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	2	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	2	0	0
T175	0	2	0	0
T178	0	1	0	0
T205	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	2012	0	0
T3	1232	223	0	0
T6	629	0	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T34	0	83	0	0
T35	0	244	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T132	0	168	0	0
T135	0	170	0	0
T136	0	51	0	0
T137	0	75	0	0
T175	0	178	0	0
T178	0	29	0	0
T205	0	79	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5170	0	0
T1	20567	32	0	0
T2	1290	0	0	0
T3	1232	1	0	0
T4	406	0	0	0
T5	503	4	0	0
T6	629	1	0	0
T7	0	2	0	0
T13	56063	0	0	0
T14	4623	17	0	0
T15	1559	0	0	0
T16	493	6	0	0
T21	0	7	0	0
T22	0	14	0	0
T51	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	12	0	0
T30	619	0	0	0
T34	775	1	0	0
T35	0	1	0	0
T59	1589	0	0	0
T60	983	0	0	0
T84	583	0	0	0
T132	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T169	9421	0	0	0
T170	522	0	0	0
T171	522	0	0	0
T172	1310	0	0	0
T173	496	0	0	0
T175	0	1	0	0
T178	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T14
1	1	Covered	T1,T5,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T5,T14
1	1	Covered	T3,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T7
1	-	Covered	T3,T6,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T7
DetectSt	168	Covered	T3,T6,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T7
DebounceSt->IdleSt	163	Covered	T80,T178,T181
DetectSt->IdleSt	186	Covered	T85
DetectSt->StableSt	191	Covered	T3,T6,T7
IdleSt->DebounceSt	148	Covered	T3,T6,T7
StableSt->IdleSt	206	Covered	T3,T6,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T178,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T85
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T37
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	88	0	0
CntIncr_A	5884758	18508	0	0
CntNoWrap_A	5884758	5402470	0	0
DetectStDropOut_A	5884758	1	0	0
DetectedOut_A	5884758	26741	0	0
DetectedPulseOut_A	5884758	41	0	0
DisabledIdleSt_A	5884758	5293348	0	0
DisabledNoDetection_A	5884758	5295304	0	0
EnterDebounceSt_A	5884758	46	0	0
EnterDetectSt_A	5884758	42	0	0
EnterStableSt_A	5884758	41	0	0
PulseIsPulse_A	5884758	41	0	0
StayInStableSt	5884758	26683	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	88	0	0
T3	1232	2	0	0
T6	629	2	0	0
T7	945	2	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T32	0	2	0	0
T35	0	2	0	0
T37	0	4	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	2	0	0
T118	0	2	0	0
T143	0	6	0	0
T208	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	18508	0	0
T3	1232	90	0	0
T6	629	13	0	0
T7	945	87	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T32	0	11202	0	0
T35	0	87	0	0
T37	0	46	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	76	0	0
T118	0	45	0	0
T143	0	75	0	0
T208	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5402470	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	829	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	226	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1	0	0
T85	798	1	0	0
T131	744	0	0	0
T144	786	0	0	0
T188	506	0	0	0
T209	406	0	0	0
T210	479	0	0	0
T211	658	0	0	0
T212	426	0	0	0
T213	495	0	0	0
T214	13089	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	26741	0	0
T3	1232	16	0	0
T6	629	57	0	0
T7	945	448	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T32	0	11247	0	0
T35	0	419	0	0
T37	0	18	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T118	0	68	0	0
T143	0	59	0	0
T194	0	3	0	0
T208	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	41	0	0
T3	1232	1	0	0
T6	629	1	0	0
T7	945	1	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T118	0	1	0	0
T143	0	3	0	0
T194	0	1	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5293348	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	4	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	4	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5295304	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	4	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	4	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	46	0	0
T3	1232	1	0	0
T6	629	1	0	0
T7	945	1	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T118	0	1	0	0
T143	0	3	0	0
T208	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	42	0	0
T3	1232	1	0	0
T6	629	1	0	0
T7	945	1	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T118	0	1	0	0
T143	0	3	0	0
T208	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	41	0	0
T3	1232	1	0	0
T6	629	1	0	0
T7	945	1	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T118	0	1	0	0
T143	0	3	0	0
T194	0	1	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	41	0	0
T3	1232	1	0	0
T6	629	1	0	0
T7	945	1	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T118	0	1	0	0
T143	0	3	0	0
T194	0	1	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	26683	0	0
T3	1232	15	0	0
T6	629	56	0	0
T7	945	446	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T32	0	11246	0	0
T35	0	418	0	0
T37	0	16	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T118	0	66	0	0
T143	0	55	0	0
T194	0	2	0	0
T208	0	45	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	24	0	0
T3	1232	1	0	0
T6	629	1	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T24	603	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T143	0	2	0	0
T154	0	1	0	0
T175	0	2	0	0
T176	0	1	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T14
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T14
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T31,T32,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T31,T32,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T31,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T31,T32
1	0	Covered	T1,T5,T14
1	1	Covered	T31,T32,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T33
0	1	Covered	T31,T33,T143
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T32,T33
1	-	Covered	T31,T33,T143

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T31,T32,T33
DetectSt	168	Covered	T31,T32,T33
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T31,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T32,T33
DebounceSt->IdleSt	163	Covered	T80,T81
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T31,T32,T33
IdleSt->DebounceSt	148	Covered	T31,T32,T33
StableSt->IdleSt	206	Covered	T31,T32,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T32,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T32,T33
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T32,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T31,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T33,T143
StableSt	-	-	-	-	-	-	0	Covered	T31,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	46	0	0
CntIncr_A	5884758	80718	0	0
CntNoWrap_A	5884758	5402512	0	0
DetectStDropOut_A	5884758	0	0	0
DetectedOut_A	5884758	13308	0	0
DetectedPulseOut_A	5884758	22	0	0
DisabledIdleSt_A	5884758	5169454	0	0
DisabledNoDetection_A	5884758	5171412	0	0
EnterDebounceSt_A	5884758	24	0	0
EnterDetectSt_A	5884758	22	0	0
EnterStableSt_A	5884758	22	0	0
PulseIsPulse_A	5884758	22	0	0
StayInStableSt	5884758	13272	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5884758	5125	0	0
gen_low_level_sva.LowLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	46	0	0
T27	29212	0	0	0
T31	1189	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T39	15387	0	0	0
T44	740	0	0	0
T45	15188	0	0	0
T64	1821	0	0	0
T70	522	0	0	0
T80	0	1	0	0
T103	447	0	0	0
T142	0	2	0	0
T143	0	4	0	0
T158	193887	0	0	0
T159	423	0	0	0
T168	0	2	0	0
T175	0	4	0	0
T179	0	2	0	0
T180	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	80718	0	0
T27	29212	0	0	0
T31	1189	79	0	0
T32	0	11202	0	0
T33	0	15	0	0
T39	15387	0	0	0
T44	740	0	0	0
T45	15188	0	0	0
T64	1821	0	0	0
T70	522	0	0	0
T80	0	32	0	0
T103	447	0	0	0
T142	0	4898	0	0
T143	0	50	0	0
T158	193887	0	0	0
T159	423	0	0	0
T168	0	63779	0	0
T175	0	44	0	0
T179	0	71	0	0
T180	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5402512	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	13308	0	0
T27	29212	0	0	0
T31	1189	57	0	0
T32	0	2105	0	0
T33	0	8	0	0
T39	15387	0	0	0
T44	740	0	0	0
T45	15188	0	0	0
T64	1821	0	0	0
T70	522	0	0	0
T103	447	0	0	0
T142	0	9880	0	0
T143	0	117	0	0
T158	193887	0	0	0
T159	423	0	0	0
T168	0	43	0	0
T175	0	132	0	0
T179	0	43	0	0
T180	0	41	0	0
T215	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	22	0	0
T27	29212	0	0	0
T31	1189	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T39	15387	0	0	0
T44	740	0	0	0
T45	15188	0	0	0
T64	1821	0	0	0
T70	522	0	0	0
T103	447	0	0	0
T142	0	1	0	0
T143	0	2	0	0
T158	193887	0	0	0
T159	423	0	0	0
T168	0	1	0	0
T175	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0
T215	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5169454	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5171412	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	24	0	0
T27	29212	0	0	0
T31	1189	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T39	15387	0	0	0
T44	740	0	0	0
T45	15188	0	0	0
T64	1821	0	0	0
T70	522	0	0	0
T80	0	1	0	0
T103	447	0	0	0
T142	0	1	0	0
T143	0	2	0	0
T158	193887	0	0	0
T159	423	0	0	0
T168	0	1	0	0
T175	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	22	0	0
T27	29212	0	0	0
T31	1189	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T39	15387	0	0	0
T44	740	0	0	0
T45	15188	0	0	0
T64	1821	0	0	0
T70	522	0	0	0
T103	447	0	0	0
T142	0	1	0	0
T143	0	2	0	0
T158	193887	0	0	0
T159	423	0	0	0
T168	0	1	0	0
T175	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0
T215	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	22	0	0
T27	29212	0	0	0
T31	1189	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T39	15387	0	0	0
T44	740	0	0	0
T45	15188	0	0	0
T64	1821	0	0	0
T70	522	0	0	0
T103	447	0	0	0
T142	0	1	0	0
T143	0	2	0	0
T158	193887	0	0	0
T159	423	0	0	0
T168	0	1	0	0
T175	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0
T215	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	22	0	0
T27	29212	0	0	0
T31	1189	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T39	15387	0	0	0
T44	740	0	0	0
T45	15188	0	0	0
T64	1821	0	0	0
T70	522	0	0	0
T103	447	0	0	0
T142	0	1	0	0
T143	0	2	0	0
T158	193887	0	0	0
T159	423	0	0	0
T168	0	1	0	0
T175	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0
T215	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	13272	0	0
T27	29212	0	0	0
T31	1189	56	0	0
T32	0	2103	0	0
T33	0	7	0	0
T39	15387	0	0	0
T44	740	0	0	0
T45	15188	0	0	0
T64	1821	0	0	0
T70	522	0	0	0
T103	447	0	0	0
T142	0	9878	0	0
T143	0	115	0	0
T158	193887	0	0	0
T159	423	0	0	0
T168	0	41	0	0
T175	0	129	0	0
T179	0	41	0	0
T180	0	39	0	0
T215	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5125	0	0
T1	20567	26	0	0
T2	1290	0	0	0
T3	1232	1	0	0
T4	406	0	0	0
T5	503	5	0	0
T6	629	1	0	0
T13	56063	0	0	0
T14	4623	13	0	0
T15	1559	0	0	0
T16	493	9	0	0
T21	0	7	0	0
T22	0	8	0	0
T51	0	5	0	0
T101	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	8	0	0
T27	29212	0	0	0
T31	1189	1	0	0
T33	0	1	0	0
T39	15387	0	0	0
T44	740	0	0	0
T45	15188	0	0	0
T64	1821	0	0	0
T70	522	0	0	0
T103	447	0	0	0
T141	0	1	0	0
T143	0	2	0	0
T158	193887	0	0	0
T159	423	0	0	0
T160	0	1	0	0
T175	0	1	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T31,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T31,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T31,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T31,T37
1	0	Covered	T1,T5,T2
1	1	Covered	T6,T31,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T31,T37
0	1	Covered	T30
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T31,T37
0	1	Covered	T6,T31,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T31,T37
1	-	Covered	T6,T31,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T31,T37
DetectSt	168	Covered	T6,T31,T37
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T31,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T31,T37
DebounceSt->IdleSt	163	Covered	T133,T80,T195
DetectSt->IdleSt	186	Covered	T30
DetectSt->StableSt	191	Covered	T6,T31,T37
IdleSt->DebounceSt	148	Covered	T6,T31,T37
StableSt->IdleSt	206	Covered	T6,T31,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T31,T37
0	1	Covered	T6,T31,T37
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T31,T37
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T31,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T31,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T195,T140,T189
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T31,T37
DetectSt	-	-	-	-	1	-	-	Covered	T30
DetectSt	-	-	-	-	0	1	-	Covered	T6,T31,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T31,T37
StableSt	-	-	-	-	-	-	0	Covered	T6,T31,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	87	0	0
CntIncr_A	5884758	2027	0	0
CntNoWrap_A	5884758	5402471	0	0
DetectStDropOut_A	5884758	1	0	0
DetectedOut_A	5884758	3713	0	0
DetectedPulseOut_A	5884758	40	0	0
DisabledIdleSt_A	5884758	5390678	0	0
DisabledNoDetection_A	5884758	5392632	0	0
EnterDebounceSt_A	5884758	47	0	0
EnterDetectSt_A	5884758	41	0	0
EnterStableSt_A	5884758	40	0	0
PulseIsPulse_A	5884758	40	0	0
StayInStableSt	5884758	3655	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	87	0	0
T6	629	4	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	4	0	0
T31	0	2	0	0
T33	0	4	0	0
T35	0	4	0	0
T37	0	4	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	2	0	0
T131	0	2	0	0
T143	0	4	0	0
T144	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	2027	0	0
T6	629	26	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	26	0	0
T31	0	79	0	0
T33	0	30	0	0
T35	0	174	0	0
T37	0	46	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	76	0	0
T131	0	51	0	0
T143	0	50	0	0
T144	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5402471	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	224	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1	0	0
T30	619	1	0	0
T59	1589	0	0	0
T60	983	0	0	0
T84	583	0	0	0
T169	9421	0	0	0
T170	522	0	0	0
T171	522	0	0	0
T172	1310	0	0	0
T173	496	0	0	0
T174	411	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	3713	0	0
T6	629	81	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	68	0	0
T31	0	55	0	0
T33	0	77	0	0
T35	0	188	0	0
T37	0	116	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	197	0	0
T131	0	139	0	0
T143	0	85	0	0
T144	0	48	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	40	0	0
T6	629	2	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	2	0	0
T35	0	2	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T131	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5390678	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	4	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5392632	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	4	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	47	0	0
T6	629	2	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T33	0	2	0	0
T35	0	2	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T131	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	41	0	0
T6	629	2	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T33	0	2	0	0
T35	0	2	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T131	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	40	0	0
T6	629	2	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	2	0	0
T35	0	2	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T131	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	40	0	0
T6	629	2	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	2	0	0
T35	0	2	0	0
T37	0	2	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T131	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	3655	0	0
T6	629	79	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	67	0	0
T31	0	54	0	0
T33	0	74	0	0
T35	0	186	0	0
T37	0	113	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	196	0	0
T131	0	138	0	0
T143	0	82	0	0
T144	0	47	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	22	0	0
T6	629	2	0	0
T7	945	0	0	0
T16	493	0	0	0
T21	498	0	0	0
T22	46703	0	0	0
T24	603	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T131	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T29,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T7,T29,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T29,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T29,T32
1	0	Covered	T1,T5,T2
1	1	Covered	T7,T29,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T29,T30
0	1	Covered	T176
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T29,T30
0	1	Covered	T29,T30,T143
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T29,T30
1	-	Covered	T29,T30,T143

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T29,T30
DetectSt	168	Covered	T7,T29,T30
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T29,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T29,T30
DebounceSt->IdleSt	163	Covered	T80,T81
DetectSt->IdleSt	186	Covered	T176
DetectSt->StableSt	191	Covered	T7,T29,T30
IdleSt->DebounceSt	148	Covered	T7,T29,T30
StableSt->IdleSt	206	Covered	T29,T30,T143

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T29,T30
0	1	Covered	T7,T29,T30
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T29,T30
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T29,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T29,T30
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T29,T30
DetectSt	-	-	-	-	1	-	-	Covered	T176
DetectSt	-	-	-	-	0	1	-	Covered	T7,T29,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T30,T143
StableSt	-	-	-	-	-	-	0	Covered	T7,T29,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	50	0	0
CntIncr_A	5884758	1208	0	0
CntNoWrap_A	5884758	5402508	0	0
DetectStDropOut_A	5884758	1	0	0
DetectedOut_A	5884758	1911	0	0
DetectedPulseOut_A	5884758	23	0	0
DisabledIdleSt_A	5884758	5326860	0	0
DisabledNoDetection_A	5884758	5328820	0	0
EnterDebounceSt_A	5884758	26	0	0
EnterDetectSt_A	5884758	24	0	0
EnterStableSt_A	5884758	23	0	0
PulseIsPulse_A	5884758	23	0	0
StayInStableSt	5884758	1876	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5884758	5672	0	0
gen_low_level_sva.LowLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	50	0	0
T7	945	2	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T29	0	2	0	0
T30	0	4	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T80	0	1	0	0
T85	0	2	0	0
T101	418	0	0	0
T131	0	2	0	0
T132	0	2	0	0
T143	0	2	0	0
T176	0	2	0	0
T216	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1208	0	0
T7	945	87	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T29	0	23	0	0
T30	0	26	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T80	0	31	0	0
T85	0	76	0	0
T101	418	0	0	0
T131	0	51	0	0
T132	0	71	0	0
T143	0	25	0	0
T176	0	15	0	0
T216	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5402508	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1	0	0
T80	7120	0	0	0
T111	969	0	0	0
T176	555	1	0	0
T217	427	0	0	0
T218	422	0	0	0
T219	3033	0	0	0
T220	403	0	0	0
T221	492	0	0	0
T222	507	0	0	0
T223	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1911	0	0
T7	945	183	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T29	0	17	0	0
T30	0	87	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	38	0	0
T101	418	0	0	0
T131	0	38	0	0
T132	0	41	0	0
T135	0	25	0	0
T143	0	116	0	0
T180	0	42	0	0
T216	0	25	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	23	0	0
T7	945	1	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T29	0	1	0	0
T30	0	2	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T101	418	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T135	0	1	0	0
T143	0	1	0	0
T180	0	1	0	0
T216	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5326860	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5328820	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	26	0	0
T7	945	1	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T29	0	1	0	0
T30	0	2	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T80	0	1	0	0
T85	0	1	0	0
T101	418	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T143	0	1	0	0
T176	0	1	0	0
T216	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	24	0	0
T7	945	1	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T29	0	1	0	0
T30	0	2	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T101	418	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T135	0	1	0	0
T143	0	1	0	0
T176	0	1	0	0
T216	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	23	0	0
T7	945	1	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T29	0	1	0	0
T30	0	2	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T101	418	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T135	0	1	0	0
T143	0	1	0	0
T180	0	1	0	0
T216	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	23	0	0
T7	945	1	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T29	0	1	0	0
T30	0	2	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	1	0	0
T101	418	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T135	0	1	0	0
T143	0	1	0	0
T180	0	1	0	0
T216	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1876	0	0
T7	945	181	0	0
T22	46703	0	0	0
T24	603	0	0	0
T25	4716	0	0	0
T29	0	16	0	0
T30	0	84	0	0
T40	645	0	0	0
T50	403	0	0	0
T51	436	0	0	0
T52	754	0	0	0
T53	878	0	0	0
T85	0	36	0	0
T101	418	0	0	0
T131	0	36	0	0
T132	0	39	0	0
T135	0	24	0	0
T143	0	115	0	0
T180	0	40	0	0
T216	0	24	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5672	0	0
T1	20567	32	0	0
T2	1290	12	0	0
T3	1232	1	0	0
T4	406	0	0	0
T5	503	4	0	0
T6	629	2	0	0
T13	56063	3	0	0
T14	4623	19	0	0
T15	1559	9	0	0
T16	493	8	0	0
T21	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	11	0	0
T27	29212	0	0	0
T29	589	1	0	0
T30	0	1	0	0
T31	1189	0	0	0
T39	15387	0	0	0
T43	726	0	0	0
T44	740	0	0	0
T64	1821	0	0	0
T69	542	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T143	0	1	0	0
T157	0	1	0	0
T158	193887	0	0	0
T159	423	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T207	0	1	0	0
T216	0	1	0	0