Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T8,T10
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T8,T10
1	1	Covered	T1,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Covered	T8,T41,T73
1	0	Covered	T8,T45,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T39
0	1	Covered	T1,T10,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T39
1	-	Covered	T1,T10,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T10
DetectSt	168	Covered	T1,T8,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T10,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T10
DebounceSt->IdleSt	163	Covered	T80,T224,T81
DetectSt->IdleSt	186	Covered	T8,T41,T45
DetectSt->StableSt	191	Covered	T1,T10,T39
IdleSt->DebounceSt	148	Covered	T1,T8,T10
StableSt->IdleSt	206	Covered	T1,T10,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T8,T10
0	1	Covered	T1,T8,T10
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T8,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T224,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T8,T41,T45
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T39
DetectSt	-	-	-	-	0	0	-	Covered	T1,T8,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T39
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	2892	0	0
CntIncr_A	5884758	93226	0	0
CntNoWrap_A	5884758	5399666	0	0
DetectStDropOut_A	5884758	330	0	0
DetectedOut_A	5884758	78758	0	0
DetectedPulseOut_A	5884758	981	0	0
DisabledIdleSt_A	5884758	4957436	0	0
DisabledNoDetection_A	5884758	4959226	0	0
EnterDebounceSt_A	5884758	1463	0	0
EnterDetectSt_A	5884758	1429	0	0
EnterStableSt_A	5884758	981	0	0
PulseIsPulse_A	5884758	981	0	0
StayInStableSt	5884758	77669	0	0
gen_high_event_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	873	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	2892	0	0
T1	20567	28	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	26	0	0
T10	0	8	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	44	0	0
T39	0	22	0	0
T41	0	42	0	0
T45	0	24	0	0
T72	0	20	0	0
T73	0	26	0	0
T74	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	93226	0	0
T1	20567	392	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	1023	0	0
T10	0	196	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	1276	0	0
T39	0	759	0	0
T41	0	877	0	0
T45	0	656	0	0
T72	0	770	0	0
T73	0	525	0	0
T74	0	308	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5399666	0	0
T1	20567	20124	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	330	0	0
T8	10079	1	0	0
T9	21941	0	0	0
T10	16396	0	0	0
T11	29171	0	0	0
T41	4721	21	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T73	0	13	0	0
T87	0	17	0	0
T88	0	8	0	0
T89	0	5	0	0
T90	0	6	0	0
T225	0	4	0	0
T226	0	6	0	0
T227	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	78758	0	0
T1	20567	1305	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	515	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	2096	0	0
T39	0	1180	0	0
T72	0	743	0	0
T74	0	154	0	0
T228	0	2692	0	0
T229	0	1365	0	0
T230	0	364	0	0
T231	0	1701	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	981	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	4	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	22	0	0
T39	0	11	0	0
T72	0	10	0	0
T74	0	4	0	0
T228	0	28	0	0
T229	0	9	0	0
T230	0	9	0	0
T231	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	4957436	0	0
T1	20567	16538	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	4959226	0	0
T1	20567	16539	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1463	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	13	0	0
T10	0	4	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	22	0	0
T39	0	11	0	0
T41	0	21	0	0
T45	0	12	0	0
T72	0	10	0	0
T73	0	13	0	0
T74	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1429	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	13	0	0
T10	0	4	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	22	0	0
T39	0	11	0	0
T41	0	21	0	0
T45	0	12	0	0
T72	0	10	0	0
T73	0	13	0	0
T74	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	981	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	4	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	22	0	0
T39	0	11	0	0
T72	0	10	0	0
T74	0	4	0	0
T228	0	28	0	0
T229	0	9	0	0
T230	0	9	0	0
T231	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	981	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	4	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	22	0	0
T39	0	11	0	0
T72	0	10	0	0
T74	0	4	0	0
T228	0	28	0	0
T229	0	9	0	0
T230	0	9	0	0
T231	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	77669	0	0
T1	20567	1285	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	509	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	2072	0	0
T39	0	1166	0	0
T72	0	732	0	0
T74	0	149	0	0
T228	0	2657	0	0
T229	0	1355	0	0
T230	0	354	0	0
T231	0	1684	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	873	0	0
T1	20567	8	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	20	0	0
T39	0	8	0	0
T72	0	9	0	0
T74	0	3	0	0
T228	0	21	0	0
T229	0	8	0	0
T230	0	8	0	0
T231	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T8,T9
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T14,T52
1	1	Covered	T1,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T11
0	1	Covered	T27,T36,T91
1	0	Covered	T80,T81

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T11
0	1	Covered	T1,T11,T46
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T11
1	-	Covered	T1,T11,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T10
DetectSt	168	Covered	T1,T10,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T11
DebounceSt->IdleSt	163	Covered	T9,T27,T46
DetectSt->IdleSt	186	Covered	T27,T36,T91
DetectSt->StableSt	191	Covered	T1,T10,T11
IdleSt->DebounceSt	148	Covered	T1,T9,T10
StableSt->IdleSt	206	Covered	T1,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T10
0	1	Covered	T1,T9,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T27,T46
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T27,T36,T91
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T11
DetectSt	-	-	-	-	0	0	-	Covered	T1,T10,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T11,T46
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	902	0	0
CntIncr_A	5884758	49623	0	0
CntNoWrap_A	5884758	5401656	0	0
DetectStDropOut_A	5884758	54	0	0
DetectedOut_A	5884758	16455	0	0
DetectedPulseOut_A	5884758	367	0	0
DisabledIdleSt_A	5884758	5040323	0	0
DisabledNoDetection_A	5884758	5041616	0	0
EnterDebounceSt_A	5884758	479	0	0
EnterDetectSt_A	5884758	424	0	0
EnterStableSt_A	5884758	367	0	0
PulseIsPulse_A	5884758	367	0	0
StayInStableSt	5884758	16055	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	333	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	902	0	0
T1	20567	12	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	18	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	8	0	0
T27	0	15	0	0
T28	0	6	0	0
T36	0	10	0	0
T39	0	6	0	0
T46	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	49623	0	0
T1	20567	222	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	98	0	0
T10	0	126	0	0
T11	0	1620	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	188	0	0
T27	0	1271	0	0
T28	0	153	0	0
T36	0	473	0	0
T39	0	195	0	0
T46	0	1024	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5401656	0	0
T1	20567	20140	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	54	0	0
T27	29212	7	0	0
T36	24108	4	0	0
T45	15188	0	0	0
T46	34838	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T91	0	3	0	0
T94	0	9	0	0
T95	0	1	0	0
T96	0	6	0	0
T97	0	4	0	0
T98	0	2	0	0
T99	0	12	0	0
T100	0	3	0	0
T103	447	0	0	0
T104	404	0	0	0
T105	402	0	0	0
T106	433	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	16455	0	0
T1	20567	237	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	112	0	0
T11	0	112	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	26	0	0
T28	0	239	0	0
T39	0	57	0	0
T46	0	305	0	0
T72	0	86	0	0
T107	0	147	0	0
T108	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	367	0	0
T1	20567	6	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	2	0	0
T11	0	9	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	4	0	0
T28	0	3	0	0
T39	0	3	0	0
T46	0	8	0	0
T72	0	1	0	0
T107	0	5	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5040323	0	0
T1	20567	18853	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5041616	0	0
T1	20567	18855	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	479	0	0
T1	20567	6	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T11	0	9	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	4	0	0
T27	0	8	0	0
T28	0	3	0	0
T36	0	6	0	0
T39	0	3	0	0
T46	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	424	0	0
T1	20567	6	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	2	0	0
T11	0	9	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	4	0	0
T27	0	7	0	0
T28	0	3	0	0
T36	0	4	0	0
T39	0	3	0	0
T46	0	8	0	0
T107	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	367	0	0
T1	20567	6	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	2	0	0
T11	0	9	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	4	0	0
T28	0	3	0	0
T39	0	3	0	0
T46	0	8	0	0
T72	0	1	0	0
T107	0	5	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	367	0	0
T1	20567	6	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	2	0	0
T11	0	9	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	4	0	0
T28	0	3	0	0
T39	0	3	0	0
T46	0	8	0	0
T72	0	1	0	0
T107	0	5	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	16055	0	0
T1	20567	231	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	108	0	0
T11	0	103	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	22	0	0
T28	0	236	0	0
T39	0	51	0	0
T46	0	297	0	0
T72	0	85	0	0
T107	0	142	0	0
T108	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	333	0	0
T1	20567	6	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T11	0	9	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	4	0	0
T28	0	3	0	0
T32	0	4	0	0
T46	0	8	0	0
T72	0	1	0	0
T107	0	5	0	0
T108	0	1	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T8,T10
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T8,T10
1	1	Covered	T1,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Covered	T10,T41,T72
1	0	Covered	T10,T72,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T39
0	1	Covered	T1,T8,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T39
1	-	Covered	T1,T8,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T10
DetectSt	168	Covered	T1,T8,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T8,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T10
DebounceSt->IdleSt	163	Covered	T80,T224,T81
DetectSt->IdleSt	186	Covered	T10,T41,T72
DetectSt->StableSt	191	Covered	T1,T8,T39
IdleSt->DebounceSt	148	Covered	T1,T8,T10
StableSt->IdleSt	206	Covered	T1,T8,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T8,T10
0	1	Covered	T1,T8,T10
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T8,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T224,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T10,T41,T72
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T39
DetectSt	-	-	-	-	0	0	-	Covered	T1,T8,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T39
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	3092	0	0
CntIncr_A	5884758	103153	0	0
CntNoWrap_A	5884758	5399466	0	0
DetectStDropOut_A	5884758	463	0	0
DetectedOut_A	5884758	68805	0	0
DetectedPulseOut_A	5884758	853	0	0
DisabledIdleSt_A	5884758	4965721	0	0
DisabledNoDetection_A	5884758	4967508	0	0
EnterDebounceSt_A	5884758	1562	0	0
EnterDetectSt_A	5884758	1530	0	0
EnterStableSt_A	5884758	853	0	0
PulseIsPulse_A	5884758	853	0	0
StayInStableSt	5884758	67841	0	0
gen_high_event_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	742	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	3092	0	0
T1	20567	28	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	26	0	0
T10	0	20	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	20	0	0
T39	0	22	0	0
T41	0	4	0	0
T45	0	44	0	0
T72	0	52	0	0
T73	0	56	0	0
T74	0	34	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	103153	0	0
T1	20567	336	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	520	0	0
T10	0	529	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	660	0	0
T39	0	1012	0	0
T41	0	82	0	0
T45	0	968	0	0
T72	0	2014	0	0
T73	0	1150	0	0
T74	0	935	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5399466	0	0
T1	20567	20124	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	463	0	0
T10	16396	6	0	0
T11	29171	0	0	0
T12	1364	0	0	0
T29	589	0	0	0
T41	4721	2	0	0
T42	727	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T63	495	0	0	0
T69	542	0	0	0
T72	0	10	0	0
T73	0	28	0	0
T87	0	16	0	0
T88	0	22	0	0
T89	0	25	0	0
T226	0	20	0	0
T227	0	20	0	0
T232	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	68805	0	0
T1	20567	1361	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	527	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	728	0	0
T39	0	846	0	0
T45	0	2012	0	0
T74	0	1675	0	0
T228	0	856	0	0
T229	0	590	0	0
T230	0	2069	0	0
T231	0	1250	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	853	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	13	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	10	0	0
T39	0	11	0	0
T45	0	22	0	0
T74	0	17	0	0
T228	0	8	0	0
T229	0	7	0	0
T230	0	27	0	0
T231	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	4965721	0	0
T1	20567	16538	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	4967508	0	0
T1	20567	16539	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1562	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	13	0	0
T10	0	10	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	10	0	0
T39	0	11	0	0
T41	0	2	0	0
T45	0	22	0	0
T72	0	26	0	0
T73	0	28	0	0
T74	0	17	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1530	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	13	0	0
T10	0	10	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	10	0	0
T39	0	11	0	0
T41	0	2	0	0
T45	0	22	0	0
T72	0	26	0	0
T73	0	28	0	0
T74	0	17	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	853	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	13	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	10	0	0
T39	0	11	0	0
T45	0	22	0	0
T74	0	17	0	0
T228	0	8	0	0
T229	0	7	0	0
T230	0	27	0	0
T231	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	853	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	13	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	10	0	0
T39	0	11	0	0
T45	0	22	0	0
T74	0	17	0	0
T228	0	8	0	0
T229	0	7	0	0
T230	0	27	0	0
T231	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	67841	0	0
T1	20567	1341	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	514	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	716	0	0
T39	0	835	0	0
T45	0	1986	0	0
T74	0	1653	0	0
T228	0	846	0	0
T229	0	582	0	0
T230	0	2041	0	0
T231	0	1225	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	742	0	0
T1	20567	8	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	13	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	8	0	0
T39	0	11	0	0
T45	0	18	0	0
T74	0	12	0	0
T228	0	6	0	0
T229	0	6	0	0
T230	0	26	0	0
T231	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T8,T9
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T14,T52
1	1	Covered	T1,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T26,T32,T233
1	0	Covered	T80,T81

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
1	0	Covered	T81

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T11
1	-	Covered	T1,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T11
DetectSt	168	Covered	T1,T9,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T11
DebounceSt->IdleSt	163	Covered	T27,T46,T36
DetectSt->IdleSt	186	Covered	T26,T32,T233
DetectSt->StableSt	191	Covered	T1,T9,T11
IdleSt->DebounceSt	148	Covered	T1,T9,T11
StableSt->IdleSt	206	Covered	T1,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T46,T36
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T26,T32,T233
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	0	0	-	Covered	T1,T9,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	932	0	0
CntIncr_A	5884758	50575	0	0
CntNoWrap_A	5884758	5401626	0	0
DetectStDropOut_A	5884758	61	0	0
DetectedOut_A	5884758	19936	0	0
DetectedPulseOut_A	5884758	379	0	0
DisabledIdleSt_A	5884758	5050000	0	0
DisabledNoDetection_A	5884758	5051309	0	0
EnterDebounceSt_A	5884758	488	0	0
EnterDetectSt_A	5884758	444	0	0
EnterStableSt_A	5884758	379	0	0
PulseIsPulse_A	5884758	379	0	0
StayInStableSt	5884758	19534	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	352	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	932	0	0
T1	20567	10	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	12	0	0
T11	0	16	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	2	0	0
T27	0	23	0	0
T28	0	4	0	0
T36	0	17	0	0
T39	0	2	0	0
T45	0	8	0	0
T46	0	19	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	50575	0	0
T1	20567	145	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	654	0	0
T11	0	1456	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	54	0	0
T27	0	1588	0	0
T28	0	136	0	0
T36	0	775	0	0
T39	0	57	0	0
T45	0	316	0	0
T46	0	1332	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5401626	0	0
T1	20567	20142	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	61	0	0
T26	16414	1	0	0
T32	0	4	0	0
T37	710	0	0	0
T57	921	0	0	0
T72	14475	0	0	0
T97	0	4	0	0
T107	29068	0	0	0
T130	522	0	0	0
T146	0	2	0	0
T162	426	0	0	0
T163	407	0	0	0
T164	523	0	0	0
T165	426	0	0	0
T233	0	1	0	0
T234	0	2	0	0
T235	0	9	0	0
T236	0	13	0	0
T237	0	8	0	0
T238	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	19936	0	0
T1	20567	237	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	506	0	0
T11	0	84	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T27	0	351	0	0
T28	0	125	0	0
T36	0	70	0	0
T39	0	30	0	0
T45	0	165	0	0
T46	0	71	0	0
T107	0	29	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	379	0	0
T1	20567	5	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	6	0	0
T11	0	8	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T27	0	10	0	0
T28	0	2	0	0
T36	0	8	0	0
T39	0	1	0	0
T45	0	4	0	0
T46	0	9	0	0
T107	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5050000	0	0
T1	20567	18797	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5051309	0	0
T1	20567	18799	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	488	0	0
T1	20567	5	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	6	0	0
T11	0	8	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	1	0	0
T27	0	13	0	0
T28	0	2	0	0
T36	0	9	0	0
T39	0	1	0	0
T45	0	4	0	0
T46	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	444	0	0
T1	20567	5	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	6	0	0
T11	0	8	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	1	0	0
T27	0	10	0	0
T28	0	2	0	0
T36	0	8	0	0
T39	0	1	0	0
T45	0	4	0	0
T46	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	379	0	0
T1	20567	5	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	6	0	0
T11	0	8	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T27	0	10	0	0
T28	0	2	0	0
T36	0	8	0	0
T39	0	1	0	0
T45	0	4	0	0
T46	0	9	0	0
T107	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	379	0	0
T1	20567	5	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	6	0	0
T11	0	8	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T27	0	10	0	0
T28	0	2	0	0
T36	0	8	0	0
T39	0	1	0	0
T45	0	4	0	0
T46	0	9	0	0
T107	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	19534	0	0
T1	20567	232	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	500	0	0
T11	0	76	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T27	0	341	0	0
T28	0	123	0	0
T36	0	62	0	0
T39	0	29	0	0
T45	0	157	0	0
T46	0	62	0	0
T107	0	22	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	352	0	0
T1	20567	5	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	6	0	0
T11	0	8	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T27	0	10	0	0
T28	0	2	0	0
T32	0	3	0	0
T36	0	8	0	0
T46	0	9	0	0
T107	0	7	0	0
T108	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T8,T10
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T8,T10
1	1	Covered	T1,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Covered	T1,T10,T41
1	0	Covered	T1,T10,T45

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T39,T28
0	1	Covered	T8,T39,T28
1	0	Covered	T80,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T39,T28
1	-	Covered	T8,T39,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T10
DetectSt	168	Covered	T1,T8,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T8,T39,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T10
DebounceSt->IdleSt	163	Covered	T80,T224,T81
DetectSt->IdleSt	186	Covered	T1,T10,T41
DetectSt->StableSt	191	Covered	T8,T39,T28
IdleSt->DebounceSt	148	Covered	T1,T8,T10
StableSt->IdleSt	206	Covered	T8,T39,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T8,T10
0	1	Covered	T1,T8,T10
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T8,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T224,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T1,T10,T41
DetectSt	-	-	-	-	0	1	-	Covered	T8,T39,T28
DetectSt	-	-	-	-	0	0	-	Covered	T1,T8,T10
StableSt	-	-	-	-	-	-	1	Covered	T8,T39,T28
StableSt	-	-	-	-	-	-	0	Covered	T8,T39,T28
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	3293	0	0
CntIncr_A	5884758	106233	0	0
CntNoWrap_A	5884758	5399265	0	0
DetectStDropOut_A	5884758	404	0	0
DetectedOut_A	5884758	92874	0	0
DetectedPulseOut_A	5884758	1027	0	0
DisabledIdleSt_A	5884758	4949164	0	0
DisabledNoDetection_A	5884758	4950954	0	0
EnterDebounceSt_A	5884758	1660	0	0
EnterDetectSt_A	5884758	1633	0	0
EnterStableSt_A	5884758	1027	0	0
PulseIsPulse_A	5884758	1027	0	0
StayInStableSt	5884758	91739	0	0
gen_high_event_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	914	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	3293	0	0
T1	20567	62	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	56	0	0
T10	0	42	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	46	0	0
T39	0	22	0	0
T41	0	6	0	0
T45	0	44	0	0
T72	0	22	0	0
T73	0	52	0	0
T74	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	106233	0	0
T1	20567	1481	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	1484	0	0
T10	0	1116	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	1541	0	0
T39	0	836	0	0
T41	0	124	0	0
T45	0	1207	0	0
T72	0	682	0	0
T73	0	1061	0	0
T74	0	1152	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5399265	0	0
T1	20567	20090	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	404	0	0
T1	20567	11	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	14	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T41	0	3	0	0
T73	0	26	0	0
T87	0	25	0	0
T89	0	9	0	0
T90	0	9	0	0
T226	0	27	0	0
T227	0	27	0	0
T239	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	92874	0	0
T8	10079	2193	0	0
T9	21941	0	0	0
T10	16396	0	0	0
T11	29171	0	0	0
T28	0	1136	0	0
T39	0	1103	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T72	0	1352	0	0
T74	0	2885	0	0
T228	0	1869	0	0
T229	0	487	0	0
T230	0	154	0	0
T231	0	79	0	0
T240	0	228	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1027	0	0
T8	10079	28	0	0
T9	21941	0	0	0
T10	16396	0	0	0
T11	29171	0	0	0
T28	0	23	0	0
T39	0	11	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T72	0	11	0	0
T74	0	24	0	0
T228	0	22	0	0
T229	0	10	0	0
T230	0	7	0	0
T231	0	6	0	0
T240	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	4949164	0	0
T1	20567	17567	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	4950954	0	0
T1	20567	17574	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1660	0	0
T1	20567	31	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	28	0	0
T10	0	21	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	23	0	0
T39	0	11	0	0
T41	0	3	0	0
T45	0	22	0	0
T72	0	11	0	0
T73	0	26	0	0
T74	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1633	0	0
T1	20567	31	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	28	0	0
T10	0	21	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	23	0	0
T39	0	11	0	0
T41	0	3	0	0
T45	0	22	0	0
T72	0	11	0	0
T73	0	26	0	0
T74	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1027	0	0
T8	10079	28	0	0
T9	21941	0	0	0
T10	16396	0	0	0
T11	29171	0	0	0
T28	0	23	0	0
T39	0	11	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T72	0	11	0	0
T74	0	24	0	0
T228	0	22	0	0
T229	0	10	0	0
T230	0	7	0	0
T231	0	6	0	0
T240	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1027	0	0
T8	10079	28	0	0
T9	21941	0	0	0
T10	16396	0	0	0
T11	29171	0	0	0
T28	0	23	0	0
T39	0	11	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T72	0	11	0	0
T74	0	24	0	0
T228	0	22	0	0
T229	0	10	0	0
T230	0	7	0	0
T231	0	6	0	0
T240	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	91739	0	0
T8	10079	2164	0	0
T9	21941	0	0	0
T10	16396	0	0	0
T11	29171	0	0	0
T28	0	1113	0	0
T39	0	1089	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T72	0	1339	0	0
T74	0	2851	0	0
T228	0	1843	0	0
T229	0	477	0	0
T230	0	147	0	0
T231	0	73	0	0
T240	0	211	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	914	0	0
T8	10079	27	0	0
T9	21941	0	0	0
T10	16396	0	0	0
T11	29171	0	0	0
T28	0	23	0	0
T39	0	8	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T72	0	9	0	0
T74	0	14	0	0
T228	0	18	0	0
T229	0	10	0	0
T230	0	7	0	0
T231	0	6	0	0
T240	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T8,T9
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T11
1	0	Covered	T1,T14,T52
1	1	Covered	T8,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T11
0	1	Covered	T46,T36,T107
1	0	Covered	T80,T81

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T11
0	1	Covered	T8,T9,T11
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T11
1	-	Covered	T8,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T11
DetectSt	168	Covered	T8,T9,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T8,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T11
DebounceSt->IdleSt	163	Covered	T9,T27,T46
DetectSt->IdleSt	186	Covered	T46,T36,T107
DetectSt->StableSt	191	Covered	T8,T9,T11
IdleSt->DebounceSt	148	Covered	T8,T9,T11
StableSt->IdleSt	206	Covered	T8,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T11
0	1	Covered	T8,T9,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T27,T46
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T46,T36,T107
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T11
DetectSt	-	-	-	-	0	0	-	Covered	T8,T9,T11
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	771	0	0
CntIncr_A	5884758	42520	0	0
CntNoWrap_A	5884758	5401787	0	0
DetectStDropOut_A	5884758	54	0	0
DetectedOut_A	5884758	14014	0	0
DetectedPulseOut_A	5884758	305	0	0
DisabledIdleSt_A	5884758	5025048	0	0
DisabledNoDetection_A	5884758	5026364	0	0
EnterDebounceSt_A	5884758	408	0	0
EnterDetectSt_A	5884758	363	0	0
EnterStableSt_A	5884758	305	0	0
PulseIsPulse_A	5884758	305	0	0
StayInStableSt	5884758	13690	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	281	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	771	0	0
T8	10079	2	0	0
T9	21941	7	0	0
T10	16396	0	0	0
T11	29171	8	0	0
T26	0	5	0	0
T27	0	3	0	0
T28	0	4	0	0
T36	0	4	0	0
T39	0	6	0	0
T41	4721	0	0	0
T46	0	19	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T107	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	42520	0	0
T8	10079	63	0	0
T9	21941	593	0	0
T10	16396	0	0	0
T11	29171	664	0	0
T26	0	70	0	0
T27	0	163	0	0
T28	0	112	0	0
T36	0	191	0	0
T39	0	183	0	0
T41	4721	0	0	0
T46	0	1403	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T107	0	462	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5401787	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	54	0	0
T20	1397	0	0	0
T26	16414	0	0	0
T28	13159	0	0	0
T32	0	6	0	0
T36	24108	2	0	0
T46	34838	9	0	0
T65	489	0	0	0
T99	0	4	0	0
T107	0	3	0	0
T126	509	0	0	0
T127	527	0	0	0
T128	410	0	0	0
T129	432	0	0	0
T186	0	11	0	0
T236	0	10	0	0
T241	0	3	0	0
T242	0	4	0	0
T243	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	14014	0	0
T8	10079	61	0	0
T9	21941	86	0	0
T10	16396	0	0	0
T11	29171	105	0	0
T26	0	51	0	0
T27	0	83	0	0
T28	0	149	0	0
T32	0	132	0	0
T39	0	74	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T72	0	129	0	0
T108	0	282	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	305	0	0
T8	10079	1	0	0
T9	21941	3	0	0
T10	16396	0	0	0
T11	29171	4	0	0
T26	0	2	0	0
T27	0	1	0	0
T28	0	2	0	0
T32	0	5	0	0
T39	0	3	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T72	0	2	0	0
T108	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5025048	0	0
T1	20567	20152	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5026364	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	408	0	0
T8	10079	1	0	0
T9	21941	4	0	0
T10	16396	0	0	0
T11	29171	4	0	0
T26	0	3	0	0
T27	0	2	0	0
T28	0	2	0	0
T36	0	2	0	0
T39	0	3	0	0
T41	4721	0	0	0
T46	0	10	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T107	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	363	0	0
T8	10079	1	0	0
T9	21941	3	0	0
T10	16396	0	0	0
T11	29171	4	0	0
T26	0	2	0	0
T27	0	1	0	0
T28	0	2	0	0
T36	0	2	0	0
T39	0	3	0	0
T41	4721	0	0	0
T46	0	9	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T107	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	305	0	0
T8	10079	1	0	0
T9	21941	3	0	0
T10	16396	0	0	0
T11	29171	4	0	0
T26	0	2	0	0
T27	0	1	0	0
T28	0	2	0	0
T32	0	5	0	0
T39	0	3	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T72	0	2	0	0
T108	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	305	0	0
T8	10079	1	0	0
T9	21941	3	0	0
T10	16396	0	0	0
T11	29171	4	0	0
T26	0	2	0	0
T27	0	1	0	0
T28	0	2	0	0
T32	0	5	0	0
T39	0	3	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T72	0	2	0	0
T108	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	13690	0	0
T8	10079	60	0	0
T9	21941	83	0	0
T10	16396	0	0	0
T11	29171	101	0	0
T26	0	49	0	0
T27	0	82	0	0
T28	0	147	0	0
T32	0	127	0	0
T39	0	70	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T72	0	127	0	0
T108	0	278	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	281	0	0
T8	10079	1	0	0
T9	21941	3	0	0
T10	16396	0	0	0
T11	29171	4	0	0
T26	0	2	0	0
T27	0	1	0	0
T28	0	2	0	0
T32	0	5	0	0
T39	0	1	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T72	0	2	0	0
T108	0	4	0	0