Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T8,T10
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T8,T10
1	1	Covered	T1,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Covered	T41,T45,T73
1	0	Covered	T45,T88,T232

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Covered	T1,T8,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T10
1	-	Covered	T1,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T10
DetectSt	168	Covered	T1,T8,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T10
DebounceSt->IdleSt	163	Covered	T80,T224,T81
DetectSt->IdleSt	186	Covered	T41,T45,T73
DetectSt->StableSt	191	Covered	T1,T8,T10
IdleSt->DebounceSt	148	Covered	T1,T8,T10
StableSt->IdleSt	206	Covered	T1,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T8,T10
0	1	Covered	T1,T8,T10
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T8,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T224,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T41,T45,T73
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T8,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	2971	0	0
CntIncr_A	5884758	96704	0	0
CntNoWrap_A	5884758	5399587	0	0
DetectStDropOut_A	5884758	437	0	0
DetectedOut_A	5884758	68905	0	0
DetectedPulseOut_A	5884758	815	0	0
DisabledIdleSt_A	5884758	4968079	0	0
DisabledNoDetection_A	5884758	4969893	0	0
EnterDebounceSt_A	5884758	1510	0	0
EnterDetectSt_A	5884758	1461	0	0
EnterStableSt_A	5884758	815	0	0
PulseIsPulse_A	5884758	815	0	0
StayInStableSt	5884758	68006	0	0
gen_high_event_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	731	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	2971	0	0
T1	20567	28	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	14	0	0
T10	0	10	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	22	0	0
T39	0	12	0	0
T41	0	14	0	0
T45	0	48	0	0
T72	0	22	0	0
T73	0	52	0	0
T74	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	96704	0	0
T1	20567	336	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	497	0	0
T10	0	250	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	528	0	0
T39	0	528	0	0
T41	0	289	0	0
T45	0	1302	0	0
T72	0	693	0	0
T73	0	1060	0	0
T74	0	420	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5399587	0	0
T1	20567	20124	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	437	0	0
T12	1364	0	0	0
T29	589	0	0	0
T31	1189	0	0	0
T41	4721	7	0	0
T42	727	0	0	0
T43	726	0	0	0
T45	0	15	0	0
T64	1821	0	0	0
T69	542	0	0	0
T73	0	26	0	0
T87	0	25	0	0
T88	0	3	0	0
T89	0	5	0	0
T90	0	16	0	0
T158	193887	0	0	0
T159	423	0	0	0
T226	0	25	0	0
T227	0	29	0	0
T239	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	68905	0	0
T1	20567	1186	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	65	0	0
T10	0	543	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	545	0	0
T39	0	232	0	0
T72	0	1041	0	0
T74	0	411	0	0
T228	0	2769	0	0
T229	0	585	0	0
T230	0	1772	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	815	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	7	0	0
T10	0	5	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	11	0	0
T39	0	6	0	0
T72	0	11	0	0
T74	0	7	0	0
T228	0	24	0	0
T229	0	8	0	0
T230	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	4968079	0	0
T1	20567	16711	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	4969893	0	0
T1	20567	16714	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1510	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	7	0	0
T10	0	5	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	11	0	0
T39	0	6	0	0
T41	0	7	0	0
T45	0	24	0	0
T72	0	11	0	0
T73	0	26	0	0
T74	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	1461	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	7	0	0
T10	0	5	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	11	0	0
T39	0	6	0	0
T41	0	7	0	0
T45	0	24	0	0
T72	0	11	0	0
T73	0	26	0	0
T74	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	815	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	7	0	0
T10	0	5	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	11	0	0
T39	0	6	0	0
T72	0	11	0	0
T74	0	7	0	0
T228	0	24	0	0
T229	0	8	0	0
T230	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	815	0	0
T1	20567	14	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	7	0	0
T10	0	5	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	11	0	0
T39	0	6	0	0
T72	0	11	0	0
T74	0	7	0	0
T228	0	24	0	0
T229	0	8	0	0
T230	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	68006	0	0
T1	20567	1168	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	58	0	0
T10	0	535	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	534	0	0
T39	0	225	0	0
T72	0	1030	0	0
T74	0	403	0	0
T228	0	2741	0	0
T229	0	577	0	0
T230	0	1744	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	731	0	0
T1	20567	10	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T8	0	7	0	0
T10	0	2	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T28	0	11	0	0
T39	0	5	0	0
T72	0	11	0	0
T74	0	6	0	0
T228	0	20	0	0
T229	0	8	0	0
T230	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T8,T9
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T14,T52
1	1	Covered	T1,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T10
0	1	Covered	T9,T32,T244
1	0	Covered	T80,T81

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T11
0	1	Covered	T1,T10,T11
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T11
1	-	Covered	T1,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T10
DetectSt	168	Covered	T1,T9,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T10
DebounceSt->IdleSt	163	Covered	T27,T46,T26
DetectSt->IdleSt	186	Covered	T9,T32,T244
DetectSt->StableSt	191	Covered	T1,T10,T11
IdleSt->DebounceSt	148	Covered	T1,T9,T10
StableSt->IdleSt	206	Covered	T1,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T10
0	1	Covered	T1,T9,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T46,T26
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T9,T32,T244
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T11
DetectSt	-	-	-	-	0	0	-	Covered	T1,T9,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5884758	765	0	0
CntIncr_A	5884758	40689	0	0
CntNoWrap_A	5884758	5401793	0	0
DetectStDropOut_A	5884758	54	0	0
DetectedOut_A	5884758	14850	0	0
DetectedPulseOut_A	5884758	310	0	0
DisabledIdleSt_A	5884758	5060162	0	0
DisabledNoDetection_A	5884758	5061523	0	0
EnterDebounceSt_A	5884758	397	0	0
EnterDetectSt_A	5884758	369	0	0
EnterStableSt_A	5884758	310	0	0
PulseIsPulse_A	5884758	310	0	0
StayInStableSt	5884758	14531	0	0
gen_high_level_sva.HighLevelEvent_A	5884758	5404547	0	0
gen_not_sticky_sva.StableStDropOut_A	5884758	298	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	765	0	0
T1	20567	8	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	2	0	0
T10	0	6	0	0
T11	0	6	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	19	0	0
T27	0	5	0	0
T36	0	6	0	0
T46	0	23	0	0
T72	0	8	0	0
T107	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	40689	0	0
T1	20567	160	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	194	0	0
T10	0	261	0	0
T11	0	510	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	401	0	0
T27	0	408	0	0
T36	0	246	0	0
T46	0	1282	0	0
T72	0	256	0	0
T107	0	91	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5401793	0	0
T1	20567	20144	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	54	0	0
T9	21941	1	0	0
T10	16396	0	0	0
T11	29171	0	0	0
T12	1364	0	0	0
T32	0	12	0	0
T41	4721	0	0	0
T55	1044	0	0	0
T56	822	0	0	0
T62	494	0	0	0
T63	495	0	0	0
T68	526	0	0	0
T146	0	6	0	0
T241	0	2	0	0
T242	0	5	0	0
T244	0	3	0	0
T245	0	8	0	0
T246	0	5	0	0
T247	0	4	0	0
T248	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	14850	0	0
T1	20567	146	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	101	0	0
T11	0	66	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	103	0	0
T27	0	10	0	0
T32	0	12	0	0
T36	0	41	0	0
T46	0	422	0	0
T72	0	306	0	0
T107	0	63	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	310	0	0
T1	20567	4	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	3	0	0
T11	0	3	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	9	0	0
T27	0	2	0	0
T32	0	1	0	0
T36	0	3	0	0
T46	0	11	0	0
T72	0	4	0	0
T107	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5060162	0	0
T1	20567	18970	0	0
T2	1290	889	0	0
T3	1232	831	0	0
T4	406	5	0	0
T5	503	102	0	0
T6	629	228	0	0
T13	56063	55662	0	0
T14	4623	632	0	0
T15	1559	1158	0	0
T16	493	92	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5061523	0	0
T1	20567	18974	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	397	0	0
T1	20567	4	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	1	0	0
T10	0	3	0	0
T11	0	3	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	10	0	0
T27	0	3	0	0
T36	0	3	0	0
T46	0	12	0	0
T72	0	4	0	0
T107	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	369	0	0
T1	20567	4	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T9	0	1	0	0
T10	0	3	0	0
T11	0	3	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	9	0	0
T27	0	2	0	0
T36	0	3	0	0
T46	0	11	0	0
T72	0	4	0	0
T107	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	310	0	0
T1	20567	4	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	3	0	0
T11	0	3	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	9	0	0
T27	0	2	0	0
T32	0	1	0	0
T36	0	3	0	0
T46	0	11	0	0
T72	0	4	0	0
T107	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	310	0	0
T1	20567	4	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	3	0	0
T11	0	3	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	9	0	0
T27	0	2	0	0
T32	0	1	0	0
T36	0	3	0	0
T46	0	11	0	0
T72	0	4	0	0
T107	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	14531	0	0
T1	20567	142	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	98	0	0
T11	0	63	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	94	0	0
T27	0	8	0	0
T32	0	11	0	0
T36	0	38	0	0
T46	0	411	0	0
T72	0	302	0	0
T107	0	62	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	5404547	0	0
T1	20567	20160	0	0
T2	1290	890	0	0
T3	1232	832	0	0
T4	406	6	0	0
T5	503	103	0	0
T6	629	229	0	0
T13	56063	55663	0	0
T14	4623	646	0	0
T15	1559	1159	0	0
T16	493	93	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5884758	298	0	0
T1	20567	4	0	0
T2	1290	0	0	0
T3	1232	0	0	0
T4	406	0	0	0
T5	503	0	0	0
T6	629	0	0	0
T10	0	3	0	0
T11	0	3	0	0
T13	56063	0	0	0
T14	4623	0	0	0
T15	1559	0	0	0
T16	493	0	0	0
T26	0	9	0	0
T27	0	2	0	0
T32	0	1	0	0
T36	0	3	0	0
T46	0	11	0	0
T72	0	3	0	0
T107	0	1	0	0