Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1083867665	11360	0	0
auto_block_debounce_ctl_rd_A	1083867665	2342	0	0
auto_block_out_ctl_rd_A	1083867665	2766	0	0
com_det_ctl_0_rd_A	1083867665	4392	0	0
com_det_ctl_1_rd_A	1083867665	4374	0	0
com_det_ctl_2_rd_A	1083867665	4371	0	0
com_det_ctl_3_rd_A	1083867665	4294	0	0
com_out_ctl_0_rd_A	1083867665	4292	0	0
com_out_ctl_1_rd_A	1083867665	4637	0	0
com_out_ctl_2_rd_A	1083867665	4703	0	0
com_out_ctl_3_rd_A	1083867665	4677	0	0
com_pre_det_ctl_0_rd_A	1083867665	2140	0	0
com_pre_det_ctl_1_rd_A	1083867665	2064	0	0
com_pre_det_ctl_2_rd_A	1083867665	2085	0	0
com_pre_det_ctl_3_rd_A	1083867665	2165	0	0
com_pre_sel_ctl_0_rd_A	1083867665	4454	0	0
com_pre_sel_ctl_1_rd_A	1083867665	4621	0	0
com_pre_sel_ctl_2_rd_A	1083867665	4771	0	0
com_pre_sel_ctl_3_rd_A	1083867665	5023	0	0
com_sel_ctl_0_rd_A	1083867665	4636	0	0
com_sel_ctl_1_rd_A	1083867665	4669	0	0
com_sel_ctl_2_rd_A	1083867665	4760	0	0
com_sel_ctl_3_rd_A	1083867665	4780	0	0
ec_rst_ctl_rd_A	1083867665	2854	0	0
intr_enable_rd_A	1083867665	2390	0	0
key_intr_ctl_rd_A	1083867665	3303	0	0
key_intr_debounce_ctl_rd_A	1083867665	2109	0	0
key_invert_ctl_rd_A	1083867665	4963	0	0
pin_allowed_ctl_rd_A	1083867665	4488	0	0
pin_out_ctl_rd_A	1083867665	4186	0	0
pin_out_value_rd_A	1083867665	4133	0	0
regwen_rd_A	1083867665	2187	0	0
ulp_ac_debounce_ctl_rd_A	1083867665	2083	0	0
ulp_ctl_rd_A	1083867665	2265	0	0
ulp_lid_debounce_ctl_rd_A	1083867665	2249	0	0
ulp_pwrb_debounce_ctl_rd_A	1083867665	2149	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	11360	0	0
T3	33358	0	0	0
T6	46754	0	0	0
T7	178262	0	0	0
T14	624106	17	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T21	29951	0	0	0
T24	150924	0	0	0
T25	0	8	0	0
T50	195838	0	0	0
T51	43674	0	0	0
T52	0	8	0	0
T53	0	10	0	0
T76	0	24	0	0
T118	0	11	0	0
T184	0	13	0	0
T277	0	15	0	0
T278	0	4	0	0
T279	0	13	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2342	0	0
T8	125995	0	0	0
T9	274273	0	0	0
T10	311530	0	0	0
T25	486882	0	0	0
T40	90363	21	0	0
T44	0	6	0	0
T47	0	7	0	0
T48	0	10	0	0
T62	247641	0	0	0
T63	59448	0	0	0
T68	57875	0	0	0
T101	209570	0	0	0
T102	97449	0	0	0
T119	0	15	0	0
T143	0	21	0	0
T184	0	15	0	0
T278	0	39	0	0
T280	0	4	0	0
T281	0	1	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2766	0	0
T8	125995	0	0	0
T9	274273	0	0	0
T10	311530	0	0	0
T25	486882	0	0	0
T40	90363	7	0	0
T44	0	10	0	0
T47	0	12	0	0
T48	0	8	0	0
T49	0	7	0	0
T62	247641	0	0	0
T63	59448	0	0	0
T68	57875	0	0	0
T101	209570	0	0	0
T102	97449	0	0	0
T119	0	9	0	0
T143	0	30	0	0
T184	0	21	0	0
T278	0	33	0	0
T281	0	2	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4392	0	0
T1	524468	56	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	44	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	51	0	0
T74	0	46	0	0
T107	0	48	0	0
T108	0	68	0	0
T229	0	51	0	0
T230	0	39	0	0
T278	0	25	0	0
T282	0	56	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4374	0	0
T1	524468	49	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	42	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	58	0	0
T74	0	61	0	0
T107	0	74	0	0
T108	0	68	0	0
T229	0	48	0	0
T230	0	25	0	0
T278	0	23	0	0
T282	0	37	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4371	0	0
T1	524468	61	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	39	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	53	0	0
T74	0	72	0	0
T107	0	64	0	0
T108	0	90	0	0
T229	0	60	0	0
T230	0	45	0	0
T278	0	27	0	0
T282	0	31	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4294	0	0
T1	524468	70	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	36	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	46	0	0
T74	0	73	0	0
T107	0	67	0	0
T108	0	86	0	0
T229	0	55	0	0
T230	0	27	0	0
T278	0	14	0	0
T282	0	60	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4292	0	0
T1	524468	33	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	41	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	30	0	0
T74	0	64	0	0
T107	0	70	0	0
T108	0	71	0	0
T229	0	42	0	0
T230	0	21	0	0
T278	0	28	0	0
T282	0	37	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4637	0	0
T1	524468	36	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	37	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	47	0	0
T74	0	57	0	0
T107	0	63	0	0
T108	0	70	0	0
T229	0	43	0	0
T230	0	47	0	0
T278	0	32	0	0
T282	0	24	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4703	0	0
T1	524468	42	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	45	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	32	0	0
T74	0	84	0	0
T107	0	63	0	0
T108	0	78	0	0
T229	0	48	0	0
T230	0	40	0	0
T278	0	31	0	0
T282	0	49	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4677	0	0
T1	524468	26	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	41	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	45	0	0
T74	0	100	0	0
T107	0	78	0	0
T108	0	69	0	0
T229	0	55	0	0
T230	0	32	0	0
T278	0	22	0	0
T282	0	27	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2140	0	0
T49	470465	0	0	0
T184	0	22	0	0
T228	659970	0	0	0
T229	108036	0	0	0
T230	162323	0	0	0
T278	455092	41	0	0
T283	0	35	0	0
T284	0	13	0	0
T285	0	58	0	0
T286	0	4	0	0
T287	0	24	0	0
T288	0	26	0	0
T289	0	28	0	0
T290	0	28	0	0
T291	234362	0	0	0
T292	248632	0	0	0
T293	202436	0	0	0
T294	287699	0	0	0
T295	105806	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2064	0	0
T49	470465	0	0	0
T184	0	29	0	0
T228	659970	0	0	0
T229	108036	0	0	0
T230	162323	0	0	0
T278	455092	26	0	0
T283	0	42	0	0
T284	0	15	0	0
T285	0	45	0	0
T286	0	9	0	0
T287	0	14	0	0
T288	0	28	0	0
T289	0	30	0	0
T290	0	21	0	0
T291	234362	0	0	0
T292	248632	0	0	0
T293	202436	0	0	0
T294	287699	0	0	0
T295	105806	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2085	0	0
T49	470465	0	0	0
T184	0	14	0	0
T228	659970	0	0	0
T229	108036	0	0	0
T230	162323	0	0	0
T278	455092	47	0	0
T283	0	33	0	0
T284	0	21	0	0
T285	0	36	0	0
T286	0	15	0	0
T287	0	32	0	0
T288	0	21	0	0
T289	0	23	0	0
T290	0	5	0	0
T291	234362	0	0	0
T292	248632	0	0	0
T293	202436	0	0	0
T294	287699	0	0	0
T295	105806	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2165	0	0
T49	470465	0	0	0
T184	0	15	0	0
T228	659970	0	0	0
T229	108036	0	0	0
T230	162323	0	0	0
T278	455092	32	0	0
T283	0	32	0	0
T284	0	16	0	0
T285	0	22	0	0
T286	0	25	0	0
T287	0	24	0	0
T288	0	23	0	0
T289	0	20	0	0
T290	0	29	0	0
T291	234362	0	0	0
T292	248632	0	0	0
T293	202436	0	0	0
T294	287699	0	0	0
T295	105806	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4454	0	0
T1	524468	36	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	44	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	34	0	0
T74	0	62	0	0
T107	0	63	0	0
T108	0	62	0	0
T229	0	43	0	0
T230	0	15	0	0
T278	0	30	0	0
T282	0	17	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4621	0	0
T1	524468	54	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	38	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	57	0	0
T74	0	83	0	0
T107	0	76	0	0
T108	0	77	0	0
T229	0	41	0	0
T230	0	33	0	0
T278	0	50	0	0
T282	0	33	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4771	0	0
T1	524468	49	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	29	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	49	0	0
T74	0	60	0	0
T107	0	77	0	0
T108	0	52	0	0
T229	0	53	0	0
T230	0	29	0	0
T278	0	32	0	0
T282	0	39	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	5023	0	0
T1	524468	39	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	28	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	52	0	0
T74	0	69	0	0
T107	0	92	0	0
T108	0	89	0	0
T229	0	38	0	0
T230	0	41	0	0
T278	0	28	0	0
T282	0	45	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4636	0	0
T1	524468	35	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	43	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	47	0	0
T74	0	67	0	0
T107	0	69	0	0
T108	0	55	0	0
T229	0	53	0	0
T230	0	32	0	0
T278	0	32	0	0
T282	0	50	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4669	0	0
T1	524468	50	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	47	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	59	0	0
T74	0	52	0	0
T107	0	67	0	0
T108	0	83	0	0
T229	0	72	0	0
T230	0	25	0	0
T278	0	39	0	0
T282	0	55	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4760	0	0
T1	524468	34	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	43	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	41	0	0
T74	0	56	0	0
T107	0	69	0	0
T108	0	72	0	0
T229	0	56	0	0
T230	0	24	0	0
T278	0	37	0	0
T282	0	41	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4780	0	0
T1	524468	35	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	49	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	41	0	0
T74	0	63	0	0
T107	0	73	0	0
T108	0	76	0	0
T229	0	53	0	0
T230	0	38	0	0
T278	0	35	0	0
T282	0	24	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2854	0	0
T1	524468	4	0	0
T2	69727	0	0	0
T3	33358	0	0	0
T4	48750	0	0	0
T5	123379	0	0	0
T6	46754	0	0	0
T10	0	24	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T49	0	51	0	0
T74	0	32	0	0
T107	0	57	0	0
T108	0	25	0	0
T190	0	4	0	0
T229	0	7	0	0
T278	0	18	0	0
T282	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2390	0	0
T33	0	21	0	0
T49	470465	0	0	0
T184	0	11	0	0
T228	659970	0	0	0
T229	108036	0	0	0
T230	162323	0	0	0
T278	455092	23	0	0
T283	0	54	0	0
T284	0	16	0	0
T285	0	36	0	0
T286	0	9	0	0
T287	0	9	0	0
T288	0	12	0	0
T291	234362	0	0	0
T292	248632	0	0	0
T293	202436	0	0	0
T294	287699	0	0	0
T295	105806	0	0	0
T296	0	12	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	3303	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	121655	1	0	0
T57	230509	0	0	0
T72	347410	0	0	0
T108	698096	0	0	0
T131	0	7	0	0
T143	0	2	0	0
T162	53288	0	0	0
T163	61095	0	0	0
T164	96733	0	0	0
T165	53376	0	0	0
T166	53143	0	0	0
T167	212303	0	0	0
T184	0	20	0	0
T216	0	1	0	0
T278	0	31	0	0
T283	0	32	0	0
T284	0	12	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2109	0	0
T49	470465	0	0	0
T184	0	30	0	0
T228	659970	0	0	0
T229	108036	0	0	0
T230	162323	0	0	0
T278	455092	29	0	0
T283	0	36	0	0
T284	0	21	0	0
T285	0	37	0	0
T286	0	16	0	0
T287	0	7	0	0
T288	0	29	0	0
T289	0	21	0	0
T290	0	14	0	0
T291	234362	0	0	0
T292	248632	0	0	0
T293	202436	0	0	0
T294	287699	0	0	0
T295	105806	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4963	0	0
T7	178262	0	0	0
T16	241789	63	0	0
T21	29951	70	0	0
T22	256871	0	0	0
T24	150924	0	0	0
T40	90363	0	0	0
T49	0	124	0	0
T50	195838	0	0	0
T51	43674	0	0	0
T52	362413	0	0	0
T53	430641	0	0	0
T62	0	66	0	0
T66	0	68	0	0
T184	0	16	0	0
T278	0	40	0	0
T297	0	77	0	0
T298	0	74	0	0
T299	0	63	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4488	0	0
T26	402158	0	0	0
T37	121655	0	0	0
T107	142435	0	0	0
T126	35654	65	0	0
T127	60630	0	0	0
T128	100556	0	0	0
T129	216248	0	0	0
T130	253588	0	0	0
T162	53288	0	0	0
T163	61095	0	0	0
T184	0	24	0	0
T278	0	34	0	0
T283	0	166	0	0
T284	0	34	0	0
T285	0	43	0	0
T300	0	80	0	0
T301	0	92	0	0
T302	0	79	0	0
T303	0	70	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4186	0	0
T26	402158	0	0	0
T37	121655	0	0	0
T107	142435	0	0	0
T126	35654	50	0	0
T127	60630	0	0	0
T128	100556	0	0	0
T129	216248	0	0	0
T130	253588	0	0	0
T162	53288	0	0	0
T163	61095	0	0	0
T184	0	22	0	0
T278	0	23	0	0
T283	0	180	0	0
T284	0	19	0	0
T285	0	40	0	0
T300	0	53	0	0
T301	0	56	0	0
T302	0	71	0	0
T303	0	75	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	4133	0	0
T26	402158	0	0	0
T37	121655	0	0	0
T107	142435	0	0	0
T126	35654	77	0	0
T127	60630	0	0	0
T128	100556	0	0	0
T129	216248	0	0	0
T130	253588	0	0	0
T162	53288	0	0	0
T163	61095	0	0	0
T184	0	5	0	0
T278	0	39	0	0
T283	0	174	0	0
T284	0	26	0	0
T285	0	40	0	0
T300	0	68	0	0
T301	0	59	0	0
T302	0	58	0	0
T303	0	95	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2187	0	0
T49	470465	0	0	0
T184	0	39	0	0
T228	659970	0	0	0
T229	108036	0	0	0
T230	162323	0	0	0
T278	455092	43	0	0
T283	0	49	0	0
T284	0	18	0	0
T285	0	38	0	0
T286	0	5	0	0
T287	0	13	0	0
T288	0	19	0	0
T289	0	26	0	0
T290	0	18	0	0
T291	234362	0	0	0
T292	248632	0	0	0
T293	202436	0	0	0
T294	287699	0	0	0
T295	105806	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2083	0	0
T2	69727	5	0	0
T3	33358	0	0	0
T6	46754	0	0	0
T7	178262	0	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T20	0	5	0	0
T21	29951	0	0	0
T33	0	4	0	0
T50	195838	0	0	0
T60	0	1	0	0
T79	0	6	0	0
T143	0	3	0	0
T184	0	13	0	0
T278	0	30	0	0
T283	0	44	0	0
T284	0	13	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2265	0	0
T2	69727	5	0	0
T3	33358	0	0	0
T6	46754	0	0	0
T7	178262	0	0	0
T12	0	5	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T21	29951	0	0	0
T33	0	2	0	0
T50	195838	0	0	0
T60	0	6	0	0
T79	0	5	0	0
T143	0	3	0	0
T184	0	29	0	0
T278	0	28	0	0
T283	0	49	0	0
T284	0	31	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2249	0	0
T2	69727	17	0	0
T3	33358	0	0	0
T6	46754	0	0	0
T7	178262	0	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T21	29951	0	0	0
T33	0	4	0	0
T50	195838	0	0	0
T60	0	5	0	0
T79	0	4	0	0
T143	0	7	0	0
T184	0	18	0	0
T278	0	35	0	0
T283	0	46	0	0
T284	0	31	0	0
T304	0	10	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083867665	2149	0	0
T2	69727	8	0	0
T3	33358	0	0	0
T6	46754	0	0	0
T7	178262	0	0	0
T12	0	5	0	0
T13	196222	0	0	0
T14	624106	0	0	0
T15	199203	0	0	0
T16	241789	0	0	0
T20	0	3	0	0
T21	29951	0	0	0
T33	0	2	0	0
T50	195838	0	0	0
T143	0	1	0	0
T184	0	23	0	0
T278	0	42	0	0
T283	0	29	0	0
T284	0	38	0	0
T304	0	3	0	0