Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1028010
Category 01028010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1028010
Severity 01028010

Summary for Assertions
NUMBERPERCENT
Total Number1028100.00
Uncovered111.07
Success101798.93
Failure00.00
Incomplete10.10
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00
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ASSERTIONS   CATEGORY   SEVERITY   ATTEMPTS   REAL SUCCESSES   FAILURES   INCOMPLETE   
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.DisabledNoDetection_A 007758203617914500
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.EnterDebounceSt_A 0077582035600
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.EnterDetectSt_A 0077582033900
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.EnterStableSt_A 0077582033900
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.PulseIsPulse_A 0077582033900
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.StayInStableSt 00775820316838200
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.gen_high_event_sva.HighLevelEvent_A 007758203728547500
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.gen_high_level_sva.HighLevelEvent_A 007758203728547500
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.gen_sticky_sva.StableStDropOut_A 00775820385189900
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.CntClr_A 00775820311800
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.CntIncr_A 00775820312268100
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.CntNoWrap_A 007758203728344400
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.DetectStDropOut_A 0077582031100
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.DetectedOut_A 00775820338059800
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.DetectedPulseOut_A 0077582033500
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.DisabledIdleSt_A 007758203617723300
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.DisabledNoDetection_A 007758203617914500
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.EnterDebounceSt_A 0077582037300
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.EnterDetectSt_A 0077582034600
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.EnterStableSt_A 0077582033500
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.PulseIsPulse_A 0077582033500
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.StayInStableSt 00775820338056300
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.gen_high_level_sva.HighLevelEvent_A 007758203728547500
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.gen_sticky_sva.StableStDropOut_A 00775820338955000
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.CntClr_A 00775820311900
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.CntIncr_A 00775820310013500
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.CntNoWrap_A 007758203728344300
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.DetectStDropOut_A 007758203900
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.DetectedOut_A 00775820329553500
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.DetectedPulseOut_A 0077582033200
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.DisabledIdleSt_A 007758203617723300
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.DisabledNoDetection_A 007758203617914500
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.EnterDebounceSt_A 0077582037900
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.EnterDetectSt_A 0077582034100
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.EnterStableSt_A 0077582033200
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.PulseIsPulse_A 0077582033200
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.StayInStableSt 00775820329550300
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.gen_edge_to_low_event_sva.EdgeToLowEvent_A 007758203550100
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.gen_low_level_sva.LowLevelEvent_A 007758203728547500
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.gen_sticky_sva.StableStDropOut_A 00775820345697500

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 0079997036110912

Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCES   CATEGORY   SEVERITY   ATTEMPTS   ALL MATCHES   FIRST MATCHES   INCOMPLETE   SRC   
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0012223373444554874554870
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 001222337344422042200
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 00122233734410975109750
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 001222337344820782070
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00122233734410556105560
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 001222337344653265320
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 001222337344519451940
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 001222337344476547650
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 00122233734410211102110
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0012223373449174191741843

Cover Sequences First Matches:
COVER SEQUENCES   CATEGORY   SEVERITY   ATTEMPTS   ALL MATCHES   FIRST MATCHES   INCOMPLETE   SRC   
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0012223373444554874554870
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 001222337344422042200
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 00122233734410975109750
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 001222337344820782070
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00122233734410556105560
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 001222337344653265320
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 001222337344519451940
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 001222337344476547650
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 00122233734410211102110
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0012223373449174191741843