Go previous page

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.DisabledNoDetection_A	0	0	7758203	6179145	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.EnterDebounceSt_A	0	0	7758203	56	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.EnterDetectSt_A	0	0	7758203	39	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.EnterStableSt_A	0	0	7758203	39	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.PulseIsPulse_A	0	0	7758203	39	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.StayInStableSt	0	0	7758203	168382	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.gen_high_event_sva.HighLevelEvent_A	0	0	7758203	7285475	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.gen_high_level_sva.HighLevelEvent_A	0	0	7758203	7285475	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.gen_sticky_sva.StableStDropOut_A	0	0	7758203	851899	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.CntClr_A	0	0	7758203	118	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.CntIncr_A	0	0	7758203	122681	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.CntNoWrap_A	0	0	7758203	7283444	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.DetectStDropOut_A	0	0	7758203	11	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.DetectedOut_A	0	0	7758203	380598	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.DetectedPulseOut_A	0	0	7758203	35	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.DisabledIdleSt_A	0	0	7758203	6177233	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.DisabledNoDetection_A	0	0	7758203	6179145	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.EnterDebounceSt_A	0	0	7758203	73	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.EnterDetectSt_A	0	0	7758203	46	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.EnterStableSt_A	0	0	7758203	35	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.PulseIsPulse_A	0	0	7758203	35	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.StayInStableSt	0	0	7758203	380563	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.gen_high_level_sva.HighLevelEvent_A	0	0	7758203	7285475	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open.gen_sticky_sva.StableStDropOut_A	0	0	7758203	389550	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.CntClr_A	0	0	7758203	119	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.CntIncr_A	0	0	7758203	100135	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.CntNoWrap_A	0	0	7758203	7283443	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.DetectStDropOut_A	0	0	7758203	9	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.DetectedOut_A	0	0	7758203	295535	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.DetectedPulseOut_A	0	0	7758203	32	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.DisabledIdleSt_A	0	0	7758203	6177233	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.DisabledNoDetection_A	0	0	7758203	6179145	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.EnterDebounceSt_A	0	0	7758203	79	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.EnterDetectSt_A	0	0	7758203	41	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.EnterStableSt_A	0	0	7758203	32	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.PulseIsPulse_A	0	0	7758203	32	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.StayInStableSt	0	0	7758203	295503	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.gen_edge_to_low_event_sva.EdgeToLowEvent_A	0	0	7758203	5501	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.gen_low_level_sva.LowLevelEvent_A	0	0	7758203	7285475	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb.gen_sticky_sva.StableStDropOut_A	0	0	7758203	456975	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	7999703	611	0	912

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	1222337344	455487	455487	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	1222337344	4220	4220	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	1222337344	10975	10975	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	1222337344	8207	8207	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	1222337344	10556	10556	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	1222337344	6532	6532	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	1222337344	5194	5194	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	1222337344	4765	4765	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	1222337344	10211	10211	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	1222337344	91741	91741	843

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	1222337344	455487	455487	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	1222337344	4220	4220	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	1222337344	10975	10975	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	1222337344	8207	8207	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	1222337344	10556	10556	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	1222337344	6532	6532	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	1222337344	5194	5194	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	1222337344	4765	4765	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	1222337344	10211	10211	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	1222337344	91741	91741	843