Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.71	95.35	86.67		83.33	94.44	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.71	95.35	86.67		83.33	94.44	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T6 T1 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T28 T29 T25 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T28 T29 T25 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T28 T29 T25 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T28 T29 T25 
149        1/1                    cnt_en = 1'b1;
           Tests:       T28 T29 T25 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T28 T29 T25 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T28 T29 T25 
163        1/1                    state_d = IdleSt;
           Tests:       T25 T45 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 T45 
165        1/1                  end else if (cnt_done) begin
           Tests:       T28 T29 T25 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T29 T59 
167        1/1                    if (trigger_active) begin
           Tests:       T28 T29 T59 
168        1/1                      state_d = DetectSt;
           Tests:       T28 T29 T59 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T29 T59 T93 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T28 T29 T59 
182        1/1                  cnt_en = 1'b1;
           Tests:       T28 T29 T59 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T28 T29 T59 
186        1/1                    state_d = IdleSt;
           Tests:       T93 T98 T99 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T93 T98 T99 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T28 T29 T59 
191        1/1                      state_d = StableSt;
           Tests:       T28 T29 T59 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T28 T29 T59 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T28 T29 T59 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T28 T29 T59 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T28 T29 T59 
206        1/1                    state_d = IdleSt;
           Tests:       T28 T29 T59 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T28 T29 T59 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T28,T29,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T28,T29,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T28,T29,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T25
1	0	Covered	T4,T6,T14
1	1	Covered	T28,T29,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T59
0	1	Covered	T93,T98,T99
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T59
0	1	Covered	T28,T29,T59
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T29,T59
1	-	Covered	T28,T29,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T29,T25
DetectSt	168	Covered	T28,T29,T59
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T28,T29,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T29,T59
DebounceSt->IdleSt	163	Covered	T29,T25,T59
DetectSt->IdleSt	186	Covered	T93,T98,T99
DetectSt->StableSt	191	Covered	T28,T29,T59
IdleSt->DebounceSt	148	Covered	T28,T29,T25
StableSt->IdleSt	206	Covered	T28,T29,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T28,T29,T25
0	1	Covered	T28,T29,T25
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T59
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T28,T29,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25,T45
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T29,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T59,T93
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T29,T25
DetectSt	-	-	-	-	1	-	-	Covered	T93,T98,T99
DetectSt	-	-	-	-	0	1	-	Covered	T28,T29,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T29,T59
StableSt	-	-	-	-	-	-	0	Covered	T28,T29,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	191	0	0
CntIncr_A	7758203	375526	0	0
CntNoWrap_A	7758203	7283371	0	0
DetectStDropOut_A	7758203	6	0	0
DetectedOut_A	7758203	530	0	0
DetectedPulseOut_A	7758203	80	0	0
DisabledIdleSt_A	7758203	6903633	0	0
DisabledNoDetection_A	7758203	6905506	0	0
EnterDebounceSt_A	7758203	105	0	0
EnterDetectSt_A	7758203	86	0	0
EnterStableSt_A	7758203	80	0	0
PulseIsPulse_A	7758203	80	0	0
StayInStableSt	7758203	450	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7758203	5501	0	0
gen_low_level_sva.LowLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	80	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	191	0	0
T7	2664	0	0	0
T8	505	0	0	0
T25	0	1	0	0
T27	509	0	0	0
T28	619	2	0	0
T29	0	5	0	0
T32	445	0	0	0
T45	0	1	0	0
T49	0	4	0	0
T51	0	2	0	0
T59	0	3	0	0
T60	0	2	0	0
T61	0	4	0	0
T62	0	4	0	0
T63	422	0	0	0
T64	448	0	0	0
T65	795	0	0	0
T66	746	0	0	0
T67	523	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	375526	0	0
T7	2664	0	0	0
T8	505	0	0	0
T25	0	25	0	0
T27	509	0	0	0
T28	619	53	0	0
T29	0	112	0	0
T32	445	0	0	0
T45	0	23	0	0
T49	0	112	0	0
T51	0	25	0	0
T59	0	43	0	0
T60	0	44	0	0
T61	0	64	0	0
T62	0	161	0	0
T63	422	0	0	0
T64	448	0	0	0
T65	795	0	0	0
T66	746	0	0	0
T67	523	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283371	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6	0	0
T72	880	0	0	0
T79	493	0	0	0
T93	646	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T120	8402	0	0	0
T121	1756	0	0	0
T122	533	0	0	0
T123	2656	0	0	0
T124	500	0	0	0
T125	438	0	0	0
T126	587	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	530	0	0
T7	2664	0	0	0
T8	505	0	0	0
T27	509	0	0	0
T28	619	6	0	0
T29	0	14	0	0
T32	445	0	0	0
T49	0	17	0	0
T51	0	5	0	0
T59	0	9	0	0
T60	0	2	0	0
T61	0	13	0	0
T62	0	15	0	0
T63	422	0	0	0
T64	448	0	0	0
T65	795	0	0	0
T66	746	0	0	0
T67	523	0	0	0
T93	0	2	0	0
T128	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	80	0	0
T7	2664	0	0	0
T8	505	0	0	0
T27	509	0	0	0
T28	619	1	0	0
T29	0	2	0	0
T32	445	0	0	0
T49	0	2	0	0
T51	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	422	0	0	0
T64	448	0	0	0
T65	795	0	0	0
T66	746	0	0	0
T67	523	0	0	0
T93	0	1	0	0
T128	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6903633	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6905506	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	105	0	0
T7	2664	0	0	0
T8	505	0	0	0
T25	0	1	0	0
T27	509	0	0	0
T28	619	1	0	0
T29	0	3	0	0
T32	445	0	0	0
T45	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	422	0	0	0
T64	448	0	0	0
T65	795	0	0	0
T66	746	0	0	0
T67	523	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	86	0	0
T7	2664	0	0	0
T8	505	0	0	0
T27	509	0	0	0
T28	619	1	0	0
T29	0	2	0	0
T32	445	0	0	0
T49	0	2	0	0
T51	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	422	0	0	0
T64	448	0	0	0
T65	795	0	0	0
T66	746	0	0	0
T67	523	0	0	0
T93	0	2	0	0
T128	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	80	0	0
T7	2664	0	0	0
T8	505	0	0	0
T27	509	0	0	0
T28	619	1	0	0
T29	0	2	0	0
T32	445	0	0	0
T49	0	2	0	0
T51	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	422	0	0	0
T64	448	0	0	0
T65	795	0	0	0
T66	746	0	0	0
T67	523	0	0	0
T93	0	1	0	0
T128	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	80	0	0
T7	2664	0	0	0
T8	505	0	0	0
T27	509	0	0	0
T28	619	1	0	0
T29	0	2	0	0
T32	445	0	0	0
T49	0	2	0	0
T51	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	422	0	0	0
T64	448	0	0	0
T65	795	0	0	0
T66	746	0	0	0
T67	523	0	0	0
T93	0	1	0	0
T128	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	450	0	0
T7	2664	0	0	0
T8	505	0	0	0
T27	509	0	0	0
T28	619	5	0	0
T29	0	12	0	0
T32	445	0	0	0
T49	0	15	0	0
T51	0	4	0	0
T59	0	8	0	0
T60	0	1	0	0
T61	0	11	0	0
T62	0	13	0	0
T63	422	0	0	0
T64	448	0	0	0
T65	795	0	0	0
T66	746	0	0	0
T67	523	0	0	0
T93	0	1	0	0
T128	0	8	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	5501	0	0
T1	786	0	0	0
T2	510	0	0	0
T3	2489	11	0	0
T4	425	3	0	0
T5	436	0	0	0
T6	528	5	0	0
T14	430	4	0	0
T15	506	4	0	0
T16	492	8	0	0
T17	407	0	0	0
T19	0	7	0	0
T20	0	3	0	0
T28	0	3	0	0
T63	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	80	0	0
T7	2664	0	0	0
T8	505	0	0	0
T27	509	0	0	0
T28	619	1	0	0
T29	0	2	0	0
T32	445	0	0	0
T49	0	2	0	0
T51	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	422	0	0	0
T64	448	0	0	0
T65	795	0	0	0
T66	746	0	0	0
T67	523	0	0	0
T93	0	1	0	0
T128	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T6 T1 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T7 T25 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T3 T7 T25 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T3 T7 T25 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T7 T25 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T7 T25 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T7 T25 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T7 T25 
163        1/1                    state_d = IdleSt;
           Tests:       T25 T45 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 T45 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T7 T25 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T7 T38 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T7 T38 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T7 T38 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T69 T92 T130 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T7 T38 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T7 T38 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T7 T38 
186        1/1                    state_d = IdleSt;
           Tests:       T68 T72 T92 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T68 T72 T92 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T7 T38 
191        1/1                      state_d = StableSt;
           Tests:       T3 T7 T38 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T7 T38 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T7 T38 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T7 T38 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T7 T38 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T7 T38 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T7 T38 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T7,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T25
1	0	Covered	T4,T6,T14
1	1	Covered	T3,T7,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T38
0	1	Covered	T68,T72,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T38
0	1	Unreachable
1	0	Covered	T3,T7,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T25
DetectSt	168	Covered	T3,T7,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T7,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T38
DebounceSt->IdleSt	163	Covered	T25,T69,T45
DetectSt->IdleSt	186	Covered	T68,T72,T92
DetectSt->StableSt	191	Covered	T3,T7,T38
IdleSt->DebounceSt	148	Covered	T3,T7,T25
StableSt->IdleSt	206	Covered	T3,T7,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T25
0	1	Covered	T3,T7,T25
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T38
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25,T45
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T92,T130
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T25
DetectSt	-	-	-	-	1	-	-	Covered	T68,T72,T92
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	119	0	0
CntIncr_A	7758203	100135	0	0
CntNoWrap_A	7758203	7283443	0	0
DetectStDropOut_A	7758203	9	0	0
DetectedOut_A	7758203	295535	0	0
DetectedPulseOut_A	7758203	32	0	0
DisabledIdleSt_A	7758203	6177233	0	0
DisabledNoDetection_A	7758203	6179145	0	0
EnterDebounceSt_A	7758203	79	0	0
EnterDetectSt_A	7758203	41	0	0
EnterStableSt_A	7758203	32	0	0
PulseIsPulse_A	7758203	32	0	0
StayInStableSt	7758203	295503	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7758203	5501	0	0
gen_low_level_sva.LowLevelEvent_A	7758203	7285475	0	0
gen_sticky_sva.StableStDropOut_A	7758203	456975	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	119	0	0
T3	2489	2	0	0
T7	0	4	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	2	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	2	0	0
T45	0	1	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	2	0	0
T69	0	8	0	0
T72	0	4	0	0
T73	0	2	0	0
T92	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	100135	0	0
T3	2489	17	0	0
T7	0	188	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	59	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	13	0	0
T45	0	13	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	23	0	0
T69	0	704	0	0
T72	0	176	0	0
T73	0	88	0	0
T92	0	240	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283443	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2086	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	9	0	0
T49	2713	0	0	0
T54	749	0	0	0
T68	1084	1	0	0
T72	0	1	0	0
T77	491	0	0	0
T92	0	2	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	522	0	0	0
T135	402	0	0	0
T136	422	0	0	0
T137	451	0	0	0
T138	526	0	0	0
T139	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	295535	0	0
T3	2489	152	0	0
T7	0	1262	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	4	0	0
T48	0	267749	0	0
T63	422	0	0	0
T64	448	0	0	0
T72	0	1	0	0
T73	0	612	0	0
T94	0	463	0	0
T95	0	225	0	0
T96	0	236	0	0
T129	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	32	0	0
T3	2489	1	0	0
T7	0	2	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	1	0	0
T48	0	1	0	0
T63	422	0	0	0
T64	448	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	2	0	0
T129	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6177233	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	1148	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6179145	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	1149	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	79	0	0
T3	2489	1	0	0
T7	0	2	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	2	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	1	0	0
T45	0	2	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	1	0	0
T69	0	8	0	0
T72	0	2	0	0
T73	0	1	0	0
T92	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	41	0	0
T3	2489	1	0	0
T7	0	2	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	1	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	1	0	0
T72	0	2	0	0
T73	0	1	0	0
T92	0	2	0	0
T94	0	2	0	0
T95	0	1	0	0
T129	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	32	0	0
T3	2489	1	0	0
T7	0	2	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	1	0	0
T48	0	1	0	0
T63	422	0	0	0
T64	448	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	2	0	0
T129	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	32	0	0
T3	2489	1	0	0
T7	0	2	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	1	0	0
T48	0	1	0	0
T63	422	0	0	0
T64	448	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	2	0	0
T129	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	295503	0	0
T3	2489	151	0	0
T7	0	1260	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	3	0	0
T48	0	267748	0	0
T63	422	0	0	0
T64	448	0	0	0
T73	0	611	0	0
T94	0	461	0	0
T95	0	224	0	0
T96	0	234	0	0
T129	0	9	0	0
T140	0	22093	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	5501	0	0
T1	786	0	0	0
T2	510	0	0	0
T3	2489	11	0	0
T4	425	3	0	0
T5	436	0	0	0
T6	528	5	0	0
T14	430	4	0	0
T15	506	4	0	0
T16	492	8	0	0
T17	407	0	0	0
T19	0	7	0	0
T20	0	3	0	0
T28	0	3	0	0
T63	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	456975	0	0
T3	2489	748	0	0
T7	0	189	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	97	0	0
T48	0	104	0	0
T63	422	0	0	0
T64	448	0	0	0
T72	0	26	0	0
T73	0	93	0	0
T94	0	209	0	0
T95	0	64	0	0
T96	0	228	0	0
T129	0	220	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T6 T1 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T6 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T7 T25 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T3 T7 T25 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T3 T7 T25 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T6 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T6 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T6 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T6 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T6 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T6 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T6 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T6 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T7 T25 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T7 T25 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T7 T25 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T7 T25 
163        1/1                    state_d = IdleSt;
           Tests:       T25 T45 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 T45 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T7 T25 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T7 T38 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T7 T38 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T7 T38 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T7 T129 T94 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T7 T38 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T7 T38 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T7 T38 
186        1/1                    state_d = IdleSt;
           Tests:       T7 T94 T95 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T7 T94 T95 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T38 T68 
191        1/1                      state_d = StableSt;
           Tests:       T3 T38 T68 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T38 T68 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T38 T68 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T38 T68 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T38 T68 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T38 T68 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T38 T68 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T7,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T25
1	0	Covered	T4,T6,T1
1	1	Covered	T3,T7,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T38,T68
0	1	Covered	T7,T94,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T38,T68
0	1	Unreachable
1	0	Covered	T3,T38,T68

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T25
DetectSt	168	Covered	T3,T7,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T38,T68

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T38
DebounceSt->IdleSt	163	Covered	T7,T25,T45
DetectSt->IdleSt	186	Covered	T7,T94,T95
DetectSt->StableSt	191	Covered	T3,T38,T68
IdleSt->DebounceSt	148	Covered	T3,T7,T25
StableSt->IdleSt	206	Covered	T3,T38,T68

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T25
0	1	Covered	T3,T7,T25
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T38
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T25,T45
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T129,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T25
DetectSt	-	-	-	-	1	-	-	Covered	T7,T94,T95
DetectSt	-	-	-	-	0	1	-	Covered	T3,T38,T68
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T38,T68
StableSt	-	-	-	-	-	-	0	Covered	T3,T38,T68
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	118	0	0
CntIncr_A	7758203	122681	0	0
CntNoWrap_A	7758203	7283444	0	0
DetectStDropOut_A	7758203	11	0	0
DetectedOut_A	7758203	380598	0	0
DetectedPulseOut_A	7758203	35	0	0
DisabledIdleSt_A	7758203	6177233	0	0
DisabledNoDetection_A	7758203	6179145	0	0
EnterDebounceSt_A	7758203	73	0	0
EnterDetectSt_A	7758203	46	0	0
EnterStableSt_A	7758203	35	0	0
PulseIsPulse_A	7758203	35	0	0
StayInStableSt	7758203	380563	0	0
gen_high_level_sva.HighLevelEvent_A	7758203	7285475	0	0
gen_sticky_sva.StableStDropOut_A	7758203	389550	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	118	0	0
T3	2489	2	0	0
T7	0	10	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	2	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	2	0	0
T45	0	1	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	2	0	0
T69	0	4	0	0
T72	0	2	0	0
T73	0	2	0	0
T92	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	122681	0	0
T3	2489	86	0	0
T7	0	630	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	59	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	52	0	0
T45	0	13	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	53	0	0
T69	0	60	0	0
T72	0	53	0	0
T73	0	10	0	0
T92	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283444	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2086	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	11	0	0
T7	2664	1	0	0
T9	744	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T66	746	0	0	0
T67	523	0	0	0
T70	1774	0	0	0
T94	0	1	0	0
T95	0	2	0	0
T132	0	2	0	0
T141	0	2	0	0
T142	0	3	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	380598	0	0
T3	2489	733	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	9	0	0
T48	0	508	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	51	0	0
T69	0	262	0	0
T72	0	56	0	0
T73	0	64	0	0
T92	0	77	0	0
T94	0	169	0	0
T130	0	23528	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	35	0	0
T3	2489	1	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	1	0	0
T48	0	1	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T92	0	1	0	0
T94	0	2	0	0
T130	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6177233	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	1148	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6179145	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	1149	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	73	0	0
T3	2489	1	0	0
T7	0	9	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	2	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	1	0	0
T45	0	2	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T92	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	46	0	0
T3	2489	1	0	0
T7	0	1	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	1	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T92	0	1	0	0
T94	0	3	0	0
T130	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	35	0	0
T3	2489	1	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	1	0	0
T48	0	1	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T92	0	1	0	0
T94	0	2	0	0
T130	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	35	0	0
T3	2489	1	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	1	0	0
T48	0	1	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T92	0	1	0	0
T94	0	2	0	0
T130	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	380563	0	0
T3	2489	732	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	8	0	0
T48	0	507	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	50	0	0
T69	0	260	0	0
T72	0	55	0	0
T73	0	63	0	0
T92	0	76	0	0
T94	0	167	0	0
T130	0	23527	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	389550	0	0
T3	2489	113	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	58	0	0
T48	0	298729	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	28	0	0
T69	0	693	0	0
T72	0	120	0	0
T73	0	724	0	0
T92	0	307	0	0
T94	0	100	0	0
T130	0	161	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	41	95.35
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T6 T1 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T4 T6 T1 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T7 T25 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T3 T7 T25 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T3 T7 T25 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T6 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T6 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T6 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T6 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T6 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T6 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T6 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T6 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T7 T25 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T7 T25 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T7 T25 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T7 T25 
163        1/1                    state_d = IdleSt;
           Tests:       T25 T45 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 T45 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T7 T25 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T7 T38 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T7 T38 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T7 T68 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T38 T95 T96 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T7 T68 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T7 T68 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T7 T68 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T7 T68 
191        1/1                      state_d = StableSt;
           Tests:       T3 T7 T68 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T7 T68 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T7 T68 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T7 T68 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T7 T68 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T7 T68 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T7 T68 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T7,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T68

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T25
1	0	Covered	T4,T6,T1
1	1	Covered	T3,T7,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T68
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T68
0	1	Unreachable
1	0	Covered	T3,T7,T68

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T25
DetectSt	168	Covered	T3,T7,T68
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T7,T68

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T68
DebounceSt->IdleSt	163	Covered	T25,T38,T45
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T7,T68
IdleSt->DebounceSt	148	Covered	T3,T7,T25
StableSt->IdleSt	206	Covered	T3,T7,T68

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	17	94.44
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T25
0	1	Covered	T3,T7,T25
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T68
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T25,T45
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T68
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T95,T96
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T25
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T68
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T68
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T68
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	94	0	0
CntIncr_A	7758203	51651	0	0
CntNoWrap_A	7758203	7283468	0	0
DetectStDropOut_A	7758203	0	0	0
DetectedOut_A	7758203	168421	0	0
DetectedPulseOut_A	7758203	39	0	0
DisabledIdleSt_A	7758203	6177233	0	0
DisabledNoDetection_A	7758203	6179145	0	0
EnterDebounceSt_A	7758203	56	0	0
EnterDetectSt_A	7758203	39	0	0
EnterStableSt_A	7758203	39	0	0
PulseIsPulse_A	7758203	39	0	0
StayInStableSt	7758203	168382	0	0
gen_high_event_sva.HighLevelEvent_A	7758203	7285475	0	0
gen_high_level_sva.HighLevelEvent_A	7758203	7285475	0	0
gen_sticky_sva.StableStDropOut_A	7758203	851899	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	94	0	0
T3	2489	2	0	0
T7	0	4	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	2	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	1	0	0
T45	0	1	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	2	0	0
T69	0	4	0	0
T72	0	2	0	0
T73	0	2	0	0
T92	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	51651	0	0
T3	2489	27	0	0
T7	0	200	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	59	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	94	0	0
T45	0	13	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	34	0	0
T69	0	88	0	0
T72	0	23	0	0
T73	0	17	0	0
T92	0	91	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283468	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2086	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	168421	0	0
T3	2489	207	0	0
T7	0	995	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	31	0	0
T69	0	349	0	0
T72	0	39	0	0
T73	0	113	0	0
T92	0	278	0	0
T94	0	156	0	0
T129	0	75	0	0
T130	0	84	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	39	0	0
T3	2489	1	0	0
T7	0	2	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T92	0	1	0	0
T94	0	2	0	0
T129	0	1	0	0
T130	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6177233	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	1148	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6179145	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	1149	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	56	0	0
T3	2489	1	0	0
T7	0	2	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	2	0	0
T28	619	0	0	0
T32	445	0	0	0
T38	0	1	0	0
T45	0	2	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T92	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	39	0	0
T3	2489	1	0	0
T7	0	2	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T92	0	1	0	0
T94	0	2	0	0
T129	0	1	0	0
T130	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	39	0	0
T3	2489	1	0	0
T7	0	2	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T92	0	1	0	0
T94	0	2	0	0
T129	0	1	0	0
T130	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	39	0	0
T3	2489	1	0	0
T7	0	2	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T92	0	1	0	0
T94	0	2	0	0
T129	0	1	0	0
T130	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	168382	0	0
T3	2489	206	0	0
T7	0	993	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	30	0	0
T69	0	347	0	0
T72	0	38	0	0
T73	0	112	0	0
T92	0	277	0	0
T94	0	154	0	0
T129	0	74	0	0
T130	0	83	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	851899	0	0
T3	2489	699	0	0
T7	0	461	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T28	619	0	0	0
T32	445	0	0	0
T63	422	0	0	0
T64	448	0	0	0
T68	0	72	0	0
T69	0	606	0	0
T72	0	178	0	0
T73	0	680	0	0
T92	0	44	0	0
T94	0	566	0	0
T129	0	80	0	0
T130	0	41474	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T9 T25 T53 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T9 T25 T53 
149        1/1                    cnt_en = 1'b1;
           Tests:       T9 T25 T53 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T9 T25 T53 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T9 T25 T53 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T9 T25 T53 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T53 T45 
167        1/1                    if (trigger_active) begin
           Tests:       T9 T53 T45 
168        1/1                      state_d = DetectSt;
           Tests:       T9 T53 T45 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T46 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T9 T53 T45 
182        1/1                  cnt_en = 1'b1;
           Tests:       T9 T53 T45 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T9 T53 T45 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T9 T53 T45 
191        1/1                      state_d = StableSt;
           Tests:       T9 T53 T45 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T9 T53 T45 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T9 T53 T45 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T9 T53 T45 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T9 T53 T45 
206        1/1                    state_d = IdleSt;
           Tests:       T45 T146 T147 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T9 T53 T45 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T25,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T25,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T53,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T25,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T25,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T53,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T53,T45
0	1	Covered	T146,T147,T148
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T53,T45
1	-	Covered	T146,T147,T148

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T25,T53
DetectSt	168	Covered	T9,T53,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T53,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T53,T45
DebounceSt->IdleSt	163	Covered	T25,T46
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T53,T45
IdleSt->DebounceSt	148	Covered	T9,T25,T53
StableSt->IdleSt	206	Covered	T45,T146,T147

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T25,T53
0	1	Covered	T9,T25,T53
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T9,T53,T45
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T25,T53
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T53,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T46
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T25,T53
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T53,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T146,T147
StableSt	-	-	-	-	-	-	0	Covered	T9,T53,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	36	0	0
CntIncr_A	7758203	134463	0	0
CntNoWrap_A	7758203	7283526	0	0
DetectStDropOut_A	7758203	0	0	0
DetectedOut_A	7758203	15133	0	0
DetectedPulseOut_A	7758203	17	0	0
DisabledIdleSt_A	7758203	6947075	0	0
DisabledNoDetection_A	7758203	6948966	0	0
EnterDebounceSt_A	7758203	19	0	0
EnterDetectSt_A	7758203	17	0	0
EnterStableSt_A	7758203	17	0	0
PulseIsPulse_A	7758203	17	0	0
StayInStableSt	7758203	15106	0	0
gen_high_level_sva.HighLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	6	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	36	0	0
T9	744	2	0	0
T25	7314	1	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	2	0	0
T46	0	3	0	0
T53	0	2	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T146	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	134463	0	0
T9	744	31	0	0
T25	7314	34	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	21	0	0
T46	0	178	0	0
T53	0	58	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T146	0	99	0	0
T149	0	32	0	0
T150	0	42	0	0
T151	0	86	0	0
T152	0	95	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283526	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	15133	0	0
T9	744	258	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	7	0	0
T46	0	39	0	0
T53	0	41	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T146	0	154	0	0
T147	0	41	0	0
T149	0	42	0	0
T150	0	42	0	0
T151	0	39	0	0
T152	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	17	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T53	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6947075	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6948966	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	19	0	0
T9	744	1	0	0
T25	7314	1	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T53	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	17	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T53	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	17	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T53	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	17	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T53	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	15106	0	0
T9	744	256	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	6	0	0
T46	0	37	0	0
T53	0	39	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T146	0	153	0	0
T147	0	40	0	0
T149	0	40	0	0
T150	0	40	0	0
T151	0	37	0	0
T152	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6	0	0
T102	0	1	0	0
T146	2803	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	16450	0	0	0
T156	682	0	0	0
T157	418	0	0	0
T158	1453	0	0	0
T159	502	0	0	0
T160	522	0	0	0
T161	627	0	0	0
T162	452	0	0	0
T163	403	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T9 T25 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T9 T25 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T9 T25 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T9 T25 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T9 T25 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T9 T25 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T9 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T9 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T9 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T164 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T9 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T9 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T9 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T165 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T165 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T9 T11 
191        1/1                      state_d = StableSt;
           Tests:       T1 T9 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T9 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T9 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T9 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T9 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T9 T49 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T9 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T9,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T9,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T25
1	0	Covered	T4,T6,T14
1	1	Covered	T1,T9,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T165
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T1,T9,T49
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T11
1	-	Covered	T1,T9,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T25
DetectSt	168	Covered	T1,T9,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T11
DebounceSt->IdleSt	163	Covered	T25,T164
DetectSt->IdleSt	186	Covered	T165
DetectSt->StableSt	191	Covered	T1,T9,T11
IdleSt->DebounceSt	148	Covered	T1,T9,T25
StableSt->IdleSt	206	Covered	T1,T9,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T25
0	1	Covered	T1,T9,T25
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T11
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T164
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T25
DetectSt	-	-	-	-	1	-	-	Covered	T165
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T9,T49
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	100	0	0
CntIncr_A	7758203	210094	0	0
CntNoWrap_A	7758203	7283462	0	0
DetectStDropOut_A	7758203	1	0	0
DetectedOut_A	7758203	136741	0	0
DetectedPulseOut_A	7758203	48	0	0
DisabledIdleSt_A	7758203	6722857	0	0
DisabledNoDetection_A	7758203	6724730	0	0
EnterDebounceSt_A	7758203	51	0	0
EnterDetectSt_A	7758203	49	0	0
EnterStableSt_A	7758203	48	0	0
PulseIsPulse_A	7758203	48	0	0
StayInStableSt	7758203	136673	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7758203	1628	0	0
gen_low_level_sva.LowLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	100	0	0
T1	786	4	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	1	0	0
T45	0	2	0	0
T46	0	4	0	0
T48	0	4	0	0
T49	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	210094	0	0
T1	786	106	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	31	0	0
T11	0	40	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	34	0	0
T45	0	21	0	0
T46	0	178	0	0
T48	0	158	0	0
T49	0	57	0	0
T166	0	20	0	0
T167	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283462	0	0
T1	786	381	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1	0	0
T142	1352	0	0	0
T165	2267	1	0	0
T168	402	0	0	0
T169	798	0	0	0
T170	522	0	0	0
T171	492	0	0	0
T172	42952	0	0	0
T173	1895	0	0	0
T174	890	0	0	0
T175	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	136741	0	0
T1	786	78	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	13	0	0
T11	0	42	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	7	0	0
T46	0	169	0	0
T48	0	292	0	0
T49	0	54	0	0
T166	0	44	0	0
T167	0	71	0	0
T176	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	48	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6722857	0	0
T1	786	4	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6724730	0	0
T1	786	4	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	51	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	49	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	48	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	48	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	136673	0	0
T1	786	75	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	12	0	0
T11	0	40	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	6	0	0
T46	0	167	0	0
T48	0	290	0	0
T49	0	53	0	0
T166	0	42	0	0
T167	0	69	0	0
T176	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1628	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T4	425	3	0	0
T5	436	0	0	0
T6	528	5	0	0
T14	430	3	0	0
T15	506	5	0	0
T16	492	4	0	0
T17	407	0	0	0
T19	0	7	0	0
T20	0	1	0	0
T63	0	2	0	0
T64	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	27	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	1	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T46	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T146	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0