Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1620

1

T30

6

T43

3

T41

10

auto[1]

555

1

T12

2

T30

2

T41

3

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1649

1

T30

8

T41

3

T56

21

auto[1]

526

1

T12

2

T43

3

T41

10

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1604

1

T30

6

T43

2

T41

10

auto[1]

571

1

T12

2

T30

2

T43

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1760

1

T12

1

T30

6

T43

1

auto[1]

415

1

T12

1

T30

2

T43

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2021

1

T12

2

T30

8

T43

3

auto[1]

154

1

T39

2

T249

4

T252

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1954

1

T12

2

T30

8

T43

3

auto[1]

221

1

T39

2

T257

2

T249

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1999

1

T12

2

T30

8

T43

3

auto[1]

176

1

T87

1

T39

10

T40

21

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1950

1

T12

2

T30

8

T43

3

auto[1]

225

1

T57

1

T39

10

T40

10

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2021

1

T12

2

T30

6

T43

3

auto[1]

154

1

T30

2

T39

2

T40

10

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1603

1

T12

1

T30

8

T43

1

auto[1]

572

1

T12

1

T43

2

T44

6

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	770	1			T12	2		T43	3		T41	13
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	47	1			T253	8		T367	2		T232	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	41	1			T30	2		T251	1		T232	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	11	1			T368	6		T369	2		T370	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	62	1			T57	1		T100	1		T371	6
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	16	1			T372	1		T373	2		T374	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	28	1			T250	8		T375	1		T376	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T368	3		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	43	1			T87	1		T40	11		T249	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	22	1			T253	8		T273	3		T377	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	15	1			T368	10		T378	2		T379	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	20	1			T39	10		T371	2		T373	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T369	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	10	1			T40	10		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	81	1			T252	8		T357	4		T377	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	18	1			T249	4		T380	2		T377	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	13	1			T376	3		T381	3		T379	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	7	1			T39	2		T382	5		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	32	1			T257	2		T100	1		T250	7
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	7	1			T252	3		T383	4		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	3	1			T371	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	23	1			T250	9		T362	2		T384	3
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T385	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T386	1		T359	2		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	6	1			T253	6		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T387	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

124

1

T56

12

T40

5

T104

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

157

1

T87

1

T39

5

T40

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T257

2

T356

6

T362

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

61

1

T251

1

T253

6

T172

12

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

51

1

T105

1

T269

6

T388

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T260

4

T276

8

T377

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T42

5

T260

1

T357

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

99

1

T56

8

T39

2

T259

13

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

62

1

T250

8

T108

5

T355

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T42

8

T250

7

T252

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T259

4

T155

4

T377

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T269

6

T275

4

T377

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T30

2

T41

3

T56

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

31

1

T389

6

T390

5

T353

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T240

2

T357

4

T353

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

71

1

T41

10

T108

8

T109

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

44

1

T57

1

T40

5

T261

14

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T249

4

T269

3

T355

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T44

4

T39

5

T106

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

30

1

T351

6

T391

3

T392

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T351

3

T262

2

T263

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T43

2

T44

2

T275

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T352

2

T393

1

T391

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

87

1

T43

1

T44

7

T42

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

38

1

T106

3

T274

4

T132

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

16

1

T107

4

T276

2

T391

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T12

1

T259

1

T109

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

16

1

T42

2

T352

1

T354

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T12

1

T232

2

T262

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T48

1

T232

2

T377

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T352

1

T353

2

T281

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded