Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

798

1

T15

10

T27

15

T80

13

auto[1]

746

1

T15

10

T27

5

T80

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

368

1

T15

4

T27

4

T80

5

from_0to1

367

1

T15

4

T27

4

T80

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

806

1

T15

8

T27

13

T80

12

auto[1]

738

1

T15

12

T27

7

T80

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

766

1

T15

10

T27

11

T80

9

auto[1]

778

1

T15

10

T27

9

T80

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T27

1

T82

1

T49

1

auto[0]

from_1to0

auto[0]

auto[1]

45

1

T27

1

T80

1

T82

1

auto[0]

from_1to0

auto[1]

auto[0]

41

1

T15

2

T27

1

T80

1

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T15

1

T80

1

T82

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T15

1

T27

1

T194

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T27

1

T80

2

T82

2

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T82

1

T84

1

T49

1

auto[0]

from_0to1

auto[1]

auto[1]

45

1

T80

1

T49

2

T117

3

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T80

1

T82

1

T84

1

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T15

1

T27

1

T194

1

auto[1]

from_1to0

auto[1]

auto[0]

48

1

T84

2

T49

1

T139

1

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T80

1

T82

1

T194

1

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T15

1

T27

1

T82

1

auto[1]

from_0to1

auto[0]

auto[1]

42

1

T15

1

T84

1

T194

3

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T15

1

T27

1

T80

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T82

2

T84

1

T117

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

754

1

T15

6

T27

7

T80

9

auto[1]

790

1

T15

14

T27

13

T80

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

366

1

T15

4

T27

6

T80

4

from_0to1

364

1

T15

4

T27

6

T80

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

771

1

T15

8

T27

12

T80

8

auto[1]

773

1

T15

12

T27

8

T80

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

762

1

T15

13

T27

8

T80

11

auto[1]

782

1

T15

7

T27

12

T80

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

43

1

T84

2

T194

1

T51

3

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T27

2

T80

1

T82

2

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T15

1

T82

1

T49

2

auto[0]

from_1to0

auto[1]

auto[1]

32

1

T84

1

T194

1

T117

1

auto[0]

from_0to1

auto[0]

auto[0]

33

1

T80

1

T82

2

T194

1

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T84

2

T194

1

T49

1

auto[0]

from_0to1

auto[1]

auto[0]

44

1

T139

1

T51

1

T44

2

auto[0]

from_0to1

auto[1]

auto[1]

47

1

T15

1

T27

1

T82

1

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T15

1

T84

1

T117

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T15

1

T27

3

T117

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T15

1

T80

2

T82

2

auto[1]

from_1to0

auto[1]

auto[1]

43

1

T27

1

T80

1

T194

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T27

1

T80

1

T82

1

auto[1]

from_0to1

auto[0]

auto[1]

46

1

T15

1

T27

1

T49

3

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T15

2

T27

3

T80

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T84

1

T117

1

T51

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

758

1

T15

10

T27

8

T80

13

auto[1]

786

1

T15

10

T27

12

T80

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

378

1

T15

4

T27

4

T80

5

from_0to1

368

1

T15

4

T27

4

T80

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

808

1

T15

9

T27

8

T80

10

auto[1]

736

1

T15

11

T27

12

T80

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

767

1

T15

8

T27

13

T80

16

auto[1]

777

1

T15

12

T27

7

T80

4

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

35

1

T15

1

T82

1

T44

1

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T15

1

T82

1

T84

1

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T27

1

T80

1

T82

2

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T80

3

T49

1

T139

1

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T84

1

T194

2

T49

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T27

1

T194

1

T49

1

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T15

1

T80

3

T84

2

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T15

1

T27

1

T82

2

auto[1]

from_1to0

auto[0]

auto[0]

44

1

T80

1

T84

1

T194

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T15

1

T27

1

T82

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T15

1

T27

2

T82

1

auto[1]

from_1to0

auto[1]

auto[1]

45

1

T82

1

T84

2

T194

1

auto[1]

from_0to1

auto[0]

auto[0]

47

1

T80

1

T139

2

T117

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T15

1

T82

2

T84

1

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T27

1

T80

1

T82

2

auto[1]

from_0to1

auto[1]

auto[1]

35

1

T15

1

T27

1

T82

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

765

1

T15

10

T27

13

T80

9

auto[1]

779

1

T15

10

T27

7

T80

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

374

1

T15

5

T27

4

T80

4

from_0to1

373

1

T15

5

T27

4

T80

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

780

1

T15

9

T27

11

T80

9

auto[1]

764

1

T15

11

T27

9

T80

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

727

1

T15

11

T27

10

T80

13

auto[1]

817

1

T15

9

T27

10

T80

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

31

1

T15

1

T27

1

T80

2

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T15

1

T27

1

T82

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T15

1

T82

1

T84

1

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T84

1

T194

1

T44

1

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T80

1

T84

2

T139

1

auto[0]

from_0to1

auto[0]

auto[1]

46

1

T27

2

T84

1

T194

2

auto[0]

from_0to1

auto[1]

auto[0]

47

1

T82

1

T49

2

T44

2

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T15

1

T80

1

T84

1

auto[1]

from_1to0

auto[0]

auto[0]

45

1

T80

1

T82

1

T84

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T82

1

T84

1

T49

1

auto[1]

from_1to0

auto[1]

auto[0]

41

1

T15

2

T27

1

T82

1

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T27

1

T80

1

T49

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T15

2

T27

1

T82

2

auto[1]

from_0to1

auto[0]

auto[1]

39

1

T15

1

T82

2

T139

1

auto[1]

from_0to1

auto[1]

auto[0]

35

1

T27

1

T80

2

T82

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T15

1

T117

2

T51

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

782

1

T15

10

T27

12

T80

8

auto[1]

762

1

T15

10

T27

8

T80

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

368

1

T15

3

T27

7

T80

5

from_0to1

375

1

T15

4

T27

7

T80

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

798

1

T15

10

T27

14

T80

14

auto[1]

746

1

T15

10

T27

6

T80

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

777

1

T15

9

T27

13

T80

13

auto[1]

767

1

T15

11

T27

7

T80

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T27

2

T80

1

T82

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T80

1

T82

1

T84

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T15

1

T84

1

T194

1

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T27

1

T82

1

T194

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T27

3

T80

1

T84

1

auto[0]

from_0to1

auto[0]

auto[1]

41

1

T15

2

T27

1

T84

1

auto[0]

from_0to1

auto[1]

auto[0]

44

1

T27

2

T49

1

T139

1

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T15

1

T82

2

T84

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T15

2

T27

1

T80

1

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T27

1

T194

1

T139

1

auto[1]

from_1to0

auto[1]

auto[0]

42

1

T27

1

T80

1

T82

1

auto[1]

from_1to0

auto[1]

auto[1]

34

1

T27

1

T80

1

T84

1

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T80

3

T82

1

T51

1

auto[1]

from_0to1

auto[0]

auto[1]

45

1

T84

1

T194

1

T139

2

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T27

1

T84

1

T194

2

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T15

1

T84

1

T49

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

759

1

T15

12

T27

9

T80

9

auto[1]

785

1

T15

8

T27

11

T80

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

346

1

T15

5

T27

6

T80

7

from_0to1

347

1

T15

5

T27

6

T80

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

750

1

T15

11

T27

11

T80

15

auto[1]

794

1

T15

9

T27

9

T80

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

782

1

T15

7

T27

13

T80

8

auto[1]

762

1

T15

13

T27

7

T80

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T80

1

T82

1

T49

1

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T15

2

T27

1

T80

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T27

1

T84

1

T194

1

auto[0]

from_1to0

auto[1]

auto[1]

38

1

T15

2

T27

1

T84

2

auto[0]

from_0to1

auto[0]

auto[0]

46

1

T27

2

T80

2

T49

2

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T80

2

T84

1

T194

1

auto[0]

from_0to1

auto[1]

auto[0]

40

1

T80

1

T82

2

T194

1

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T15

1

T27

1

T82

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T27

2

T82

2

T84

1

auto[1]

from_1to0

auto[0]

auto[1]

37

1

T80

3

T194

1

T49

1

auto[1]

from_1to0

auto[1]

auto[0]

42

1

T15

1

T27

1

T80

1

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T80

1

T194

1

T51

1

auto[1]

from_0to1

auto[0]

auto[0]

40

1

T15

2

T27

1

T84

1

auto[1]

from_0to1

auto[0]

auto[1]

42

1

T15

1

T27

1

T80

2

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T15

1

T49

1

T139

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T27

1

T82

1

T84

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

747

1

T15

9

T27

12

T80

9

auto[1]

797

1

T15

11

T27

8

T80

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

362

1

T15

4

T27

5

T80

5

from_0to1

368

1

T15

5

T27

6

T80

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

757

1

T15

9

T27

10

T80

11

auto[1]

787

1

T15

11

T27

10

T80

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

749

1

T15

11

T27

12

T80

9

auto[1]

795

1

T15

9

T27

8

T80

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T27

1

T82

1

T49

3

auto[0]

from_1to0

auto[0]

auto[1]

50

1

T15

1

T27

1

T80

1

auto[0]

from_1to0

auto[1]

auto[0]

45

1

T15

1

T80

1

T194

1

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T84

4

T408

2

T322

1

auto[0]

from_0to1

auto[0]

auto[0]

33

1

T27

2

T80

1

T84

2

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T80

1

T84

1

T49

1

auto[0]

from_0to1

auto[1]

auto[0]

42

1

T27

2

T194

2

T49

2

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T15

1

T80

1

T84

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T15

1

T27

1

T80

1

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T27

1

T49

1

T139

1

auto[1]

from_1to0

auto[1]

auto[0]

33

1

T82

1

T194

1

T117

2

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T15

1

T27

1

T80

2

auto[1]

from_0to1

auto[0]

auto[0]

46

1

T15

1

T80

1

T84

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T15

1

T194

1

T139

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T15

2

T80

1

T82

3

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T27

2

T80

1

T49

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

783

1

T15

10

T27

11

T80

9

auto[1]

761

1

T15

10

T27

9

T80

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

357

1

T15

5

T27

4

T80

5

from_0to1

363

1

T15

4

T27

4

T80

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

749

1

T15

12

T27

11

T80

8

auto[1]

795

1

T15

8

T27

9

T80

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

755

1

T15

12

T27

9

T80

11

auto[1]

789

1

T15

8

T27

11

T80

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

53

1

T15

1

T27

2

T82

1

auto[0]

from_1to0

auto[0]

auto[1]

50

1

T80

1

T84

1

T49

1

auto[0]

from_1to0

auto[1]

auto[0]

48

1

T80

2

T82

2

T194

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T15

1

T117

1

T51

1

auto[0]

from_0to1

auto[0]

auto[0]

36

1

T15

1

T80

1

T82

1

auto[0]

from_0to1

auto[0]

auto[1]

37

1

T49

1

T51

2

T121

1

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T15

1

T27

1

T82

1

auto[0]

from_0to1

auto[1]

auto[1]

44

1

T82

1

T84

1

T49

1

auto[1]

from_1to0

auto[0]

auto[0]

40

1

T15

2

T27

1

T194

1

auto[1]

from_1to0

auto[0]

auto[1]

38

1

T15

1

T82

1

T84

2

auto[1]

from_1to0

auto[1]

auto[0]

43

1

T80

1

T49

2

T117

1

auto[1]

from_1to0

auto[1]

auto[1]

42

1

T27

1

T80

1

T82

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T15

1

T80

3

T84

1

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T15

1

T27

1

T49

1

auto[1]

from_0to1

auto[1]

auto[0]

39

1

T27

2

T80

1

T82

1

auto[1]

from_0to1

auto[1]

auto[1]

51

1

T82

1

T84

1

T194

1