Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	141490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

108718

1

T4

2

T5

4

T6

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	132602	1			T4	2		T5	3		T6	2
values[0x0]	58187	1			T5	3		T6	31		T1	3
values[0x1]	59419	1			T5	3		T6	29		T1	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	113927	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

136281

1

T4

2

T5

5

T6

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	901	1			T12	1		T30	1		T83	1
valid_sources[0x01]	797	1			T18	1		T296	1		T30	2
valid_sources[0x02]	746	1			T28	2		T12	1		T30	2
valid_sources[0x03]	873	1			T15	2		T19	1		T27	3
valid_sources[0x04]	929	1			T19	1		T144	1		T12	1
valid_sources[0x05]	807	1			T12	1		T30	13		T270	2
valid_sources[0x06]	897	1			T27	1		T30	5		T83	1
valid_sources[0x07]	783	1			T6	1		T27	1		T30	5
valid_sources[0x08]	914	1			T27	1		T66	9		T12	3
valid_sources[0x09]	974	1			T11	11		T30	9		T31	1
valid_sources[0x0a]	789	1			T3	1		T270	2		T192	2
valid_sources[0x0b]	1189	1			T15	2		T75	1		T296	2
valid_sources[0x0c]	826	1			T6	1		T28	1		T27	1
valid_sources[0x0d]	1547	1			T74	4		T12	1		T30	10
valid_sources[0x0e]	1242	1			T15	3		T296	1		T270	1
valid_sources[0x0f]	850	1			T16	5		T27	1		T82	5
valid_sources[0x10]	858	1			T16	1		T19	1		T27	1
valid_sources[0x11]	846	1			T296	6		T12	2		T83	1
valid_sources[0x12]	1217	1			T27	1		T29	1		T70	2
valid_sources[0x13]	771	1			T28	1		T65	1		T296	11
valid_sources[0x14]	915	1			T66	20		T12	2		T83	1
valid_sources[0x15]	744	1			T75	1		T296	6		T12	7
valid_sources[0x16]	2016	1			T2	2		T82	34		T12	1
valid_sources[0x17]	918	1			T14	14		T296	2		T30	8
valid_sources[0x18]	907	1			T67	62		T296	1		T12	3
valid_sources[0x19]	733	1			T81	1		T296	9		T12	1
valid_sources[0x1a]	820	1			T15	1		T27	1		T12	2
valid_sources[0x1b]	737	1			T6	7		T19	1		T27	1
valid_sources[0x1c]	795	1			T64	3		T12	2		T30	4
valid_sources[0x1d]	726	1			T9	21		T296	4		T12	1
valid_sources[0x1e]	1045	1			T6	1		T27	1		T80	15
valid_sources[0x1f]	1878	1			T3	2		T16	2		T27	1
valid_sources[0x20]	2473	1			T3	4		T75	2		T30	12
valid_sources[0x21]	1038	1			T296	12		T12	1		T30	3
valid_sources[0x22]	881	1			T15	1		T27	1		T12	1
valid_sources[0x23]	797	1			T12	7		T30	14		T270	3
valid_sources[0x24]	843	1			T64	1		T27	1		T31	2
valid_sources[0x25]	1064	1			T64	1		T29	1		T296	7
valid_sources[0x26]	807	1			T27	1		T80	12		T296	5
valid_sources[0x27]	711	1			T27	1		T29	1		T296	5
valid_sources[0x28]	789	1			T15	1		T27	3		T74	9
valid_sources[0x29]	1096	1			T19	1		T27	1		T31	1
valid_sources[0x2a]	1937	1			T15	2		T59	8		T296	5
valid_sources[0x2b]	803	1			T15	9		T81	1		T296	8
valid_sources[0x2c]	676	1			T27	1		T29	2		T296	3
valid_sources[0x2d]	773	1			T19	4		T27	1		T82	2
valid_sources[0x2e]	741	1			T66	8		T270	1		T31	1
valid_sources[0x2f]	840	1			T30	6		T85	1		T41	2
valid_sources[0x30]	718	1			T75	1		T296	2		T12	2
valid_sources[0x31]	1791	1			T296	1		T30	3		T270	1
valid_sources[0x32]	1568	1			T27	1		T296	2		T12	1
valid_sources[0x33]	1038	1			T296	1		T12	1		T13	14
valid_sources[0x34]	817	1			T12	2		T30	13		T192	1
valid_sources[0x35]	843	1			T30	2		T31	1		T192	1
valid_sources[0x36]	784	1			T16	2		T64	8		T296	3
valid_sources[0x37]	780	1			T16	1		T19	1		T296	1
valid_sources[0x38]	854	1			T81	4		T12	4		T270	3
valid_sources[0x39]	758	1			T6	6		T296	1		T30	1
valid_sources[0x3a]	773	1			T6	1		T15	1		T64	8
valid_sources[0x3b]	1771	1			T29	3		T296	9		T270	1
valid_sources[0x3c]	1086	1			T15	12		T3	2		T19	1
valid_sources[0x3d]	747	1			T15	4		T27	1		T75	1
valid_sources[0x3e]	894	1			T58	1		T12	2		T30	5
valid_sources[0x3f]	956	1			T19	1		T66	20		T12	6
valid_sources[0x40]	706	1			T15	2		T64	1		T27	1
valid_sources[0x41]	777	1			T64	1		T27	1		T66	23
valid_sources[0x42]	1220	1			T74	5		T83	4		T31	3
valid_sources[0x43]	733	1			T19	1		T12	3		T30	5
valid_sources[0x44]	1322	1			T12	1		T30	2		T270	1
valid_sources[0x45]	686	1			T75	1		T12	2		T30	2
valid_sources[0x46]	970	1			T19	1		T75	1		T12	1
valid_sources[0x47]	926	1			T3	1		T27	2		T81	4
valid_sources[0x48]	1042	1			T19	1		T28	2		T75	1
valid_sources[0x49]	870	1			T16	2		T12	1		T30	2
valid_sources[0x4a]	756	1			T15	3		T30	7		T270	1
valid_sources[0x4b]	828	1			T12	5		T30	5		T270	2
valid_sources[0x4c]	1038	1			T3	1		T27	1		T66	15
valid_sources[0x4d]	827	1			T15	4		T27	2		T296	9
valid_sources[0x4e]	864	1			T16	1		T28	1		T296	2
valid_sources[0x4f]	780	1			T16	1		T27	1		T75	2
valid_sources[0x50]	1114	1			T59	1		T12	2		T54	1
valid_sources[0x51]	940	1			T15	6		T27	2		T80	17
valid_sources[0x52]	792	1			T19	1		T27	1		T82	9
valid_sources[0x53]	798	1			T19	2		T27	1		T296	1
valid_sources[0x54]	1632	1			T30	16		T192	4		T77	6
valid_sources[0x55]	832	1			T15	3		T28	1		T12	1
valid_sources[0x56]	988	1			T14	3		T27	1		T12	1
valid_sources[0x57]	722	1			T29	1		T12	2		T30	4
valid_sources[0x58]	835	1			T15	3		T16	3		T296	9
valid_sources[0x59]	741	1			T27	2		T76	15		T83	1
valid_sources[0x5a]	801	1			T10	2		T75	1		T12	2
valid_sources[0x5b]	1487	1			T17	1		T81	3		T12	1
valid_sources[0x5c]	788	1			T27	2		T12	1		T270	3
valid_sources[0x5d]	2288	1			T16	2		T17	1		T18	2
valid_sources[0x5e]	738	1			T6	1		T15	9		T19	2
valid_sources[0x5f]	765	1			T19	1		T12	1		T192	1
valid_sources[0x60]	850	1			T82	14		T12	2		T30	7
valid_sources[0x61]	865	1			T15	6		T27	1		T296	1
valid_sources[0x62]	821	1			T27	2		T75	1		T12	2
valid_sources[0x63]	858	1			T27	1		T296	4		T30	4
valid_sources[0x64]	784	1			T4	1		T27	2		T12	1
valid_sources[0x65]	782	1			T27	2		T296	4		T12	1
valid_sources[0x66]	825	1			T75	1		T12	2		T30	9
valid_sources[0x67]	951	1			T27	1		T296	1		T12	1
valid_sources[0x68]	994	1			T27	1		T66	4		T296	2
valid_sources[0x69]	2034	1			T296	2		T30	3		T270	2
valid_sources[0x6a]	1911	1			T16	2		T28	1		T64	5
valid_sources[0x6b]	918	1			T3	1		T16	1		T27	1
valid_sources[0x6c]	1748	1			T296	4		T12	2		T30	4
valid_sources[0x6d]	1012	1			T12	3		T30	15		T270	2
valid_sources[0x6e]	658	1			T59	1		T12	2		T83	1
valid_sources[0x6f]	1922	1			T17	2		T12	3		T30	14
valid_sources[0x70]	973	1			T15	1		T75	1		T296	2
valid_sources[0x71]	873	1			T6	3		T27	2		T296	4
valid_sources[0x72]	1431	1			T6	3		T80	15		T30	15
valid_sources[0x73]	979	1			T296	4		T12	1		T30	3
valid_sources[0x74]	690	1			T30	1		T31	4		T85	1
valid_sources[0x75]	1397	1			T27	1		T65	1		T296	1
valid_sources[0x76]	720	1			T3	1		T16	2		T27	1
valid_sources[0x77]	790	1			T6	1		T17	1		T12	4
valid_sources[0x78]	894	1			T75	1		T296	4		T12	3
valid_sources[0x79]	867	1			T17	1		T65	2		T30	1
valid_sources[0x7a]	789	1			T66	6		T74	1		T12	1
valid_sources[0x7b]	893	1			T16	2		T27	2		T296	1
valid_sources[0x7c]	1006	1			T27	1		T192	1		T68	1
valid_sources[0x7d]	2011	1			T27	1		T12	4		T31	1
valid_sources[0x7e]	719	1			T12	3		T192	4		T54	1
valid_sources[0x7f]	878	1			T143	2		T296	1		T30	17
valid_sources[0x80]	734	1			T3	3		T27	2		T82	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59671

1

T4

2

T5

2

T1

7

values[0x0]

all_enables

biggest_size

28574

1

T5

1

T6

17

T1

1

values[0x1]

all_enables

biggest_size

20473

1

T5

1

T6

7

T2

1