Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	90	90	100.00
Total Bits 0->1	45	45	100.00
Total Bits 1->0	45	45	100.00

Ports	5	5	100.00
Port Bits	90	90	100.00
Port Bits 0->1	45	45	100.00
Port Bits 1->0	45	45	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T66,T26,T70	Yes	T4,T5,T6	INPUT
oh_i[0]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[15:1]	Yes	Yes	*T2,*T15,*T18	Yes	T2,T15,T18	INPUT
oh_i[16]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[42:17]	Yes	Yes	T1,T9,T144	Yes	T1,T9,T144	INPUT
addr_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T5,T6,T1	Yes	T5,T6,T1	INPUT
err_o	Yes	Yes	T144,T91,T195	Yes	T144,T91,T195	OUTPUT

*Tests covering at least one bit in the range