Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1222336775 13114 0 0
auto_block_debounce_ctl_rd_A 1222336775 1451 0 0
auto_block_out_ctl_rd_A 1222336775 1920 0 0
com_det_ctl_0_rd_A 1222336775 3045 0 0
com_det_ctl_1_rd_A 1222336775 3136 0 0
com_det_ctl_2_rd_A 1222336775 3142 0 0
com_det_ctl_3_rd_A 1222336775 3227 0 0
com_out_ctl_0_rd_A 1222336775 3299 0 0
com_out_ctl_1_rd_A 1222336775 3555 0 0
com_out_ctl_2_rd_A 1222336775 3642 0 0
com_out_ctl_3_rd_A 1222336775 3757 0 0
com_pre_det_ctl_0_rd_A 1222336775 1162 0 0
com_pre_det_ctl_1_rd_A 1222336775 1043 0 0
com_pre_det_ctl_2_rd_A 1222336775 965 0 0
com_pre_det_ctl_3_rd_A 1222336775 965 0 0
com_pre_sel_ctl_0_rd_A 1222336775 3706 0 0
com_pre_sel_ctl_1_rd_A 1222336775 3801 0 0
com_pre_sel_ctl_2_rd_A 1222336775 3484 0 0
com_pre_sel_ctl_3_rd_A 1222336775 3745 0 0
com_sel_ctl_0_rd_A 1222336775 3714 0 0
com_sel_ctl_1_rd_A 1222336775 3672 0 0
com_sel_ctl_2_rd_A 1222336775 3574 0 0
com_sel_ctl_3_rd_A 1222336775 3969 0 0
ec_rst_ctl_rd_A 1222336775 1726 0 0
intr_enable_rd_A 1222336775 1515 0 0
key_intr_ctl_rd_A 1222336775 3103 0 0
key_intr_debounce_ctl_rd_A 1222336775 1040 0 0
key_invert_ctl_rd_A 1222336775 4347 0 0
pin_allowed_ctl_rd_A 1222336775 5108 0 0
pin_out_ctl_rd_A 1222336775 3697 0 0
pin_out_value_rd_A 1222336775 4104 0 0
regwen_rd_A 1222336775 1139 0 0
ulp_ac_debounce_ctl_rd_A 1222336775 1177 0 0
ulp_ctl_rd_A 1222336775 1067 0 0
ulp_lid_debounce_ctl_rd_A 1222336775 1153 0 0
ulp_pwrb_debounce_ctl_rd_A 1222336775 1177 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 13114 0 0
T9 160964 0 0 0
T25 837557 0 0 0
T26 157058 0 0 0
T29 310192 0 0 0
T49 0 7 0 0
T51 0 8 0 0
T66 373637 6 0 0
T67 128352 0 0 0
T70 851721 0 0 0
T123 0 12 0 0
T129 0 3 0 0
T143 53383 0 0 0
T144 199922 0 0 0
T145 193409 0 0 0
T192 0 6 0 0
T270 0 6 0 0
T296 0 9 0 0
T303 0 11 0 0
T304 0 11 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 1451 0 0
T11 81852 0 0 0
T12 191889 0 0 0
T48 0 57 0 0
T51 0 54 0 0
T59 79937 4 0 0
T75 236110 0 0 0
T76 42122 0 0 0
T82 25773 0 0 0
T91 107871 0 0 0
T123 0 24 0 0
T128 0 1 0 0
T129 0 11 0 0
T140 0 19 0 0
T186 53144 0 0 0
T187 98688 0 0 0
T270 0 17 0 0
T296 540734 0 0 0
T305 0 10 0 0
T306 0 22 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 1920 0 0
T11 81852 0 0 0
T12 191889 0 0 0
T48 0 44 0 0
T51 0 48 0 0
T59 79937 6 0 0
T75 236110 0 0 0
T76 42122 0 0 0
T82 25773 0 0 0
T91 107871 0 0 0
T123 0 13 0 0
T128 0 12 0 0
T129 0 18 0 0
T140 0 1 0 0
T186 53144 0 0 0
T187 98688 0 0 0
T270 0 27 0 0
T296 540734 0 0 0
T305 0 4 0 0
T306 0 19 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3045 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 73 0 0
T41 0 60 0 0
T42 0 46 0 0
T43 0 60 0 0
T51 0 37 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 55 0 0
T123 0 17 0 0
T127 229658 0 0 0
T129 0 20 0 0
T192 349095 0 0 0
T270 261280 18 0 0
T271 188109 0 0 0
T279 0 58 0 0
T283 48538 0 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3136 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 70 0 0
T41 0 80 0 0
T42 0 29 0 0
T43 0 86 0 0
T51 0 35 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 29 0 0
T123 0 15 0 0
T127 229658 0 0 0
T129 0 14 0 0
T192 349095 0 0 0
T270 261280 27 0 0
T271 188109 0 0 0
T279 0 85 0 0
T283 48538 0 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3142 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 93 0 0
T41 0 73 0 0
T42 0 20 0 0
T43 0 58 0 0
T51 0 33 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 50 0 0
T123 0 2 0 0
T127 229658 0 0 0
T129 0 23 0 0
T192 349095 0 0 0
T270 261280 31 0 0
T271 188109 0 0 0
T279 0 66 0 0
T283 48538 0 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3227 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 91 0 0
T41 0 74 0 0
T42 0 42 0 0
T43 0 62 0 0
T51 0 50 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 69 0 0
T123 0 25 0 0
T127 229658 0 0 0
T129 0 23 0 0
T192 349095 0 0 0
T270 261280 12 0 0
T271 188109 0 0 0
T279 0 89 0 0
T283 48538 0 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3299 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 57 0 0
T41 0 68 0 0
T42 0 58 0 0
T43 0 67 0 0
T51 0 30 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 56 0 0
T123 0 22 0 0
T127 229658 0 0 0
T129 0 20 0 0
T192 349095 0 0 0
T270 261280 25 0 0
T271 188109 0 0 0
T279 0 77 0 0
T283 48538 0 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3555 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 76 0 0
T41 0 83 0 0
T42 0 43 0 0
T43 0 47 0 0
T51 0 39 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 66 0 0
T123 0 15 0 0
T127 229658 0 0 0
T129 0 17 0 0
T192 349095 0 0 0
T270 261280 24 0 0
T271 188109 0 0 0
T279 0 47 0 0
T283 48538 0 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3642 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 95 0 0
T41 0 75 0 0
T42 0 60 0 0
T43 0 76 0 0
T51 0 44 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 58 0 0
T123 0 21 0 0
T127 229658 0 0 0
T129 0 15 0 0
T192 349095 0 0 0
T270 261280 20 0 0
T271 188109 0 0 0
T279 0 71 0 0
T283 48538 0 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3757 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 76 0 0
T41 0 99 0 0
T42 0 68 0 0
T43 0 60 0 0
T51 0 24 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 74 0 0
T123 0 31 0 0
T127 229658 0 0 0
T129 0 12 0 0
T192 349095 0 0 0
T270 261280 11 0 0
T271 188109 0 0 0
T279 0 75 0 0
T283 48538 0 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 1162 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T48 0 39 0 0
T51 0 56 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T123 0 37 0 0
T127 229658 0 0 0
T129 0 13 0 0
T140 0 17 0 0
T192 349095 0 0 0
T270 261280 13 0 0
T271 188109 0 0 0
T283 48538 0 0 0
T291 0 42 0 0
T306 0 26 0 0
T307 0 27 0 0
T308 0 27 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 1043 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T48 0 43 0 0
T51 0 50 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T123 0 15 0 0
T127 229658 0 0 0
T129 0 13 0 0
T140 0 6 0 0
T192 349095 0 0 0
T270 261280 39 0 0
T271 188109 0 0 0
T283 48538 0 0 0
T291 0 23 0 0
T306 0 25 0 0
T307 0 35 0 0
T308 0 11 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 965 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T48 0 33 0 0
T51 0 40 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T123 0 10 0 0
T127 229658 0 0 0
T129 0 11 0 0
T140 0 4 0 0
T192 349095 0 0 0
T270 261280 10 0 0
T271 188109 0 0 0
T283 48538 0 0 0
T291 0 48 0 0
T306 0 26 0 0
T307 0 23 0 0
T308 0 20 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 965 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T48 0 45 0 0
T51 0 25 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T123 0 8 0 0
T127 229658 0 0 0
T129 0 15 0 0
T140 0 3 0 0
T192 349095 0 0 0
T270 261280 20 0 0
T271 188109 0 0 0
T283 48538 0 0 0
T291 0 44 0 0
T306 0 19 0 0
T307 0 25 0 0
T308 0 22 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3706 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 69 0 0
T41 0 83 0 0
T42 0 58 0 0
T43 0 75 0 0
T51 0 46 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 63 0 0
T123 0 20 0 0
T127 229658 0 0 0
T129 0 26 0 0
T192 349095 0 0 0
T270 261280 24 0 0
T271 188109 0 0 0
T279 0 80 0 0
T283 48538 0 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3801 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 86 0 0
T41 0 74 0 0
T42 0 38 0 0
T43 0 57 0 0
T51 0 22 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 45 0 0
T123 0 21 0 0
T127 229658 0 0 0
T129 0 12 0 0
T192 349095 0 0 0
T270 261280 13 0 0
T271 188109 0 0 0
T279 0 74 0 0
T283 48538 0 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3484 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 80 0 0
T41 0 64 0 0
T42 0 33 0 0
T43 0 73 0 0
T51 0 42 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 61 0 0
T123 0 10 0 0
T127 229658 0 0 0
T129 0 13 0 0
T192 349095 0 0 0
T270 261280 19 0 0
T271 188109 0 0 0
T279 0 73 0 0
T283 48538 0 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3745 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 83 0 0
T41 0 63 0 0
T42 0 30 0 0
T43 0 70 0 0
T51 0 44 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 53 0 0
T123 0 8 0 0
T127 229658 0 0 0
T129 0 21 0 0
T192 349095 0 0 0
T270 261280 11 0 0
T271 188109 0 0 0
T279 0 91 0 0
T283 48538 0 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3714 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 84 0 0
T41 0 69 0 0
T42 0 43 0 0
T43 0 87 0 0
T51 0 45 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 72 0 0
T123 0 24 0 0
T127 229658 0 0 0
T129 0 13 0 0
T192 349095 0 0 0
T270 261280 20 0 0
T271 188109 0 0 0
T279 0 65 0 0
T283 48538 0 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3672 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 55 0 0
T41 0 78 0 0
T42 0 32 0 0
T43 0 66 0 0
T51 0 38 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 48 0 0
T123 0 13 0 0
T127 229658 0 0 0
T129 0 30 0 0
T192 349095 0 0 0
T270 261280 18 0 0
T271 188109 0 0 0
T279 0 60 0 0
T283 48538 0 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3574 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 69 0 0
T41 0 67 0 0
T42 0 37 0 0
T43 0 81 0 0
T51 0 44 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 54 0 0
T123 0 10 0 0
T127 229658 0 0 0
T129 0 3 0 0
T192 349095 0 0 0
T270 261280 19 0 0
T271 188109 0 0 0
T279 0 40 0 0
T283 48538 0 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3969 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T40 0 68 0 0
T41 0 68 0 0
T42 0 65 0 0
T43 0 59 0 0
T51 0 36 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T87 0 53 0 0
T123 0 24 0 0
T127 229658 0 0 0
T129 0 28 0 0
T192 349095 0 0 0
T270 261280 28 0 0
T271 188109 0 0 0
T279 0 93 0 0
T283 48538 0 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 1726 0 0
T10 117201 0 0 0
T25 837557 2 0 0
T41 0 1 0 0
T43 0 4 0 0
T51 0 45 0 0
T58 57883 0 0 0
T70 851721 4 0 0
T80 25649 0 0 0
T81 62970 0 0 0
T87 0 11 0 0
T90 44748 0 0 0
T122 0 1 0 0
T123 0 2 0 0
T143 53383 0 0 0
T144 199922 0 0 0
T145 193409 0 0 0
T270 0 17 0 0
T309 0 3 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 1515 0 0
T10 117201 0 0 0
T25 837557 0 0 0
T26 157058 11 0 0
T48 0 42 0 0
T51 0 25 0 0
T58 57883 0 0 0
T70 851721 0 0 0
T80 25649 0 0 0
T90 44748 0 0 0
T123 0 12 0 0
T129 0 27 0 0
T140 0 18 0 0
T143 53383 0 0 0
T144 199922 0 0 0
T145 193409 0 0 0
T167 0 11 0 0
T270 0 10 0 0
T306 0 20 0 0
T307 0 15 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3103 0 0
T10 117201 0 0 0
T11 0 4 0 0
T25 837557 99 0 0
T48 0 54 0 0
T51 0 40 0 0
T58 57883 0 0 0
T59 79937 0 0 0
T74 240560 0 0 0
T75 236110 0 0 0
T80 25649 0 0 0
T81 62970 0 0 0
T90 44748 0 0 0
T91 107871 0 0 0
T123 0 13 0 0
T129 0 24 0 0
T150 0 1 0 0
T167 0 8 0 0
T205 0 1 0 0
T270 0 11 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 1040 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T48 0 31 0 0
T51 0 42 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T123 0 24 0 0
T127 229658 0 0 0
T129 0 22 0 0
T192 349095 0 0 0
T270 261280 21 0 0
T271 188109 0 0 0
T283 48538 0 0 0
T291 0 21 0 0
T306 0 16 0 0
T307 0 16 0 0
T308 0 22 0 0
T310 0 8 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 4347 0 0
T7 60434 0 0 0
T8 124038 0 0 0
T19 54652 56 0 0
T20 202906 0 0 0
T26 0 77 0 0
T27 30541 0 0 0
T28 309864 0 0 0
T32 109143 0 0 0
T48 0 42 0 0
T51 0 88 0 0
T63 207012 0 0 0
T64 56104 0 0 0
T65 91398 0 0 0
T123 0 14 0 0
T124 0 71 0 0
T129 0 18 0 0
T237 0 53 0 0
T270 0 15 0 0
T311 0 75 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 5108 0 0
T10 117201 0 0 0
T11 81852 0 0 0
T51 0 109 0 0
T58 57883 0 0 0
T59 79937 0 0 0
T74 240560 0 0 0
T75 236110 0 0 0
T80 25649 62 0 0
T81 62970 0 0 0
T82 0 62 0 0
T91 107871 0 0 0
T123 0 28 0 0
T129 0 84 0 0
T139 0 51 0 0
T270 0 17 0 0
T296 540734 0 0 0
T312 0 44 0 0
T313 0 67 0 0
T314 0 75 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 3697 0 0
T10 117201 0 0 0
T11 81852 0 0 0
T51 0 131 0 0
T58 57883 0 0 0
T59 79937 0 0 0
T74 240560 0 0 0
T75 236110 0 0 0
T80 25649 63 0 0
T81 62970 0 0 0
T82 0 90 0 0
T91 107871 0 0 0
T123 0 8 0 0
T129 0 83 0 0
T139 0 43 0 0
T270 0 21 0 0
T296 540734 0 0 0
T312 0 48 0 0
T313 0 84 0 0
T314 0 40 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 4104 0 0
T10 117201 0 0 0
T11 81852 0 0 0
T51 0 63 0 0
T58 57883 0 0 0
T59 79937 0 0 0
T74 240560 0 0 0
T75 236110 0 0 0
T80 25649 74 0 0
T81 62970 0 0 0
T82 0 60 0 0
T91 107871 0 0 0
T123 0 23 0 0
T129 0 84 0 0
T139 0 75 0 0
T270 0 11 0 0
T296 540734 0 0 0
T312 0 36 0 0
T313 0 96 0 0
T314 0 33 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 1139 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T48 0 37 0 0
T51 0 36 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T84 288298 0 0 0
T123 0 12 0 0
T127 229658 0 0 0
T129 0 9 0 0
T140 0 9 0 0
T192 349095 0 0 0
T270 261280 22 0 0
T271 188109 0 0 0
T283 48538 0 0 0
T291 0 31 0 0
T306 0 22 0 0
T307 0 15 0 0
T308 0 27 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 1177 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T48 0 55 0 0
T51 0 48 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T69 0 11 0 0
T84 288298 0 0 0
T106 0 1 0 0
T123 0 28 0 0
T127 229658 0 0 0
T129 0 30 0 0
T140 0 8 0 0
T192 349095 0 0 0
T270 261280 24 0 0
T271 188109 0 0 0
T283 48538 0 0 0
T315 0 1 0 0
T316 0 3 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 1067 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T48 0 25 0 0
T51 0 42 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T69 0 7 0 0
T84 288298 0 0 0
T106 0 2 0 0
T123 0 12 0 0
T127 229658 0 0 0
T129 0 26 0 0
T130 0 4 0 0
T192 349095 0 0 0
T270 261280 28 0 0
T271 188109 0 0 0
T283 48538 0 0 0
T315 0 4 0 0
T317 0 5 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 1153 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T48 0 33 0 0
T51 0 35 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T69 0 6 0 0
T84 288298 0 0 0
T123 0 11 0 0
T127 229658 0 0 0
T129 0 23 0 0
T130 0 6 0 0
T192 349095 0 0 0
T270 261280 9 0 0
T271 188109 0 0 0
T283 48538 0 0 0
T315 0 5 0 0
T316 0 3 0 0
T317 0 5 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1222336775 1177 0 0
T31 500936 0 0 0
T38 215289 0 0 0
T48 0 50 0 0
T51 0 40 0 0
T53 217836 0 0 0
T60 321380 0 0 0
T69 0 9 0 0
T84 288298 0 0 0
T123 0 19 0 0
T127 229658 0 0 0
T129 0 12 0 0
T130 0 3 0 0
T140 0 22 0 0
T192 349095 0 0 0
T270 261280 28 0 0
T271 188109 0 0 0
T283 48538 0 0 0
T315 0 2 0 0
T316 0 11 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%